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Fix various binutils testsuite failures.
[deliverable/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
4670103e 27#ifndef MAX_INSN_ARGS
4eb6f892 28#define MAX_INSN_ARGS 16
4670103e
CZ		 29#endif
30
31#ifndef MAX_INSN_FLGS
886a2506 32#define MAX_INSN_FLGS 3
4670103e 33#endif
886a2506
NC		 34
35/* Instruction Class. */
36typedef enum
37 {
38 ARITH,
39 AUXREG,
40 BRANCH,
41 CONTROL,
42 DSP,
43 FLOAT,
44 INVALID,
45 JUMP,
46 KERNEL,
47 LOGICAL,
48 MEMORY,
e23e8ebe 49 BITOP,
c8f785f2
AB		 50 NET,
51 ACL,
9ba75c88 52 DPI,
886a2506
NC		 53 } insn_class_t;
54
55/* Instruction Subclass. */
56typedef enum
57 {
58 NONE,
59 CVT,
60 BTSCN,
61 CD1,
62 CD2,
d9eca1df 63 COND,
886a2506
NC		 64 DIV,
65 DP,
8ddf6b2a
CZ		 66 DPA,
67 DPX,
886a2506
NC		 68 MPY1E,
69 MPY6E,
70 MPY7E,
71 MPY8E,
72 MPY9E,
bdd582db 73 NPS400,
f2dd8838 74 QUARKSE,
886a2506
NC		 75 SHFT1,
76 SHFT2,
77 SWAP,
8ddf6b2a
CZ		 78 SP,
79 SPX
886a2506
NC		 80 } insn_subclass_t;
81
82/* Flags class. */
83typedef enum
84 {
f36e33da 85 F_CLASS_NONE = 0,
1ae8ab47
AB		 86
87 /* At most one flag from the set of flags can appear in the
88 instruction. */
f36e33da 89 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47
AB		 90
91 /* Exactly one from from the set of flags must appear in the
92 instruction. */
f36e33da
CZ		 93 F_CLASS_REQUIRED = (1 << 1),
94
95 /* The conditional code can be extended over the standard variants
96 via .extCondCode pseudo-op. */
d9eca1df
CZ		 97 F_CLASS_EXTEND = (1 << 2),
98
99 /* Condition code flag. */
100 F_CLASS_COND = (1 << 3)
886a2506
NC		 101 } flag_class_t;
102
103/* The opcode table is an array of struct arc_opcode. */
104struct arc_opcode
105{
106 /* The opcode name. */
107 const char *name;
108
109 /* The opcode itself. Those bits which will be filled in with
110 operands are zeroes. */
111 unsigned opcode;
112
113 /* The opcode mask. This is used by the disassembler. This is a
114 mask containing ones indicating those bits which must match the
115 opcode field, and zeroes indicating those bits which need not
116 match (and are presumably filled in by operands). */
117 unsigned mask;
118
119 /* One bit flags for the opcode. These are primarily used to
120 indicate specific processors and environments support the
121 instructions. The defined values are listed below. */
122 unsigned cpu;
123
124 /* The instruction class. This is used by gdb. */
c810e0b8 125 insn_class_t insn_class;
886a2506
NC		 126
127 /* The instruction subclass. */
128 insn_subclass_t subclass;
129
130 /* An array of operand codes. Each code is an index into the
131 operand table. They appear in the order which the operands must
132 appear in assembly code, and are terminated by a zero. */
133 unsigned char operands[MAX_INSN_ARGS + 1];
134
135 /* An array of flag codes. Each code is an index into the flag
136 table. They appear in the order which the flags must appear in
137 assembly code, and are terminated by a zero. */
138 unsigned char flags[MAX_INSN_FLGS + 1];
139};
252b5132 140
4eb6f892
AB		 141/* Structure used to describe 48 and 64 bit instructions. */
142struct arc_long_opcode
143{
144 /* The base instruction is either 16 or 32 bits, and is described like a
145 normal instruction. */
146 struct arc_opcode base_opcode;
147
148 /* The template value for the 32-bit LIMM extension. Used by the
149 assembler and disassembler in the same way as the 'opcode' field of
150 'struct arc_opcode'. */
151 unsigned limm_template;
152
153 /* The mask value for the 32-bit LIMM extension. Used by the
154 disassembler just like the 'mask' field in 'struct arc_opcode'. */
155 unsigned limm_mask;
156
157 /* Array of operand codes similar to the 'operands' array in 'struct
158 arc_opcode'. These operands are used to fill in the LIMM value. */
159 unsigned char operands[MAX_INSN_ARGS + 1];
160};
161
162extern const struct arc_long_opcode arc_long_opcodes[];
163extern const unsigned arc_num_long_opcodes;
164
886a2506
NC		 165/* The table itself is sorted by major opcode number, and is otherwise
166 in the order in which the disassembler should consider
167 instructions. */
168extern const struct arc_opcode arc_opcodes[];
886a2506
NC		 169
170/* CPU Availability. */
f36e33da 171#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 172#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
173#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
174#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
175#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
176
f36e33da
CZ		 177/* CPU combi. */
178#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
179 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
180#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
181
886a2506
NC		 182/* CPU extensions. */
183#define ARC_EA 0x0001
184#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
185#define ARC_LLOCK 0x0002
186#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
187#define ARC_MPY 0x0004
188#define ARC_MULT 0x0004
bdd582db 189#define ARC_NPS400 0x0008
886a2506
NC		 190
191/* Floating point support. */
192#define ARC_DPFP 0x0010
193#define ARC_SPFP 0x0020
194#define ARC_FPU 0x0030
8ddf6b2a 195#define ARC_FPUDA 0x0040
886a2506
NC		 196
197/* NORM & SWAP. */
198#define ARC_SWAP 0x0100
199#define ARC_NORM 0x0200
200#define ARC_BSCAN 0x0200
201
202/* A7 specific. */
203#define ARC_UIX 0x1000
204#define ARC_TSTAMP 0x1000
205
206/* A6 specific. */
207#define ARC_VBFDW 0x1000
208#define ARC_BARREL 0x1000
209#define ARC_DSPA 0x1000
210
211/* EM specific. */
212#define ARC_SHIFT 0x1000
213
214/* V2 specific. */
215#define ARC_INTR 0x1000
216#define ARC_DIV 0x1000
217
218/* V1 specific. */
219#define ARC_XMAC 0x1000
220#define ARC_CRC 0x1000
221
886a2506
NC		 222/* A macro to check for short instructions. */
223#define ARC_SHORT(mask) \
224 (((mask) & 0xFFFF0000) ? 0 : 1)
225
226/* The operands table is an array of struct arc_operand. */
227struct arc_operand
228{
229 /* The number of bits in the operand. */
230 unsigned int bits;
231
232 /* How far the operand is left shifted in the instruction. */
233 unsigned int shift;
234
235 /* The default relocation type for this operand. */
236 signed int default_reloc;
237
238 /* One bit syntax flags. */
239 unsigned int flags;
240
241 /* Insertion function. This is used by the assembler. To insert an
242 operand value into an instruction, check this field.
243
244 If it is NULL, execute
245 i |= (op & ((1 << o->bits) - 1)) << o->shift;
246 (i is the instruction which we are filling in, o is a pointer to
247 this structure, and op is the opcode value; this assumes twos
248 complement arithmetic).
249
250 If this field is not NULL, then simply call it with the
251 instruction and the operand value. It will return the new value
252 of the instruction. If the ERRMSG argument is not NULL, then if
253 the operand value is illegal, *ERRMSG will be set to a warning
254 string (the operand will be inserted in any case). If the
255 operand value is legal, *ERRMSG will be unchanged (most operands
256 can accept any value). */
257 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
258
259 /* Extraction function. This is used by the disassembler. To
260 extract this operand type from an instruction, check this field.
261
262 If it is NULL, compute
263 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
264 if ((o->flags & ARC_OPERAND_SIGNED) != 0
265 && (op & (1 << (o->bits - 1))) != 0)
266 op -= 1 << o->bits;
267 (i is the instruction, o is a pointer to this structure, and op
268 is the result; this assumes twos complement arithmetic).
269
270 If this field is not NULL, then simply call it with the
271 instruction value. It will return the value of the operand. If
272 the INVALID argument is not NULL, *INVALID will be set to
273 TRUE if this operand type can not actually be extracted from
274 this operand (i.e., the instruction does not match). If the
275 operand is valid, *INVALID will not be changed. */
276 int (*extract) (unsigned instruction, bfd_boolean *invalid);
277};
0d2bcfaf 278
886a2506
NC		 279/* Elements in the table are retrieved by indexing with values from
280 the operands field of the arc_opcodes table. */
281extern const struct arc_operand arc_operands[];
282extern const unsigned arc_num_operands;
283extern const unsigned arc_Toperand;
284extern const unsigned arc_NToperand;
252b5132 285
886a2506 286/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 287
886a2506
NC		 288/* This operand does not actually exist in the assembler input. This
289 is used to support extended mnemonics, for which two operands fields
290 are identical. The assembler should call the insert function with
291 any op value. The disassembler should call the extract function,
292 ignore the return value, and check the value placed in the invalid
293 argument. */
294#define ARC_OPERAND_FAKE 0x0001
252b5132 295
886a2506
NC		 296/* This operand names an integer register. */
297#define ARC_OPERAND_IR 0x0002
0d2bcfaf 298
886a2506
NC		 299/* This operand takes signed values. */
300#define ARC_OPERAND_SIGNED 0x0004
252b5132 301
886a2506
NC		 302/* This operand takes unsigned values. This exists primarily so that
303 a flags value of 0 can be treated as end-of-arguments. */
304#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 305
886a2506
NC		 306/* This operand takes long immediate values. */
307#define ARC_OPERAND_LIMM 0x0010
252b5132 308
886a2506
NC		 309/* This operand is identical like the previous one. */
310#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 311
886a2506
NC		 312/* This operand is PC relative. Used for internal relocs. */
313#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 314
886a2506
NC		 315/* This operand is truncated. The truncation is done accordingly to
316 operand alignment attribute. */
317#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 318
886a2506
NC		 319/* This operand is 16bit aligned. */
320#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 321
886a2506
NC		 322/* This operand is 32bit aligned. */
323#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 324
886a2506
NC		 325/* This operand can be ignored by matching process if it is not
326 present. */
327#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 328
886a2506
NC		 329/* Don't check the range when matching. */
330#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 331
886a2506
NC		 332/* Mark the braket possition. */
333#define ARC_OPERAND_BRAKET 0x1000
252b5132 334
886a2506
NC		 335/* Mask for selecting the type for typecheck purposes. */
336#define ARC_OPERAND_TYPECHECK_MASK \
337 (ARC_OPERAND_IR | \
338 ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
339 ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
252b5132 340
886a2506
NC		 341/* The flags structure. */
342struct arc_flag_operand
343{
344 /* The flag name. */
345 const char *name;
0d2bcfaf 346
886a2506
NC		 347 /* The flag code. */
348 unsigned code;
252b5132 349
886a2506
NC		 350 /* The number of bits in the operand. */
351 unsigned int bits;
252b5132 352
886a2506
NC		 353 /* How far the operand is left shifted in the instruction. */
354 unsigned int shift;
252b5132 355
886a2506
NC		 356 /* Available for disassembler. */
357 unsigned char favail;
84037f8c
KD		 358};
359
886a2506
NC		 360/* The flag operands table. */
361extern const struct arc_flag_operand arc_flag_operands[];
362extern const unsigned arc_num_flag_operands;
0d2bcfaf 363
886a2506
NC		 364/* The flag's class structure. */
365struct arc_flag_class
366{
367 /* Flag class. */
c810e0b8 368 flag_class_t flag_class;
252b5132 369
886a2506
NC		 370 /* List of valid flags (codes). */
371 unsigned flags[256];
372};
252b5132 373
886a2506 374extern const struct arc_flag_class arc_flag_classes[];
252b5132 375
886a2506
NC		 376/* Structure for special cases. */
377struct arc_flag_special
378{
379 /* Name of special case instruction. */
380 const char *name;
252b5132 381
886a2506
NC		 382 /* List of flags applicable for special case instruction. */
383 unsigned flags[32];
384};
252b5132 385
886a2506
NC		 386extern const struct arc_flag_special arc_flag_special_cases[];
387extern const unsigned arc_num_flag_special;
388
389/* Relocation equivalence structure. */
390struct arc_reloc_equiv_tab
391{
392 const char * name; /* String to lookup. */
393 const char * mnemonic; /* Extra matching condition. */
24b368f8 394 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 395 signed int oldreloc; /* Old relocation. */
396 signed int newreloc; /* New relocation. */
397};
252b5132 398
886a2506
NC		 399extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
400extern const unsigned arc_num_equiv_tab;
252b5132 401
886a2506
NC		 402/* Structure for operand operations for pseudo/alias instructions. */
403struct arc_operand_operation
404{
405 /* The index for operand from operand array. */
406 unsigned operand_idx;
252b5132 407
886a2506
NC		 408 /* Defines if it needs the operand inserted by the assembler or
409 whether this operand comes from the pseudo instruction's
410 operands. */
411 unsigned char needs_insert;
252b5132 412
886a2506
NC		 413 /* Count we have to add to the operand. Use negative number to
414 subtract from the operand. Also use this number to add to 0 if
415 the operand needs to be inserted (i.e. needs_insert == 1). */
416 int count;
252b5132 417
886a2506
NC		 418 /* Index of the operand to swap with. To be done AFTER applying
419 inc_count. */
420 unsigned swap_operand_idx;
252b5132
RH		 421};
422
886a2506
NC		 423/* Structure for pseudo/alias instructions. */
424struct arc_pseudo_insn
425{
426 /* Mnemonic for pseudo/alias insn. */
427 const char *mnemonic_p;
252b5132 428
886a2506
NC		 429 /* Mnemonic for real instruction. */
430 const char *mnemonic_r;
252b5132 431
886a2506
NC		 432 /* Flag that will have to be added (if any). */
433 const char *flag_r;
252b5132 434
886a2506
NC		 435 /* Amount of operands. */
436 unsigned operand_cnt;
252b5132 437
886a2506
NC		 438 /* Array of operand operations. */
439 struct arc_operand_operation operand[6];
440};
252b5132 441
886a2506
NC		 442extern const struct arc_pseudo_insn arc_pseudo_insns[];
443extern const unsigned arc_num_pseudo_insn;
252b5132 444
886a2506
NC		 445/* Structure for AUXILIARY registers. */
446struct arc_aux_reg
447{
448 /* Register address. */
449 int address;
252b5132 450
f36e33da
CZ		 451 /* One bit flags for the opcode. These are primarily used to
452 indicate specific processors and environments support the
453 instructions. */
454 unsigned cpu;
455
8ddf6b2a
CZ		 456 /* AUX register subclass. */
457 insn_subclass_t subclass;
458
459 /* Register name. */
886a2506
NC		 460 const char *name;
461
462 /* Size of the string. */
463 size_t length;
464};
465
466extern const struct arc_aux_reg arc_aux_regs[];
467extern const unsigned arc_num_aux_regs;
468
4670103e
CZ		 469extern const struct arc_opcode arc_relax_opcodes[];
470extern const unsigned arc_num_relax_opcodes;
471
4b0c052e
AB		 472/* Macro used for generating one class of NPS instructions. */
473#define NPS_CMEM_HIGH_VALUE 0x57f0
474
f2dd8838
CZ		 475/* Macros to help generating regular pattern instructions. */
476#define FIELDA(word) (word & 0x3F)
477#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
478#define FIELDC(word) ((word & 0x3F) << 6)
479#define FIELDF (0x01 << 15)
480#define FIELDQ (0x1F)
481
482#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
483#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
484#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
485
486#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
487#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
488#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
489#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
490#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
491#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
492#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
493#define INSN3OP_0LL(MOP,SOP) \
494 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
495#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
496#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
497#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
498#define INSN3OP_0LU(MOP,SOP) \
499 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
500#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
501#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
502#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
503#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
504#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
505#define INSN3OP_C0LL(MOP,SOP) \
506 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
507#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
508#define INSN3OP_C0LU(MOP,SOP) \
509 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
510
511#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
512#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
513#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
514#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
515#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
516#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
517#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
518#define MINSN3OP_0LL (~(FIELDF))
519#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
520#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
521#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
522#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
523#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
524#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
525#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
526#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
527#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
528#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
529#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
530#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
531
532#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
533#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
534#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
535#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
536#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
537#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
538
539#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
540#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
541#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
542#define MINSN2OP_0L (~(FIELDF))
543#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
544#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
545
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CZ		 546/* Various constants used when defining an extension instruction. */
547#define ARC_SYNTAX_3OP (1 << 0)
548#define ARC_SYNTAX_2OP (1 << 1)
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CZ		 549#define ARC_SYNTAX_1OP (1 << 2)
550#define ARC_SYNTAX_NOP (1 << 3)
551#define ARC_SYNTAX_MASK (0x0F)
552
553#define ARC_OP1_MUST_BE_IMM (1 << 0)
554#define ARC_OP1_IMM_IMPLIED (1 << 1)
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CZ		 555
556#define ARC_SUFFIX_NONE (1 << 0)
557#define ARC_SUFFIX_COND (1 << 1)
558#define ARC_SUFFIX_FLAG (1 << 2)
559
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CZ		 560#define ARC_REGISTER_READONLY (1 << 0)
561#define ARC_REGISTER_WRITEONLY (1 << 1)
562#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
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CZ		 563
564/* Constants needed to initialize extension instructions. */
565extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
566extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
567extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
568extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
569
570extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
571extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
572extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
573extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
574extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
575extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
576extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
577extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
578extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
579extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
580extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
581extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
582
583extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
584extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
585extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
586
587extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
588extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
589extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
590
591extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
592extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
593extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
594extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
595extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
597
598extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
599extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
600extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
601extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
602
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CZ		 603extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
604extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
605extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
606
886a2506 607#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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