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[deliverable/binutils-gdb.git] / include / opcode / arc.h
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252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
4670103e 27#ifndef MAX_INSN_ARGS
886a2506 28#define MAX_INSN_ARGS 6
4670103e
CZ		 29#endif
30
31#ifndef MAX_INSN_FLGS
886a2506 32#define MAX_INSN_FLGS 3
4670103e 33#endif
886a2506
NC		 34
35/* Instruction Class. */
36typedef enum
37 {
38 ARITH,
39 AUXREG,
40 BRANCH,
41 CONTROL,
42 DSP,
43 FLOAT,
44 INVALID,
45 JUMP,
46 KERNEL,
47 LOGICAL,
48 MEMORY,
e23e8ebe 49 BITOP,
886a2506
NC		 50 } insn_class_t;
51
52/* Instruction Subclass. */
53typedef enum
54 {
55 NONE,
56 CVT,
57 BTSCN,
58 CD1,
59 CD2,
60 DIV,
61 DP,
8ddf6b2a
CZ		 62 DPA,
63 DPX,
886a2506
NC		 64 MPY1E,
65 MPY6E,
66 MPY7E,
67 MPY8E,
68 MPY9E,
f2dd8838 69 QUARKSE,
886a2506
NC		 70 SHFT1,
71 SHFT2,
72 SWAP,
8ddf6b2a
CZ		 73 SP,
74 SPX
886a2506
NC		 75 } insn_subclass_t;
76
77/* Flags class. */
78typedef enum
79 {
f36e33da 80 F_CLASS_NONE = 0,
1ae8ab47
AB		 81
82 /* At most one flag from the set of flags can appear in the
83 instruction. */
f36e33da 84 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47
AB		 85
86 /* Exactly one from from the set of flags must appear in the
87 instruction. */
f36e33da
CZ		 88 F_CLASS_REQUIRED = (1 << 1),
89
90 /* The conditional code can be extended over the standard variants
91 via .extCondCode pseudo-op. */
92 F_CLASS_EXTEND = (1 << 2)
886a2506
NC		 93 } flag_class_t;
94
95/* The opcode table is an array of struct arc_opcode. */
96struct arc_opcode
97{
98 /* The opcode name. */
99 const char *name;
100
101 /* The opcode itself. Those bits which will be filled in with
102 operands are zeroes. */
103 unsigned opcode;
104
105 /* The opcode mask. This is used by the disassembler. This is a
106 mask containing ones indicating those bits which must match the
107 opcode field, and zeroes indicating those bits which need not
108 match (and are presumably filled in by operands). */
109 unsigned mask;
110
111 /* One bit flags for the opcode. These are primarily used to
112 indicate specific processors and environments support the
113 instructions. The defined values are listed below. */
114 unsigned cpu;
115
116 /* The instruction class. This is used by gdb. */
117 insn_class_t class;
118
119 /* The instruction subclass. */
120 insn_subclass_t subclass;
121
122 /* An array of operand codes. Each code is an index into the
123 operand table. They appear in the order which the operands must
124 appear in assembly code, and are terminated by a zero. */
125 unsigned char operands[MAX_INSN_ARGS + 1];
126
127 /* An array of flag codes. Each code is an index into the flag
128 table. They appear in the order which the flags must appear in
129 assembly code, and are terminated by a zero. */
130 unsigned char flags[MAX_INSN_FLGS + 1];
131};
252b5132 132
886a2506
NC		 133/* The table itself is sorted by major opcode number, and is otherwise
134 in the order in which the disassembler should consider
135 instructions. */
136extern const struct arc_opcode arc_opcodes[];
886a2506
NC		 137
138/* CPU Availability. */
f36e33da 139#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 140#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
141#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
142#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
143#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e 144#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 145
f36e33da
CZ		 146/* CPU combi. */
147#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
148 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
149#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
150
886a2506
NC		 151/* CPU extensions. */
152#define ARC_EA 0x0001
153#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
154#define ARC_LLOCK 0x0002
155#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
156#define ARC_MPY 0x0004
157#define ARC_MULT 0x0004
158
159/* Floating point support. */
160#define ARC_DPFP 0x0010
161#define ARC_SPFP 0x0020
162#define ARC_FPU 0x0030
8ddf6b2a 163#define ARC_FPUDA 0x0040
886a2506
NC		 164
165/* NORM & SWAP. */
166#define ARC_SWAP 0x0100
167#define ARC_NORM 0x0200
168#define ARC_BSCAN 0x0200
169
170/* A7 specific. */
171#define ARC_UIX 0x1000
172#define ARC_TSTAMP 0x1000
173
174/* A6 specific. */
175#define ARC_VBFDW 0x1000
176#define ARC_BARREL 0x1000
177#define ARC_DSPA 0x1000
178
179/* EM specific. */
180#define ARC_SHIFT 0x1000
181
182/* V2 specific. */
183#define ARC_INTR 0x1000
184#define ARC_DIV 0x1000
185
186/* V1 specific. */
187#define ARC_XMAC 0x1000
188#define ARC_CRC 0x1000
189
886a2506
NC		 190/* A macro to check for short instructions. */
191#define ARC_SHORT(mask) \
192 (((mask) & 0xFFFF0000) ? 0 : 1)
193
194/* The operands table is an array of struct arc_operand. */
195struct arc_operand
196{
197 /* The number of bits in the operand. */
198 unsigned int bits;
199
200 /* How far the operand is left shifted in the instruction. */
201 unsigned int shift;
202
203 /* The default relocation type for this operand. */
204 signed int default_reloc;
205
206 /* One bit syntax flags. */
207 unsigned int flags;
208
209 /* Insertion function. This is used by the assembler. To insert an
210 operand value into an instruction, check this field.
211
212 If it is NULL, execute
213 i |= (op & ((1 << o->bits) - 1)) << o->shift;
214 (i is the instruction which we are filling in, o is a pointer to
215 this structure, and op is the opcode value; this assumes twos
216 complement arithmetic).
217
218 If this field is not NULL, then simply call it with the
219 instruction and the operand value. It will return the new value
220 of the instruction. If the ERRMSG argument is not NULL, then if
221 the operand value is illegal, *ERRMSG will be set to a warning
222 string (the operand will be inserted in any case). If the
223 operand value is legal, *ERRMSG will be unchanged (most operands
224 can accept any value). */
225 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
226
227 /* Extraction function. This is used by the disassembler. To
228 extract this operand type from an instruction, check this field.
229
230 If it is NULL, compute
231 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
232 if ((o->flags & ARC_OPERAND_SIGNED) != 0
233 && (op & (1 << (o->bits - 1))) != 0)
234 op -= 1 << o->bits;
235 (i is the instruction, o is a pointer to this structure, and op
236 is the result; this assumes twos complement arithmetic).
237
238 If this field is not NULL, then simply call it with the
239 instruction value. It will return the value of the operand. If
240 the INVALID argument is not NULL, *INVALID will be set to
241 TRUE if this operand type can not actually be extracted from
242 this operand (i.e., the instruction does not match). If the
243 operand is valid, *INVALID will not be changed. */
244 int (*extract) (unsigned instruction, bfd_boolean *invalid);
245};
0d2bcfaf 246
886a2506
NC		 247/* Elements in the table are retrieved by indexing with values from
248 the operands field of the arc_opcodes table. */
249extern const struct arc_operand arc_operands[];
250extern const unsigned arc_num_operands;
251extern const unsigned arc_Toperand;
252extern const unsigned arc_NToperand;
252b5132 253
886a2506 254/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 255
886a2506
NC		 256/* This operand does not actually exist in the assembler input. This
257 is used to support extended mnemonics, for which two operands fields
258 are identical. The assembler should call the insert function with
259 any op value. The disassembler should call the extract function,
260 ignore the return value, and check the value placed in the invalid
261 argument. */
262#define ARC_OPERAND_FAKE 0x0001
252b5132 263
886a2506
NC		 264/* This operand names an integer register. */
265#define ARC_OPERAND_IR 0x0002
0d2bcfaf 266
886a2506
NC		 267/* This operand takes signed values. */
268#define ARC_OPERAND_SIGNED 0x0004
252b5132 269
886a2506
NC		 270/* This operand takes unsigned values. This exists primarily so that
271 a flags value of 0 can be treated as end-of-arguments. */
272#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 273
886a2506
NC		 274/* This operand takes long immediate values. */
275#define ARC_OPERAND_LIMM 0x0010
252b5132 276
886a2506
NC		 277/* This operand is identical like the previous one. */
278#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 279
886a2506
NC		 280/* This operand is PC relative. Used for internal relocs. */
281#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 282
886a2506
NC		 283/* This operand is truncated. The truncation is done accordingly to
284 operand alignment attribute. */
285#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 286
886a2506
NC		 287/* This operand is 16bit aligned. */
288#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 289
886a2506
NC		 290/* This operand is 32bit aligned. */
291#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 292
886a2506
NC		 293/* This operand can be ignored by matching process if it is not
294 present. */
295#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 296
886a2506
NC		 297/* Don't check the range when matching. */
298#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 299
886a2506
NC		 300/* Mark the braket possition. */
301#define ARC_OPERAND_BRAKET 0x1000
252b5132 302
886a2506
NC		 303/* Mask for selecting the type for typecheck purposes. */
304#define ARC_OPERAND_TYPECHECK_MASK \
305 (ARC_OPERAND_IR | \
306 ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
307 ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
252b5132 308
886a2506
NC		 309/* The flags structure. */
310struct arc_flag_operand
311{
312 /* The flag name. */
313 const char *name;
0d2bcfaf 314
886a2506
NC		 315 /* The flag code. */
316 unsigned code;
252b5132 317
886a2506
NC		 318 /* The number of bits in the operand. */
319 unsigned int bits;
252b5132 320
886a2506
NC		 321 /* How far the operand is left shifted in the instruction. */
322 unsigned int shift;
252b5132 323
886a2506
NC		 324 /* Available for disassembler. */
325 unsigned char favail;
84037f8c
KD		 326};
327
886a2506
NC		 328/* The flag operands table. */
329extern const struct arc_flag_operand arc_flag_operands[];
330extern const unsigned arc_num_flag_operands;
0d2bcfaf 331
886a2506
NC		 332/* The flag's class structure. */
333struct arc_flag_class
334{
335 /* Flag class. */
336 flag_class_t class;
252b5132 337
886a2506
NC		 338 /* List of valid flags (codes). */
339 unsigned flags[256];
340};
252b5132 341
886a2506 342extern const struct arc_flag_class arc_flag_classes[];
252b5132 343
886a2506
NC		 344/* Structure for special cases. */
345struct arc_flag_special
346{
347 /* Name of special case instruction. */
348 const char *name;
252b5132 349
886a2506
NC		 350 /* List of flags applicable for special case instruction. */
351 unsigned flags[32];
352};
252b5132 353
886a2506
NC		 354extern const struct arc_flag_special arc_flag_special_cases[];
355extern const unsigned arc_num_flag_special;
356
357/* Relocation equivalence structure. */
358struct arc_reloc_equiv_tab
359{
360 const char * name; /* String to lookup. */
361 const char * mnemonic; /* Extra matching condition. */
24b368f8 362 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 363 signed int oldreloc; /* Old relocation. */
364 signed int newreloc; /* New relocation. */
365};
252b5132 366
886a2506
NC		 367extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
368extern const unsigned arc_num_equiv_tab;
252b5132 369
886a2506
NC		 370/* Structure for operand operations for pseudo/alias instructions. */
371struct arc_operand_operation
372{
373 /* The index for operand from operand array. */
374 unsigned operand_idx;
252b5132 375
886a2506
NC		 376 /* Defines if it needs the operand inserted by the assembler or
377 whether this operand comes from the pseudo instruction's
378 operands. */
379 unsigned char needs_insert;
252b5132 380
886a2506
NC		 381 /* Count we have to add to the operand. Use negative number to
382 subtract from the operand. Also use this number to add to 0 if
383 the operand needs to be inserted (i.e. needs_insert == 1). */
384 int count;
252b5132 385
886a2506
NC		 386 /* Index of the operand to swap with. To be done AFTER applying
387 inc_count. */
388 unsigned swap_operand_idx;
252b5132
RH		 389};
390
886a2506
NC		 391/* Structure for pseudo/alias instructions. */
392struct arc_pseudo_insn
393{
394 /* Mnemonic for pseudo/alias insn. */
395 const char *mnemonic_p;
252b5132 396
886a2506
NC		 397 /* Mnemonic for real instruction. */
398 const char *mnemonic_r;
252b5132 399
886a2506
NC		 400 /* Flag that will have to be added (if any). */
401 const char *flag_r;
252b5132 402
886a2506
NC		 403 /* Amount of operands. */
404 unsigned operand_cnt;
252b5132 405
886a2506
NC		 406 /* Array of operand operations. */
407 struct arc_operand_operation operand[6];
408};
252b5132 409
886a2506
NC		 410extern const struct arc_pseudo_insn arc_pseudo_insns[];
411extern const unsigned arc_num_pseudo_insn;
252b5132 412
886a2506
NC		 413/* Structure for AUXILIARY registers. */
414struct arc_aux_reg
415{
416 /* Register address. */
417 int address;
252b5132 418
f36e33da
CZ		 419 /* One bit flags for the opcode. These are primarily used to
420 indicate specific processors and environments support the
421 instructions. */
422 unsigned cpu;
423
8ddf6b2a
CZ		 424 /* AUX register subclass. */
425 insn_subclass_t subclass;
426
427 /* Register name. */
886a2506
NC		 428 const char *name;
429
430 /* Size of the string. */
431 size_t length;
432};
433
434extern const struct arc_aux_reg arc_aux_regs[];
435extern const unsigned arc_num_aux_regs;
436
4670103e
CZ		 437extern const struct arc_opcode arc_relax_opcodes[];
438extern const unsigned arc_num_relax_opcodes;
439
4b0c052e
AB		 440/* Macro used for generating one class of NPS instructions. */
441#define NPS_CMEM_HIGH_VALUE 0x57f0
442
f2dd8838
CZ		 443/* Macros to help generating regular pattern instructions. */
444#define FIELDA(word) (word & 0x3F)
445#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
446#define FIELDC(word) ((word & 0x3F) << 6)
447#define FIELDF (0x01 << 15)
448#define FIELDQ (0x1F)
449
450#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
451#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
452#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
453
454#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
455#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
456#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
457#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
458#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
459#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
460#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
461#define INSN3OP_0LL(MOP,SOP) \
462 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
463#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
464#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
465#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
466#define INSN3OP_0LU(MOP,SOP) \
467 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
468#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
469#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
470#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
471#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
472#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
473#define INSN3OP_C0LL(MOP,SOP) \
474 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
475#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
476#define INSN3OP_C0LU(MOP,SOP) \
477 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
478
479#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
480#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
481#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
482#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
483#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
484#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
485#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
486#define MINSN3OP_0LL (~(FIELDF))
487#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
488#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
489#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
490#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
491#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
492#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
493#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
494#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
495#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
496#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
497#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
498#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
499
500#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
501#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
502#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
503#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
504#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
505#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
506
507#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
508#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
509#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
510#define MINSN2OP_0L (~(FIELDF))
511#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
512#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
513
b99747ae
CZ		 514/* Various constants used when defining an extension instruction. */
515#define ARC_SYNTAX_3OP (1 << 0)
516#define ARC_SYNTAX_2OP (1 << 1)
517#define ARC_OP1_MUST_BE_IMM (1 << 2)
518#define ARC_OP1_IMM_IMPLIED (1 << 3)
519
520#define ARC_SUFFIX_NONE (1 << 0)
521#define ARC_SUFFIX_COND (1 << 1)
522#define ARC_SUFFIX_FLAG (1 << 2)
523
f36e33da
CZ		 524#define ARC_REGISTER_READONLY (1 << 0)
525#define ARC_REGISTER_WRITEONLY (1 << 1)
526#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 527
528/* Constants needed to initialize extension instructions. */
529extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
530extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
531extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
532extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
533
534extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
535extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
536extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
537extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
538extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
539extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
540extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
541extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
542extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
543extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
544extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
545extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
546
547extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
548extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
549extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
550
551extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
552extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
553extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
554
555extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
556extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
557extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
558extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
559extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
560extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
561
562extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
563extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
564extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
565extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
566
886a2506 567#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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