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252b5132 | 1 | /* Opcode table for the ARC. |
8cf3f354 AM |
2 | Copyright 1994, 1995, 1997, 2001, 2002, 2003 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by Doug Evans (dje@cygnus.com). |
5 | ||
0d2bcfaf NC |
6 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
7 | the GNU Binutils. | |
252b5132 | 8 | |
0d2bcfaf NC |
9 | GAS/GDB is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
252b5132 | 13 | |
0d2bcfaf NC |
14 | GAS/GDB is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS or GDB; see the file COPYING. If not, write to | |
e172dbf8 NC |
21 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
22 | MA 02110-1301, USA. */ | |
252b5132 | 23 | |
252b5132 RH |
24 | |
25 | /* List of the various cpu types. | |
26 | The tables currently use bit masks to say whether the instruction or | |
27 | whatever is supported by a particular cpu. This lets us have one entry | |
28 | apply to several cpus. | |
29 | ||
0d2bcfaf NC |
30 | The `base' cpu must be 0. The cpu type is treated independently of |
31 | endianness. The complete `mach' number includes endianness. | |
252b5132 | 32 | These values are internal to opcodes/bfd/binutils/gas. */ |
0d2bcfaf NC |
33 | #define ARC_MACH_5 0 |
34 | #define ARC_MACH_6 1 | |
35 | #define ARC_MACH_7 2 | |
36 | #define ARC_MACH_8 4 | |
37 | ||
252b5132 | 38 | /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ |
0d2bcfaf | 39 | #define ARC_MACH_BIG 16 |
252b5132 RH |
40 | |
41 | /* Mask of number of bits necessary to record cpu type. */ | |
0d2bcfaf NC |
42 | #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) |
43 | ||
252b5132 | 44 | /* Mask of number of bits necessary to record cpu type + endianness. */ |
0d2bcfaf | 45 | #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) |
252b5132 RH |
46 | |
47 | /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ | |
0d2bcfaf | 48 | |
252b5132 RH |
49 | typedef unsigned int arc_insn; |
50 | ||
51 | struct arc_opcode { | |
0d2bcfaf NC |
52 | char *syntax; /* syntax of insn */ |
53 | unsigned long mask, value; /* recognize insn if (op&mask) == value */ | |
54 | int flags; /* various flag bits */ | |
252b5132 RH |
55 | |
56 | /* Values for `flags'. */ | |
57 | ||
58 | /* Return CPU number, given flag bits. */ | |
59 | #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
0d2bcfaf | 60 | |
252b5132 RH |
61 | /* Return MACH number, given flag bits. */ |
62 | #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
0d2bcfaf | 63 | |
252b5132 | 64 | /* First opcode flag bit available after machine mask. */ |
0d2bcfaf NC |
65 | #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) |
66 | ||
252b5132 RH |
67 | /* This insn is a conditional branch. */ |
68 | #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) | |
0d2bcfaf NC |
69 | #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) |
70 | #define SYNTAX_LENGTH (SYNTAX_3OP ) | |
71 | #define SYNTAX_2OP (SYNTAX_3OP << 1) | |
72 | #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) | |
73 | #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) | |
74 | #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) | |
75 | ||
76 | #define I(x) (((x) & 31) << 27) | |
77 | #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) | |
78 | #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) | |
79 | #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) | |
80 | #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ | |
81 | ||
82 | /* These values are used to optimize assembly and disassembly. Each insn | |
83 | is on a list of related insns (same first letter for assembly, same | |
84 | insn code for disassembly). */ | |
85 | ||
86 | struct arc_opcode *next_asm; /* Next instr to try during assembly. */ | |
87 | struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ | |
88 | ||
89 | /* Macros to create the hash values for the lists. */ | |
252b5132 RH |
90 | #define ARC_HASH_OPCODE(string) \ |
91 | ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) | |
92 | #define ARC_HASH_ICODE(insn) \ | |
93 | ((unsigned int) (insn) >> 27) | |
94 | ||
0d2bcfaf NC |
95 | /* Macros to access `next_asm', `next_dis' so users needn't care about the |
96 | underlying mechanism. */ | |
252b5132 RH |
97 | #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) |
98 | #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) | |
99 | }; | |
100 | ||
0d2bcfaf NC |
101 | /* this is an "insert at front" linked list per Metaware spec |
102 | that new definitions override older ones. */ | |
84037f8c | 103 | extern struct arc_opcode *arc_ext_opcodes; |
0d2bcfaf | 104 | |
252b5132 | 105 | struct arc_operand_value { |
0d2bcfaf NC |
106 | char *name; /* eg: "eq" */ |
107 | short value; /* eg: 1 */ | |
108 | unsigned char type; /* index into `arc_operands' */ | |
109 | unsigned char flags; /* various flag bits */ | |
252b5132 RH |
110 | |
111 | /* Values for `flags'. */ | |
112 | ||
113 | /* Return CPU number, given flag bits. */ | |
114 | #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
115 | /* Return MACH number, given flag bits. */ | |
116 | #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) | |
117 | }; | |
118 | ||
0d2bcfaf NC |
119 | struct arc_ext_operand_value { |
120 | struct arc_ext_operand_value *next; | |
121 | struct arc_operand_value operand; | |
84037f8c KD |
122 | }; |
123 | ||
124 | extern struct arc_ext_operand_value *arc_ext_operands; | |
0d2bcfaf | 125 | |
252b5132 | 126 | struct arc_operand { |
0d2bcfaf | 127 | /* One of the insn format chars. */ |
252b5132 RH |
128 | unsigned char fmt; |
129 | ||
0d2bcfaf | 130 | /* The number of bits in the operand (may be unused for a modifier). */ |
252b5132 RH |
131 | unsigned char bits; |
132 | ||
0d2bcfaf NC |
133 | /* How far the operand is left shifted in the instruction, or |
134 | the modifier's flag bit (may be unused for a modifier. */ | |
252b5132 RH |
135 | unsigned char shift; |
136 | ||
0d2bcfaf | 137 | /* Various flag bits. */ |
252b5132 RH |
138 | int flags; |
139 | ||
140 | /* Values for `flags'. */ | |
141 | ||
142 | /* This operand is a suffix to the opcode. */ | |
143 | #define ARC_OPERAND_SUFFIX 1 | |
144 | ||
145 | /* This operand is a relative branch displacement. The disassembler | |
146 | prints these symbolically if possible. */ | |
147 | #define ARC_OPERAND_RELATIVE_BRANCH 2 | |
148 | ||
149 | /* This operand is an absolute branch address. The disassembler | |
150 | prints these symbolically if possible. */ | |
151 | #define ARC_OPERAND_ABSOLUTE_BRANCH 4 | |
152 | ||
153 | /* This operand is an address. The disassembler | |
154 | prints these symbolically if possible. */ | |
155 | #define ARC_OPERAND_ADDRESS 8 | |
156 | ||
157 | /* This operand is a long immediate value. */ | |
158 | #define ARC_OPERAND_LIMM 0x10 | |
159 | ||
160 | /* This operand takes signed values. */ | |
161 | #define ARC_OPERAND_SIGNED 0x20 | |
162 | ||
163 | /* This operand takes signed values, but also accepts a full positive | |
164 | range of values. That is, if bits is 16, it takes any value from | |
165 | -0x8000 to 0xffff. */ | |
166 | #define ARC_OPERAND_SIGNOPT 0x40 | |
167 | ||
168 | /* This operand should be regarded as a negative number for the | |
169 | purposes of overflow checking (i.e., the normal most negative | |
170 | number is disallowed and one more than the normal most positive | |
171 | number is allowed). This flag will only be set for a signed | |
172 | operand. */ | |
173 | #define ARC_OPERAND_NEGATIVE 0x80 | |
174 | ||
175 | /* This operand doesn't really exist. The program uses these operands | |
176 | in special ways. */ | |
177 | #define ARC_OPERAND_FAKE 0x100 | |
178 | ||
0d2bcfaf NC |
179 | /* separate flags operand for j and jl instructions */ |
180 | #define ARC_OPERAND_JUMPFLAGS 0x200 | |
181 | ||
182 | /* allow warnings and errors to be issued after call to insert_xxxxxx */ | |
183 | #define ARC_OPERAND_WARN 0x400 | |
184 | #define ARC_OPERAND_ERROR 0x800 | |
185 | ||
186 | /* this is a load operand */ | |
187 | #define ARC_OPERAND_LOAD 0x8000 | |
188 | ||
189 | /* this is a store operand */ | |
190 | #define ARC_OPERAND_STORE 0x10000 | |
191 | ||
252b5132 RH |
192 | /* Modifier values. */ |
193 | /* A dot is required before a suffix. Eg: .le */ | |
194 | #define ARC_MOD_DOT 0x1000 | |
195 | ||
196 | /* A normal register is allowed (not used, but here for completeness). */ | |
197 | #define ARC_MOD_REG 0x2000 | |
198 | ||
199 | /* An auxiliary register name is expected. */ | |
200 | #define ARC_MOD_AUXREG 0x4000 | |
201 | ||
202 | /* Sum of all ARC_MOD_XXX bits. */ | |
203 | #define ARC_MOD_BITS 0x7000 | |
204 | ||
205 | /* Non-zero if the operand type is really a modifier. */ | |
206 | #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) | |
207 | ||
0d2bcfaf NC |
208 | /* enforce read/write only register restrictions */ |
209 | #define ARC_REGISTER_READONLY 0x01 | |
210 | #define ARC_REGISTER_WRITEONLY 0x02 | |
211 | #define ARC_REGISTER_NOSHORT_CUT 0x04 | |
212 | ||
213 | /* Insertion function. This is used by the assembler. To insert an | |
214 | operand value into an instruction, check this field. | |
215 | ||
216 | If it is NULL, execute | |
217 | i |= (p & ((1 << o->bits) - 1)) << o->shift; | |
218 | (I is the instruction which we are filling in, O is a pointer to | |
219 | this structure, and OP is the opcode value; this assumes twos | |
220 | complement arithmetic). | |
221 | ||
222 | If this field is not NULL, then simply call it with the | |
223 | instruction and the operand value. It will return the new value | |
224 | of the instruction. If the ERRMSG argument is not NULL, then if | |
225 | the operand value is illegal, *ERRMSG will be set to a warning | |
226 | string (the operand will be inserted in any case). If the | |
227 | operand value is legal, *ERRMSG will be unchanged. | |
228 | ||
229 | REG is non-NULL when inserting a register value. */ | |
252b5132 | 230 | |
8cf3f354 AM |
231 | arc_insn (*insert) |
232 | (arc_insn insn, const struct arc_operand *operand, int mods, | |
233 | const struct arc_operand_value *reg, long value, const char **errmsg); | |
252b5132 | 234 | |
0d2bcfaf NC |
235 | /* Extraction function. This is used by the disassembler. To |
236 | extract this operand type from an instruction, check this field. | |
237 | ||
238 | If it is NULL, compute | |
239 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); | |
240 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 | |
241 | && (op & (1 << (o->bits - 1))) != 0) | |
242 | op -= 1 << o->bits; | |
243 | (I is the instruction, O is a pointer to this structure, and OP | |
244 | is the result; this assumes twos complement arithmetic). | |
245 | ||
246 | If this field is not NULL, then simply call it with the | |
247 | instruction value. It will return the value of the operand. If | |
248 | the INVALID argument is not NULL, *INVALID will be set to | |
249 | non-zero if this operand type can not actually be extracted from | |
250 | this operand (i.e., the instruction does not match). If the | |
251 | operand is valid, *INVALID will not be changed. | |
252 | ||
253 | INSN is a pointer to an array of two `arc_insn's. The first element is | |
254 | the insn, the second is the limm if present. | |
255 | ||
256 | Operands that have a printable form like registers and suffixes have | |
257 | their struct arc_operand_value pointer stored in OPVAL. */ | |
252b5132 | 258 | |
8cf3f354 AM |
259 | long (*extract) |
260 | (arc_insn *insn, const struct arc_operand *operand, int mods, | |
261 | const struct arc_operand_value **opval, int *invalid); | |
252b5132 RH |
262 | }; |
263 | ||
0d2bcfaf NC |
264 | /* Bits that say what version of cpu we have. These should be passed to |
265 | arc_init_opcode_tables. At present, all there is is the cpu type. */ | |
252b5132 RH |
266 | |
267 | /* CPU number, given value passed to `arc_init_opcode_tables'. */ | |
268 | #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
269 | /* MACH number, given value passed to `arc_init_opcode_tables'. */ | |
270 | #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
271 | ||
272 | /* Special register values: */ | |
273 | #define ARC_REG_SHIMM_UPDATE 61 | |
274 | #define ARC_REG_SHIMM 63 | |
275 | #define ARC_REG_LIMM 62 | |
276 | ||
277 | /* Non-zero if REG is a constant marker. */ | |
278 | #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) | |
279 | ||
280 | /* Positions and masks of various fields: */ | |
281 | #define ARC_SHIFT_REGA 21 | |
282 | #define ARC_SHIFT_REGB 15 | |
283 | #define ARC_SHIFT_REGC 9 | |
284 | #define ARC_MASK_REG 63 | |
285 | ||
286 | /* Delay slot types. */ | |
0d2bcfaf NC |
287 | #define ARC_DELAY_NONE 0 /* no delay slot */ |
288 | #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ | |
289 | #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ | |
252b5132 RH |
290 | |
291 | /* Non-zero if X will fit in a signed 9 bit field. */ | |
292 | #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) | |
293 | ||
294 | extern const struct arc_operand arc_operands[]; | |
295 | extern const int arc_operand_count; | |
0d2bcfaf | 296 | extern struct arc_opcode arc_opcodes[]; |
252b5132 RH |
297 | extern const int arc_opcodes_count; |
298 | extern const struct arc_operand_value arc_suffixes[]; | |
299 | extern const int arc_suffixes_count; | |
300 | extern const struct arc_operand_value arc_reg_names[]; | |
301 | extern const int arc_reg_names_count; | |
302 | extern unsigned char arc_operand_map[]; | |
303 | ||
304 | /* Utility fns in arc-opc.c. */ | |
8cf3f354 | 305 | int arc_get_opcode_mach (int, int); |
0d2bcfaf | 306 | |
252b5132 | 307 | /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ |
8cf3f354 AM |
308 | void arc_opcode_init_tables (int); |
309 | void arc_opcode_init_insert (void); | |
310 | void arc_opcode_init_extract (void); | |
311 | const struct arc_opcode *arc_opcode_lookup_asm (const char *); | |
312 | const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); | |
313 | int arc_opcode_limm_p (long *); | |
0d2bcfaf | 314 | const struct arc_operand_value *arc_opcode_lookup_suffix |
8cf3f354 AM |
315 | (const struct arc_operand *type, int value); |
316 | int arc_opcode_supported (const struct arc_opcode *); | |
317 | int arc_opval_supported (const struct arc_operand_value *); | |
318 | int arc_limm_fixup_adjust (arc_insn); | |
319 | int arc_insn_is_j (arc_insn); | |
320 | int arc_insn_not_jl (arc_insn); | |
321 | int arc_operand_type (int); | |
322 | struct arc_operand_value *get_ext_suffix (char *); | |
323 | int arc_get_noshortcut_flag (void); |