[deliverable/binutils-gdb.git] / include / opcode / arm.h

/* ARM assembler/disassembler support.
   Copyright 2004 Free Software Foundation, Inc.

   This file is part of GDB and GAS.

   GDB and GAS are free software; you can redistribute it and/or
   modify it under the terms of the GNU General Public License as
   published by the Free Software Foundation; either version 1, or (at
   your option) any later version.

   GDB and GAS are distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GDB or GAS; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

/* The following bitmasks control CPU extensions:  */
#define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
#define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
#define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
#define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
#define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
#define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
#define ARM_EXT_V4T	 0x00000040	/* Thumb.                  */
#define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
#define ARM_EXT_V5T	 0x00000100	/* Improved interworking.  */
#define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
#define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
#define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
#define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
#define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
#define ARM_EXT_V6Z      0x00004000     /* ARM V6Z.                */
#define ARM_EXT_V6T2	 0x00008000	/* Thumb-2.                */

/* Co-processor space extensions.  */
#define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
#define ARM_CEXT_MAVERICK 0x00000002	/* Use Cirrus/DSP coprocessor.  */
#define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */

#define FPU_ENDIAN_PURE	 0x80000000	/* Pure-endian doubles.	      */
#define FPU_ENDIAN_BIG	 0		/* Double words-big-endian.   */
#define FPU_FPA_EXT_V1	 0x40000000	/* Base FPA instruction set.  */
#define FPU_FPA_EXT_V2	 0x20000000	/* LFM/SFM.		      */
#define FPU_MAVERICK	 0x10000000	/* Cirrus Maverick.	      */
#define FPU_VFP_EXT_V1xD 0x08000000	/* Base VFP instruction set.  */
#define FPU_VFP_EXT_V1	 0x04000000	/* Double-precision insns.    */
#define FPU_VFP_EXT_V2	 0x02000000	/* ARM10E VFPr1.	      */

/* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
   defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
   ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
   three more to cover cores prior to ARM6.  Finally, there are cores which
   implement further extensions in the co-processor space.  */
#define ARM_AEXT_V1			  ARM_EXT_V1
#define ARM_AEXT_V2	(ARM_AEXT_V1	| ARM_EXT_V2)
#define ARM_AEXT_V2S	(ARM_AEXT_V2	| ARM_EXT_V2S)
#define ARM_AEXT_V3	(ARM_AEXT_V2S	| ARM_EXT_V3)
#define ARM_AEXT_V3M	(ARM_AEXT_V3	| ARM_EXT_V3M)
#define ARM_AEXT_V4xM	(ARM_AEXT_V3	| ARM_EXT_V4)
#define ARM_AEXT_V4	(ARM_AEXT_V3M	| ARM_EXT_V4)
#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T)
#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T)
#define ARM_AEXT_V5xM	(ARM_AEXT_V4xM	| ARM_EXT_V5)
#define ARM_AEXT_V5	(ARM_AEXT_V4	| ARM_EXT_V5)
#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5TExP	(ARM_AEXT_V5T	| ARM_EXT_V5ExP)
#define ARM_AEXT_V5TE	(ARM_AEXT_V5TExP | ARM_EXT_V5E)
#define ARM_AEXT_V5TEJ	(ARM_AEXT_V5TE	| ARM_EXT_V5J)
#define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
#define ARM_AEXT_V6Z    (ARM_AEXT_V6    | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZK   (ARM_AEXT_V6    | ARM_EXT_V6K | ARM_EXT_V6Z)
#define ARM_AEXT_V6T2   (ARM_AEXT_V6    | ARM_EXT_V6T2)
#define ARM_AEXT_V6KT2  (ARM_AEXT_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2  (ARM_AEXT_V6    | ARM_EXT_V6T2 | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)

/* Processors with specific extensions in the co-processor space.  */
#define ARM_ARCH_XSCALE	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_IWMMXT	\
 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)

#define FPU_VFP_V1xD	(FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1	(FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2	(FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_HARD	(FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2)
#define FPU_FPA		(FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)

/* Deprecated */
#define FPU_ARCH_VFP	ARM_FEATURE (0, FPU_ENDIAN_PURE)

#define FPU_ARCH_FPE	ARM_FEATURE (0, FPU_FPA_EXT_V1)
#define FPU_ARCH_FPA	ARM_FEATURE (0, FPU_FPA)

#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1	  ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2	  ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)

#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)

#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)

#define ARM_ARCH_V1	ARM_FEATURE (ARM_AEXT_V1, 0)
#define ARM_ARCH_V2	ARM_FEATURE (ARM_AEXT_V2, 0)
#define ARM_ARCH_V2S	ARM_FEATURE (ARM_AEXT_V2S, 0)
#define ARM_ARCH_V3	ARM_FEATURE (ARM_AEXT_V3, 0)
#define ARM_ARCH_V3M	ARM_FEATURE (ARM_AEXT_V3M, 0)
#define ARM_ARCH_V4xM	ARM_FEATURE (ARM_AEXT_V4xM, 0)
#define ARM_ARCH_V4	ARM_FEATURE (ARM_AEXT_V4, 0)
#define ARM_ARCH_V4TxM	ARM_FEATURE (ARM_AEXT_V4TxM, 0)
#define ARM_ARCH_V4T	ARM_FEATURE (ARM_AEXT_V4T, 0)
#define ARM_ARCH_V5xM	ARM_FEATURE (ARM_AEXT_V5xM, 0)
#define ARM_ARCH_V5	ARM_FEATURE (ARM_AEXT_V5, 0)
#define ARM_ARCH_V5TxM	ARM_FEATURE (ARM_AEXT_V5TxM, 0)
#define ARM_ARCH_V5T	ARM_FEATURE (ARM_AEXT_V5T, 0)
#define ARM_ARCH_V5TExP	ARM_FEATURE (ARM_AEXT_V5TExP, 0)
#define ARM_ARCH_V5TE	ARM_FEATURE (ARM_AEXT_V5TE, 0)
#define ARM_ARCH_V5TEJ	ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
#define ARM_ARCH_V6	ARM_FEATURE (ARM_AEXT_V6, 0)
#define ARM_ARCH_V6K	ARM_FEATURE (ARM_AEXT_V6K, 0)
#define ARM_ARCH_V6Z	ARM_FEATURE (ARM_AEXT_V6Z, 0)
#define ARM_ARCH_V6ZK	ARM_FEATURE (ARM_AEXT_V6ZK, 0)
#define ARM_ARCH_V6T2	ARM_FEATURE (ARM_AEXT_V6T2, 0)
#define ARM_ARCH_V6KT2	ARM_FEATURE (ARM_AEXT_V6KT2, 0)
#define ARM_ARCH_V6ZT2	ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
#define ARM_ARCH_V6ZKT2	ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)

/* Some useful combinations:  */
#define ARM_ARCH_NONE	ARM_FEATURE (0, 0)
#define FPU_NONE	ARM_FEATURE (0, 0)
#define ARM_ANY		ARM_FEATURE (-1, 0)	/* Any basic core.  */
#define FPU_ANY_HARD	ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2, 0)

/* There are too many feature bits to fit in a single word, so use a
   structure.  For simplicity we put all core features in one word and
   everything else in the other.  */
typedef struct
{
  unsigned long core;
  unsigned long coproc;
} arm_feature_set;

#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
  (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)

#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)	\
  do {						\
    (TARG).core = (F1).core | (F2).core;	\
    (TARG).coproc = (F1).coproc | (F2).coproc;	\
  } while (0)

#define ARM_CLEAR_FEATURE(TARG,F1,F2)		\
  do {						\
    (TARG).core = (F1).core &~ (F2).core;	\
    (TARG).coproc = (F1).coproc &~ (F2).coproc;	\
  } while (0)

#define ARM_FEATURE(core, coproc) {(core), (coproc)}
Commit	Line	Data
b781e558 RE	1	/* ARM assembler/disassembler support.
	2	Copyright 2004 Free Software Foundation, Inc.
	3
	4	This file is part of GDB and GAS.
	5
	6	GDB and GAS are free software; you can redistribute it and/or
	7	modify it under the terms of the GNU General Public License as
	8	published by the Free Software Foundation; either version 1, or (at
	9	your option) any later version.
	10
	11	GDB and GAS are distributed in the hope that it will be useful, but
	12	WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GDB or GAS; see the file COPYING. If not, write to the
e172dbf8 NC	18	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
e172dbf8 NC	19	02110-1301, USA. */
b781e558 RE	20
	21	/* The following bitmasks control CPU extensions: */
	22	#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
	23	#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
	24	#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
	25	#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
	26	#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
	27	#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
0a003adc	28	#define ARM_EXT_V4T 0x00000040 /* Thumb. */
b781e558	29	#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
0a003adc	30	#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
b781e558 RE	31	#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
	32	#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
	33	#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
	34	#define ARM_EXT_V6 0x00001000 /* ARM V6. */
0dd132b6 NC	35	#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
0dd132b6 NC	36	#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
0a003adc	37	#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
b781e558 RE	38
b781e558 RE	39	/* Co-processor space extensions. */
e74cfd16 PB	40	#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
	41	#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
	42	#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
	43
	44	#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
	45	#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
	46	#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
	47	#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
	48	#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
	49	#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
	50	#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
	51	#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
b781e558 RE	52
	53	/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
	54	defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
	55	ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
	56	three more to cover cores prior to ARM6. Finally, there are cores which
	57	implement further extensions in the co-processor space. */
e74cfd16 PB	58	#define ARM_AEXT_V1 ARM_EXT_V1
	59	#define ARM_AEXT_V2 (ARM_AEXT_V1 \| ARM_EXT_V2)
	60	#define ARM_AEXT_V2S (ARM_AEXT_V2 \| ARM_EXT_V2S)
	61	#define ARM_AEXT_V3 (ARM_AEXT_V2S \| ARM_EXT_V3)
	62	#define ARM_AEXT_V3M (ARM_AEXT_V3 \| ARM_EXT_V3M)
	63	#define ARM_AEXT_V4xM (ARM_AEXT_V3 \| ARM_EXT_V4)
	64	#define ARM_AEXT_V4 (ARM_AEXT_V3M \| ARM_EXT_V4)
	65	#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM \| ARM_EXT_V4T)
	66	#define ARM_AEXT_V4T (ARM_AEXT_V4 \| ARM_EXT_V4T)
	67	#define ARM_AEXT_V5xM (ARM_AEXT_V4xM \| ARM_EXT_V5)
	68	#define ARM_AEXT_V5 (ARM_AEXT_V4 \| ARM_EXT_V5)
	69	#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM \| ARM_EXT_V4T \| ARM_EXT_V5T)
	70	#define ARM_AEXT_V5T (ARM_AEXT_V5 \| ARM_EXT_V4T \| ARM_EXT_V5T)
	71	#define ARM_AEXT_V5TExP (ARM_AEXT_V5T \| ARM_EXT_V5ExP)
	72	#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP \| ARM_EXT_V5E)
	73	#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE \| ARM_EXT_V5J)
	74	#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ \| ARM_EXT_V6)
	75	#define ARM_AEXT_V6K (ARM_AEXT_V6 \| ARM_EXT_V6K)
	76	#define ARM_AEXT_V6Z (ARM_AEXT_V6 \| ARM_EXT_V6Z)
	77	#define ARM_AEXT_V6ZK (ARM_AEXT_V6 \| ARM_EXT_V6K \| ARM_EXT_V6Z)
	78	#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \| ARM_EXT_V6T2)
	79	#define ARM_AEXT_V6KT2 (ARM_AEXT_V6 \| ARM_EXT_V6T2 \| ARM_EXT_V6K)
	80	#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6 \| ARM_EXT_V6T2 \| ARM_EXT_V6Z)
	81	#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6 \| ARM_EXT_V6T2 \| ARM_EXT_V6K \| ARM_EXT_V6Z)
b781e558 RE	82
b781e558 RE	83	/* Processors with specific extensions in the co-processor space. */
e74cfd16 PB	84	#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
	85	#define ARM_ARCH_IWMMXT \
	86	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT)
	87
	88	#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD \| FPU_ENDIAN_PURE)
	89	#define FPU_VFP_V1 (FPU_VFP_V1xD \| FPU_VFP_EXT_V1)
	90	#define FPU_VFP_V2 (FPU_VFP_V1 \| FPU_VFP_EXT_V2)
	91	#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD \| FPU_VFP_EXT_V1 \| FPU_VFP_EXT_V2)
	92	#define FPU_FPA (FPU_FPA_EXT_V1 \| FPU_FPA_EXT_V2)
	93
	94	/* Deprecated */
	95	#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
b781e558	96
e74cfd16 PB	97	#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
e74cfd16 PB	98	#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
b781e558	99
e74cfd16 PB	100	#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
	101	#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
	102	#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
	103	#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
b781e558	104
e74cfd16	105	#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
b781e558	106
e74cfd16 PB	107	#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
	108
	109	#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
	110	#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
	111	#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
	112	#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
	113	#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
	114	#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
	115	#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
	116	#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
	117	#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
	118	#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
	119	#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
	120	#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
	121	#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
	122	#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
	123	#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
	124	#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
	125	#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
	126	#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
	127	#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
	128	#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
	129	#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
	130	#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
	131	#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
	132	#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
b781e558 RE	133
b781e558 RE	134	/* Some useful combinations: */
e74cfd16 PB	135	#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
	136	#define FPU_NONE ARM_FEATURE (0, 0)
	137	#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
	138	#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA \| FPU_VFP_HARD \| FPU_MAVERICK)
	139	#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2, 0)
	140
	141	/* There are too many feature bits to fit in a single word, so use a
	142	structure. For simplicity we put all core features in one word and
	143	everything else in the other. */
	144	typedef struct
	145	{
	146	unsigned long core;
	147	unsigned long coproc;
	148	} arm_feature_set;
	149
	150	#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
	151	(((CPU).core & (FEAT).core) != 0 \|\| ((CPU).coproc & (FEAT).coproc) != 0)
	152
	153	#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
	154	do { \
	155	(TARG).core = (F1).core \| (F2).core; \
	156	(TARG).coproc = (F1).coproc \| (F2).coproc; \
	157	} while (0)
	158
	159	#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
	160	do { \
	161	(TARG).core = (F1).core &~ (F2).core; \
	162	(TARG).coproc = (F1).coproc &~ (F2).coproc; \
	163	} while (0)
	164
	165	#define ARM_FEATURE(core, coproc) {(core), (coproc)}