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b781e558 | 1 | /* ARM assembler/disassembler support. |
219d1afa | 2 | Copyright (C) 2004-2018 Free Software Foundation, Inc. |
b781e558 RE |
3 | |
4 | This file is part of GDB and GAS. | |
5 | ||
6 | GDB and GAS are free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU General Public License as | |
e4e42b45 | 8 | published by the Free Software Foundation; either version 3, or (at |
b781e558 RE |
9 | your option) any later version. |
10 | ||
11 | GDB and GAS are distributed in the hope that it will be useful, but | |
12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
e4e42b45 NC |
17 | along with GDB or GAS; see the file COPYING3. If not, write to the |
18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
19 | MA 02110-1301, USA. */ | |
b781e558 RE |
20 | |
21 | /* The following bitmasks control CPU extensions: */ | |
22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ | |
23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ | |
24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ | |
25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ | |
26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ | |
27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ | |
0a003adc | 28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ |
b781e558 | 29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ |
0a003adc | 30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ |
b781e558 RE |
31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ |
32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ | |
33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ | |
34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ | |
0dd132b6 | 35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ |
4ed7ed8d | 36 | #define ARM_EXT_V8 0x00004000 /* ARMv8 w/o atomics. */ |
0a003adc | 37 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ |
62b3e311 PB |
38 | #define ARM_EXT_DIV 0x00010000 /* Integer division. */ |
39 | /* The 'M' in Arm V7M stands for Microcontroller. | |
40 | On earlier architecture variants it stands for Multiply. */ | |
41 | #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ | |
42 | #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ | |
43 | #define ARM_EXT_V7 0x00080000 /* Arm V7. */ | |
44 | #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ | |
45 | #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ | |
46 | #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ | |
7e806470 PB |
47 | #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ |
48 | #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ | |
49 | #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ | |
9e3c6df6 PB |
50 | #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), |
51 | not in v7-M. */ | |
60e5ef9f | 52 | #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ |
f4c65163 | 53 | #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ |
b2a5fbdc | 54 | #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ |
b8ec4e87 | 55 | #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM |
eea54501 | 56 | state. */ |
90ec0d68 | 57 | #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ |
b781e558 | 58 | |
ddfded2f | 59 | #define ARM_EXT2_PAN 0x00000001 /* PAN extension. */ |
56a1b672 | 60 | #define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */ |
4ed7ed8d TP |
61 | #define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */ |
62 | #define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */ | |
4d1464f2 | 63 | #define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */ |
b8ec4e87 | 64 | #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */ |
4d1464f2 MW |
65 | #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */ |
66 | #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */ | |
a12fd8e1 | 67 | #define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */ |
ced40572 | 68 | #define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */ |
dec41383 | 69 | #define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */ |
01f48020 | 70 | #define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */ |
23f233a5 | 71 | #define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */ |
7fadb25d | 72 | #define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */ |
dad0c3bf | 73 | #define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */ |
ddfded2f | 74 | |
b781e558 | 75 | /* Co-processor space extensions. */ |
e74cfd16 PB |
76 | #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
77 | #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ | |
0198d5e6 TC |
78 | #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ |
79 | #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ | |
e74cfd16 PB |
80 | |
81 | #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ | |
82 | #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ | |
83 | #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ | |
84 | #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ | |
85 | #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ | |
86 | #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ | |
87 | #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ | |
88 | #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ | |
62f3b8c8 PB |
89 | #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ |
90 | #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ | |
91 | #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ | |
92 | #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ | |
93 | #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ | |
94 | #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ | |
95 | #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ | |
a715796b | 96 | #define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ |
bca38921 MGD |
97 | #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ |
98 | #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ | |
dd5181d5 | 99 | #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ |
a715796b | 100 | #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ |
c604a79a JW |
101 | #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ |
102 | #define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */ | |
b781e558 RE |
103 | |
104 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) | |
105 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, | |
106 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add | |
107 | three more to cover cores prior to ARM6. Finally, there are cores which | |
108 | implement further extensions in the co-processor space. */ | |
e74cfd16 PB |
109 | #define ARM_AEXT_V1 ARM_EXT_V1 |
110 | #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) | |
111 | #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) | |
112 | #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) | |
113 | #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) | |
114 | #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) | |
115 | #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) | |
173205ca TP |
116 | #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T | ARM_EXT_OS) |
117 | #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T | ARM_EXT_OS) | |
e74cfd16 PB |
118 | #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) |
119 | #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) | |
173205ca TP |
120 | #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T \ |
121 | | ARM_EXT_OS) | |
122 | #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T \ | |
123 | | ARM_EXT_OS) | |
e74cfd16 PB |
124 | #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) |
125 | #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) | |
126 | #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) | |
127 | #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) | |
128 | #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) | |
f4c65163 | 129 | #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) |
f33026a9 | 130 | #define ARM_AEXT_V6KZ (ARM_AEXT_V6K | ARM_EXT_SEC) |
7e806470 | 131 | #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ |
9e3c6df6 PB |
132 | | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ |
133 | | ARM_EXT_V6_DSP ) | |
62b3e311 | 134 | #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) |
f4c65163 | 135 | #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) |
f33026a9 | 136 | #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) |
ac7f631b | 137 | #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) |
62b3e311 | 138 | #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) |
c9fb6e58 YZ |
139 | #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ |
140 | | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP) | |
62b3e311 PB |
141 | #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) |
142 | #define ARM_AEXT_NOTM \ | |
9e3c6df6 PB |
143 | (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ |
144 | | ARM_EXT_V6_DSP ) | |
251665fc MGD |
145 | #define ARM_AEXT_V6M_ONLY \ |
146 | ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) | |
7e806470 | 147 | #define ARM_AEXT_V6M \ |
173205ca | 148 | ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM | ARM_EXT_OS)) |
b2a5fbdc | 149 | #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) |
62b3e311 | 150 | #define ARM_AEXT_V7M \ |
7e806470 PB |
151 | ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ |
152 | & ~(ARM_AEXT_NOTM)) | |
62b3e311 | 153 | #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) |
9e3c6df6 PB |
154 | #define ARM_AEXT_V7EM \ |
155 | (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) | |
bca38921 MGD |
156 | #define ARM_AEXT_V8A \ |
157 | (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ | |
158 | | ARM_EXT_VIRT | ARM_EXT_V8) | |
ced40572 TP |
159 | #define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) |
160 | #define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A) | |
ff8646ee | 161 | #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) |
4d1464f2 | 162 | #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS) |
a12fd8e1 | 163 | #define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A) |
01f48020 | 164 | #define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_FP16_FML | ARM_EXT2_V8_4A) |
0632eeea SD |
165 | #define ARM_AEXT2_V8_5A (ARM_AEXT2_V8_4A | ARM_EXT2_V8_5A | ARM_EXT2_SB \ |
166 | | ARM_EXT2_PREDRES) | |
ff8646ee | 167 | #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) |
4ed7ed8d | 168 | #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M |
b19ea8d2 | 169 | #define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM |
ff8646ee | 170 | #define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) |
16a1fa25 | 171 | #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN) |
b19ea8d2 | 172 | #define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN |
ced40572 TP |
173 | #define ARM_AEXT_V8R ARM_AEXT_V8A |
174 | #define ARM_AEXT2_V8R ARM_AEXT2_V8AR | |
b781e558 RE |
175 | |
176 | /* Processors with specific extensions in the co-processor space. */ | |
823d2571 | 177 | #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
e74cfd16 | 178 | #define ARM_ARCH_IWMMXT \ |
823d2571 | 179 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
2d447fca | 180 | #define ARM_ARCH_IWMMXT2 \ |
823d2571 TG |
181 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ |
182 | | ARM_CEXT_IWMMXT2) | |
e74cfd16 PB |
183 | |
184 | #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) | |
185 | #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) | |
186 | #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) | |
62f3b8c8 | 187 | #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) |
b1cc4aeb | 188 | #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) |
62f3b8c8 PB |
189 | #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) |
190 | #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) | |
191 | #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) | |
ada65aa3 | 192 | #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
a715796b TG |
193 | #define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8) |
194 | #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) | |
195 | #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD) | |
bca38921 MGD |
196 | #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) |
197 | #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) | |
9e498214 | 198 | #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ |
62f3b8c8 | 199 | | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ |
b1cc4aeb | 200 | | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) |
e74cfd16 PB |
201 | #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) |
202 | ||
84701018 | 203 | /* Deprecated. */ |
823d2571 | 204 | #define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
b781e558 | 205 | |
823d2571 TG |
206 | #define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) |
207 | #define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) | |
b781e558 | 208 | |
823d2571 TG |
209 | #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) |
210 | #define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) | |
211 | #define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) | |
212 | #define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) | |
62f3b8c8 | 213 | #define FPU_ARCH_VFP_V3D16_FP16 \ |
823d2571 TG |
214 | ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) |
215 | #define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) | |
216 | #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16) | |
217 | #define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) | |
218 | #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ | |
219 | | FPU_VFP_EXT_FP16) | |
220 | #define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) | |
9e498214 | 221 | #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ |
823d2571 | 222 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1) |
8e79c3df | 223 | #define FPU_ARCH_NEON_FP16 \ |
823d2571 TG |
224 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
225 | #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) | |
226 | #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) | |
227 | #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) | |
228 | #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) | |
229 | #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) | |
230 | #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) | |
62f3b8c8 | 231 | #define FPU_ARCH_NEON_VFP_V4 \ |
823d2571 TG |
232 | ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) |
233 | #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) | |
234 | #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ | |
235 | | FPU_VFP_ARMV8) | |
bca38921 | 236 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ |
823d2571 | 237 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
0198d5e6 | 238 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \ |
dec41383 JW |
239 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ |
240 | | FPU_NEON_EXT_DOTPROD) | |
823d2571 | 241 | #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) |
d6b4b13e MW |
242 | #define FPU_ARCH_NEON_VFP_ARMV8_1 \ |
243 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ | |
244 | | FPU_VFP_ARMV8 \ | |
245 | | FPU_NEON_EXT_RDMA) | |
a5932920 MW |
246 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ |
247 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ | |
248 | | FPU_NEON_EXT_RDMA) | |
c604a79a JW |
249 | #define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \ |
250 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) | |
d6b4b13e | 251 | |
b781e558 | 252 | |
823d2571 | 253 | #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
b781e558 | 254 | |
823d2571 | 255 | #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) |
e74cfd16 | 256 | |
823d2571 TG |
257 | #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) |
258 | #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) | |
259 | #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) | |
260 | #define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) | |
261 | #define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) | |
262 | #define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) | |
263 | #define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) | |
264 | #define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) | |
265 | #define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) | |
266 | #define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) | |
267 | #define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) | |
268 | #define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) | |
269 | #define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) | |
270 | #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) | |
271 | #define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) | |
272 | #define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) | |
273 | #define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) | |
274 | #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) | |
275 | #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) | |
f33026a9 | 276 | #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) |
ff8646ee TP |
277 | #define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M) |
278 | #define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M) | |
279 | #define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M) | |
280 | #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M) | |
823d2571 TG |
281 | #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) |
282 | #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) | |
ff8646ee TP |
283 | #define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M) |
284 | #define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M) | |
285 | #define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M) | |
286 | #define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M) | |
287 | #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) | |
288 | #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) | |
289 | #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) | |
27e5a270 RE |
290 | #define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \ |
291 | CRC_EXT_ARMV8) | |
4ed7ed8d | 292 | #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ |
643afb90 | 293 | CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) |
4ed7ed8d | 294 | #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \ |
534dbe46 | 295 | CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) |
a12fd8e1 SN |
296 | #define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \ |
297 | CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) | |
dec41383 JW |
298 | #define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \ |
299 | CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ | |
300 | | FPU_NEON_EXT_DOTPROD) | |
0632eeea | 301 | #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_5A, \ |
23f233a5 SD |
302 | CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ |
303 | | FPU_NEON_EXT_DOTPROD) | |
ff8646ee | 304 | #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) |
16a1fa25 TP |
305 | #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ |
306 | ARM_AEXT2_V8M_MAIN) | |
b19ea8d2 TP |
307 | #define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ |
308 | ARM_AEXT2_V8M_MAIN_DSP) | |
ced40572 | 309 | #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) |
b781e558 RE |
310 | |
311 | /* Some useful combinations: */ | |
823d2571 TG |
312 | #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) |
313 | #define FPU_NONE ARM_FEATURE_LOW (0, 0) | |
314 | #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ | |
2c6b98ea | 315 | #define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */ |
1af1dd51 | 316 | #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ |
823d2571 | 317 | #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
fc289b0a TP |
318 | /* Extensions containing some Thumb-2 instructions. If any is present, Thumb |
319 | ISA is Thumb-2. */ | |
ff8646ee TP |
320 | #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ |
321 | | ARM_EXT_DIV | ARM_EXT_V8, \ | |
322 | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) | |
f4c65163 | 323 | /* v7-a+sec. */ |
ff8646ee TP |
324 | #define ARM_ARCH_V7A_SEC \ |
325 | ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) | |
f4c65163 MGD |
326 | /* v7-a+mp+sec. */ |
327 | #define ARM_ARCH_V7A_MP_SEC \ | |
ff8646ee | 328 | ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) |
3b2f0793 | 329 | /* v7-r+idiv. */ |
ff8646ee TP |
330 | #define ARM_ARCH_V7R_IDIV \ |
331 | ARM_FEATURE_CORE (ARM_AEXT_V7R | ARM_EXT_ADIV, ARM_EXT2_V6T2_V8M) | |
251665fc | 332 | /* Features that are present in v6M and v6S-M but not other v6 cores. */ |
823d2571 | 333 | #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) |
bca38921 | 334 | /* v8-a+fp. */ |
4ed7ed8d | 335 | #define ARM_ARCH_V8A_FP \ |
ff8646ee | 336 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_VFP_ARMV8) |
bca38921 | 337 | /* v8-a+simd (implies fp). */ |
4ed7ed8d | 338 | #define ARM_ARCH_V8A_SIMD \ |
ff8646ee | 339 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_NEON_VFP_ARMV8) |
bca38921 | 340 | /* v8-a+crypto (implies simd+fp). */ |
4ed7ed8d | 341 | #define ARM_ARCH_V8A_CRYPTOV1 \ |
ff8646ee | 342 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) |
e74cfd16 | 343 | |
a5932920 | 344 | /* v8.1-a+fp. */ |
4ed7ed8d TP |
345 | #define ARM_ARCH_V8_1A_FP \ |
346 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_VFP_ARMV8) | |
a5932920 | 347 | /* v8.1-a+simd (implies fp). */ |
4ed7ed8d TP |
348 | #define ARM_ARCH_V8_1A_SIMD \ |
349 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_NEON_VFP_ARMV8_1) | |
a5932920 | 350 | /* v8.1-a+crypto (implies simd+fp). */ |
4ed7ed8d TP |
351 | #define ARM_ARCH_V8_1A_CRYPTOV1 \ |
352 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1) | |
a5932920 MW |
353 | |
354 | ||
e74cfd16 | 355 | /* There are too many feature bits to fit in a single word, so use a |
823d2571 TG |
356 | structure. For simplicity we put all core features in array CORE |
357 | and everything else in the other. All the bits in element core[0] | |
358 | have been occupied, so new feature should use bit in element core[1] | |
359 | and use macro ARM_FEATURE to initialize the feature set variable. */ | |
e74cfd16 PB |
360 | typedef struct |
361 | { | |
823d2571 | 362 | unsigned long core[2]; |
e74cfd16 PB |
363 | unsigned long coproc; |
364 | } arm_feature_set; | |
365 | ||
643afb90 | 366 | /* Test whether CPU and FEAT have any features in common. */ |
e74cfd16 | 367 | #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ |
823d2571 TG |
368 | (((CPU).core[0] & (FEAT).core[0]) != 0 \ |
369 | || ((CPU).core[1] & (FEAT).core[1]) != 0 \ | |
370 | || ((CPU).coproc & (FEAT).coproc) != 0) | |
e74cfd16 | 371 | |
d942732e TP |
372 | /* Tests whether the features of A are a subset of B. */ |
373 | #define ARM_FSET_CPU_SUBSET(A,B) \ | |
374 | (((A).core[0] & (B).core[0]) == (A).core[0] \ | |
375 | && ((A).core[1] & (B).core[1]) == (A).core[1] \ | |
376 | && ((A).coproc & (B).coproc) == (A).coproc) | |
377 | ||
59d09be6 | 378 | #define ARM_CPU_IS_ANY(CPU) \ |
823d2571 TG |
379 | ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ |
380 | && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) | |
59d09be6 | 381 | |
0198d5e6 TC |
382 | #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
383 | do \ | |
384 | { \ | |
385 | (TARG).core[0] = (F1).core[0] | (F2).core[0]; \ | |
386 | (TARG).core[1] = (F1).core[1] | (F2).core[1]; \ | |
387 | (TARG).coproc = (F1).coproc | (F2).coproc; \ | |
388 | } \ | |
389 | while (0) | |
390 | ||
391 | #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ | |
392 | do \ | |
393 | { \ | |
394 | (TARG).core[0] = (F1).core[0] &~ (F2).core[0]; \ | |
395 | (TARG).core[1] = (F1).core[1] &~ (F2).core[1]; \ | |
396 | (TARG).coproc = (F1).coproc &~ (F2).coproc; \ | |
397 | } \ | |
398 | while (0) | |
e74cfd16 | 399 | |
823d2571 | 400 | #define ARM_FEATURE_EQUAL(T1,T2) \ |
0198d5e6 | 401 | ( (T1).core[0] == (T2).core[0] \ |
823d2571 | 402 | && (T1).core[1] == (T2).core[1] \ |
0198d5e6 | 403 | && (T1).coproc == (T2).coproc) |
823d2571 TG |
404 | |
405 | #define ARM_FEATURE_ZERO(T) \ | |
406 | ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) | |
407 | ||
408 | #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ | |
409 | ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) | |
410 | ||
411 | #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} | |
a5932920 | 412 | #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} |
823d2571 | 413 | #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} |
ddfded2f | 414 | #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} |
823d2571 TG |
415 | #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} |
416 | #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} |