projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b781e558 RE |
1 | /* ARM assembler/disassembler support. |
| 2 | Copyright 2004 Free Software Foundation, Inc. | |
| 3 | ||
| 4 | This file is part of GDB and GAS. | |
| 5 | ||
| 6 | GDB and GAS are free software; you can redistribute it and/or | |
| 7 | modify it under the terms of the GNU General Public License as | |
| 8 | published by the Free Software Foundation; either version 1, or (at | |
| 9 | your option) any later version. | |
| 10 | ||
| 11 | GDB and GAS are distributed in the hope that it will be useful, but | |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | General Public License for more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License | |
| 17 | along with GDB or GAS; see the file COPYING. If not, write to the | |
| e172dbf8 NC |
18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ | |
| b781e558 RE |
20 | |
| 21 | /* The following bitmasks control CPU extensions: */ | |
| 22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ | |
| 23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ | |
| 24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ | |
| 25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ | |
| 26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ | |
| 27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ | |
| 0a003adc | 28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ |
| b781e558 | 29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ |
| 0a003adc | 30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ |
| b781e558 RE |
31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ |
| 32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ | |
| 33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ | |
| 34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ | |
| 0dd132b6 NC |
35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ |
| 36 | #define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ | |
| 0a003adc | 37 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ |
| b781e558 RE |
38 | |
| 39 | /* Co-processor space extensions. */ | |
| 40 | #define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */ | |
| 41 | #define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */ | |
| 42 | #define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */ | |
| 43 | ||
| 44 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) | |
| 45 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, | |
| 46 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add | |
| 47 | three more to cover cores prior to ARM6. Finally, there are cores which | |
| 48 | implement further extensions in the co-processor space. */ | |
| 49 | #define ARM_ARCH_V1 ARM_EXT_V1 | |
| 50 | #define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2) | |
| 51 | #define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S) | |
| 52 | #define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3) | |
| 53 | #define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M) | |
| 54 | #define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4) | |
| 55 | #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4) | |
| 56 | #define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T) | |
| 57 | #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T) | |
| 58 | #define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5) | |
| 59 | #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) | |
| 60 | #define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) | |
| 61 | #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T) | |
| 62 | #define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP) | |
| 63 | #define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E) | |
| 64 | #define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J) | |
| 65 | #define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6) | |
| 0dd132b6 NC |
66 | #define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K) |
| 67 | #define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z) | |
| 68 | #define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) | |
| 0a003adc ZW |
69 | #define ARM_ARCH_V6T2 (ARM_ARCH_V6 | ARM_EXT_V6T2) |
| 70 | #define ARM_ARCH_V6KT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K) | |
| 71 | #define ARM_ARCH_V6ZT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6Z) | |
| 72 | #define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) | |
| b781e558 RE |
73 | |
| 74 | /* Processors with specific extensions in the co-processor space. */ | |
| 75 | #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE) | |
| 76 | #define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT) | |
| 77 | ||
| 78 | #define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */ | |
| 79 | #define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */ | |
| 80 | #define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */ | |
| 81 | #define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */ | |
| 82 | #define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */ | |
| 83 | #define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */ | |
| 84 | #define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */ | |
| 85 | #define FPU_NONE 0 | |
| 86 | ||
| 87 | #define FPU_ARCH_FPE FPU_FPA_EXT_V1 | |
| 88 | #define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2) | |
| 89 | ||
| 90 | #define FPU_ARCH_VFP FPU_VFP_EXT_NONE | |
| 91 | #define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE) | |
| 92 | #define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1) | |
| 93 | #define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2) | |
| 94 | ||
| 95 | #define FPU_ARCH_MAVERICK FPU_MAVERICK | |
| 96 | ||
| 97 | /* Some useful combinations: */ | |
| 98 | #define ARM_ANY 0x0000ffff /* Any basic core. */ | |
| 99 | #define ARM_ALL 0x00ffffff /* Any core + co-processor */ | |
| 100 | #define CPROC_ANY 0x00ff0000 /* Any co-processor */ | |
| 101 | #define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */ |