projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b781e558 RE |
1 | /* ARM assembler/disassembler support. |
| 2 | Copyright 2004 Free Software Foundation, Inc. | |
| 3 | ||
| 4 | This file is part of GDB and GAS. | |
| 5 | ||
| 6 | GDB and GAS are free software; you can redistribute it and/or | |
| 7 | modify it under the terms of the GNU General Public License as | |
| 8 | published by the Free Software Foundation; either version 1, or (at | |
| 9 | your option) any later version. | |
| 10 | ||
| 11 | GDB and GAS are distributed in the hope that it will be useful, but | |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | General Public License for more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License | |
| 17 | along with GDB or GAS; see the file COPYING. If not, write to the | |
| e172dbf8 NC |
18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ | |
| b781e558 RE |
20 | |
| 21 | /* The following bitmasks control CPU extensions: */ | |
| 22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ | |
| 23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ | |
| 24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ | |
| 25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ | |
| 26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ | |
| 27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ | |
| 0a003adc | 28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ |
| b781e558 | 29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ |
| 0a003adc | 30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ |
| b781e558 RE |
31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ |
| 32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ | |
| 33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ | |
| 34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ | |
| 0dd132b6 NC |
35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ |
| 36 | #define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ | |
| 0a003adc | 37 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ |
| 62b3e311 PB |
38 | #define ARM_EXT_DIV 0x00010000 /* Integer division. */ |
| 39 | /* The 'M' in Arm V7M stands for Microcontroller. | |
| 40 | On earlier architecture variants it stands for Multiply. */ | |
| 41 | #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ | |
| 42 | #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ | |
| 43 | #define ARM_EXT_V7 0x00080000 /* Arm V7. */ | |
| 44 | #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ | |
| 45 | #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ | |
| 46 | #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ | |
| 7e806470 PB |
47 | #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ |
| 48 | #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ | |
| 49 | #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ | |
| 9e3c6df6 PB |
50 | #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), |
| 51 | not in v7-M. */ | |
| b781e558 RE |
52 | |
| 53 | /* Co-processor space extensions. */ | |
| e74cfd16 PB |
54 | #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
| 55 | #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ | |
| 56 | #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ | |
| 2d447fca | 57 | #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ |
| e74cfd16 PB |
58 | |
| 59 | #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ | |
| 60 | #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ | |
| 61 | #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ | |
| 62 | #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ | |
| 63 | #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ | |
| 64 | #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ | |
| 65 | #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ | |
| 66 | #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ | |
| 62f3b8c8 PB |
67 | #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ |
| 68 | #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ | |
| 69 | #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ | |
| 70 | #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ | |
| 71 | #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ | |
| 72 | #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ | |
| 73 | #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ | |
| b781e558 RE |
74 | |
| 75 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) | |
| 76 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, | |
| 77 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add | |
| 78 | three more to cover cores prior to ARM6. Finally, there are cores which | |
| 79 | implement further extensions in the co-processor space. */ | |
| e74cfd16 PB |
80 | #define ARM_AEXT_V1 ARM_EXT_V1 |
| 81 | #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) | |
| 82 | #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) | |
| 83 | #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) | |
| 84 | #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) | |
| 85 | #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) | |
| 86 | #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) | |
| 87 | #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) | |
| 88 | #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) | |
| 89 | #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) | |
| 90 | #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) | |
| 91 | #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) | |
| 92 | #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) | |
| 93 | #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) | |
| 94 | #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) | |
| 95 | #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) | |
| 96 | #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) | |
| 97 | #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) | |
| 98 | #define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z) | |
| 99 | #define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) | |
| 7e806470 | 100 | #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ |
| 9e3c6df6 PB |
101 | | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ |
| 102 | | ARM_EXT_V6_DSP ) | |
| 62b3e311 PB |
103 | #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) |
| 104 | #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z) | |
| 105 | #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) | |
| 7e806470 | 106 | #define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) |
| 62b3e311 PB |
107 | #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) |
| 108 | #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) | |
| 109 | #define ARM_AEXT_NOTM \ | |
| 9e3c6df6 PB |
110 | (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ |
| 111 | | ARM_EXT_V6_DSP ) | |
| 7e806470 PB |
112 | #define ARM_AEXT_V6M \ |
| 113 | ((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \ | |
| 114 | & ~(ARM_AEXT_NOTM)) | |
| 62b3e311 | 115 | #define ARM_AEXT_V7M \ |
| 7e806470 PB |
116 | ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ |
| 117 | & ~(ARM_AEXT_NOTM)) | |
| 62b3e311 | 118 | #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) |
| 9e3c6df6 PB |
119 | #define ARM_AEXT_V7EM \ |
| 120 | (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) | |
| b781e558 RE |
121 | |
| 122 | /* Processors with specific extensions in the co-processor space. */ | |
| e74cfd16 PB |
123 | #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
| 124 | #define ARM_ARCH_IWMMXT \ | |
| 125 | ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) | |
| 2d447fca JM |
126 | #define ARM_ARCH_IWMMXT2 \ |
| 127 | ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) | |
| e74cfd16 PB |
128 | |
| 129 | #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) | |
| 130 | #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) | |
| 131 | #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) | |
| 62f3b8c8 | 132 | #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) |
| b1cc4aeb | 133 | #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) |
| 62f3b8c8 PB |
134 | #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) |
| 135 | #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) | |
| 136 | #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) | |
| ada65aa3 | 137 | #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
| 9e498214 | 138 | #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ |
| 62f3b8c8 | 139 | | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ |
| b1cc4aeb | 140 | | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) |
| e74cfd16 PB |
141 | #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) |
| 142 | ||
| 143 | /* Deprecated */ | |
| 144 | #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) | |
| b781e558 | 145 | |
| e74cfd16 PB |
146 | #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) |
| 147 | #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) | |
| b781e558 | 148 | |
| e74cfd16 PB |
149 | #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) |
| 150 | #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) | |
| 151 | #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) | |
| b1cc4aeb | 152 | #define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) |
| 62f3b8c8 PB |
153 | #define FPU_ARCH_VFP_V3D16_FP16 \ |
| 154 | ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) | |
| 9e498214 | 155 | #define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) |
| 62f3b8c8 PB |
156 | #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) |
| 157 | #define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) | |
| 158 | #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) | |
| 9e498214 JB |
159 | #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) |
| 160 | #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ | |
| 161 | ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) | |
| 8e79c3df | 162 | #define FPU_ARCH_NEON_FP16 \ |
| 62f3b8c8 | 163 | ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
| e74cfd16 | 164 | #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) |
| 62f3b8c8 PB |
165 | #define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) |
| 166 | #define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) | |
| ada65aa3 | 167 | #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) |
| 62f3b8c8 PB |
168 | #define FPU_ARCH_NEON_VFP_V4 \ |
| 169 | ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) | |
| b781e558 | 170 | |
| e74cfd16 | 171 | #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) |
| b781e558 | 172 | |
| e74cfd16 PB |
173 | #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) |
| 174 | ||
| 175 | #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) | |
| 176 | #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) | |
| 177 | #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) | |
| 178 | #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) | |
| 179 | #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) | |
| 180 | #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) | |
| 181 | #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) | |
| 182 | #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) | |
| 183 | #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) | |
| 184 | #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) | |
| 185 | #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) | |
| 186 | #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) | |
| 187 | #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) | |
| 188 | #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) | |
| 189 | #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) | |
| 190 | #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) | |
| 191 | #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) | |
| 192 | #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) | |
| 193 | #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) | |
| 194 | #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) | |
| 195 | #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) | |
| 196 | #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) | |
| 197 | #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) | |
| 198 | #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) | |
| 7e806470 | 199 | #define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) |
| 62b3e311 PB |
200 | #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) |
| 201 | #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) | |
| 202 | #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) | |
| 203 | #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) | |
| 9e3c6df6 | 204 | #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) |
| b781e558 RE |
205 | |
| 206 | /* Some useful combinations: */ | |
| e74cfd16 PB |
207 | #define ARM_ARCH_NONE ARM_FEATURE (0, 0) |
| 208 | #define FPU_NONE ARM_FEATURE (0, 0) | |
| 209 | #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ | |
| 210 | #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) | |
| 62b3e311 | 211 | #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) |
| e74cfd16 PB |
212 | |
| 213 | /* There are too many feature bits to fit in a single word, so use a | |
| 214 | structure. For simplicity we put all core features in one word and | |
| 215 | everything else in the other. */ | |
| 216 | typedef struct | |
| 217 | { | |
| 218 | unsigned long core; | |
| 219 | unsigned long coproc; | |
| 220 | } arm_feature_set; | |
| 221 | ||
| 222 | #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ | |
| 223 | (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) | |
| 224 | ||
| 225 | #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ | |
| 226 | do { \ | |
| 227 | (TARG).core = (F1).core | (F2).core; \ | |
| 228 | (TARG).coproc = (F1).coproc | (F2).coproc; \ | |
| 229 | } while (0) | |
| 230 | ||
| 231 | #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ | |
| 232 | do { \ | |
| 233 | (TARG).core = (F1).core &~ (F2).core; \ | |
| 234 | (TARG).coproc = (F1).coproc &~ (F2).coproc; \ | |
| 235 | } while (0) | |
| 236 | ||
| 237 | #define ARM_FEATURE(core, coproc) {(core), (coproc)} |