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252b5132 RH |
1 | /* Header file for targets using CGEN: Cpu tools GENerator. |
2 | ||
ac1e9eca | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009 |
4fdf0a75 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GDB, the GNU debugger, and the GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License along | |
19 | with this program; if not, write to the Free Software Foundation, Inc., | |
e172dbf8 | 20 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
ac1e9eca DE |
22 | #ifndef OPCODE_CGEN_H |
23 | #define OPCODE_CGEN_H | |
252b5132 | 24 | |
ea5ca089 | 25 | #include "symcat.h" |
ac1e9eca DE |
26 | #include "cgen/bitset.h" |
27 | ||
252b5132 RH |
28 | /* ??? This file requires bfd.h but only to get bfd_vma. |
29 | Seems like an awful lot to require just to get such a fundamental type. | |
30 | Perhaps the definition of bfd_vma can be moved outside of bfd.h. | |
31 | Or perhaps one could duplicate its definition in another file. | |
32 | Until such time, this file conditionally compiles definitions that require | |
ea6a213a | 33 | bfd_vma using __BFD_H_SEEN__. */ |
252b5132 RH |
34 | |
35 | /* Enums must be defined before they can be used. | |
36 | Allow them to be used in struct definitions, even though the enum must | |
37 | be defined elsewhere. | |
38 | If CGEN_ARCH isn't defined, this file is being included by something other | |
39 | than <arch>-desc.h. */ | |
40 | ||
41 | /* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. | |
42 | The lack of spaces in the arg list is important for non-stdc systems. | |
43 | This file is included by <arch>-desc.h. | |
44 | It can be included independently of <arch>-desc.h, in which case the arch | |
45 | dependent portions will be declared as "unknown_cgen_foo". */ | |
46 | ||
47 | #ifndef CGEN_SYM | |
48 | #define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) | |
49 | #endif | |
50 | ||
51 | /* This file contains the static (unchanging) pieces and as much other stuff | |
52 | as we can reasonably put here. It's generally cleaner to put stuff here | |
53 | rather than having it machine generated if possible. */ | |
54 | ||
55 | /* The assembler syntax is made up of expressions (duh...). | |
56 | At the lowest level the values are mnemonics, register names, numbers, etc. | |
57 | Above that are subexpressions, if any (an example might be the | |
58 | "effective address" in m68k cpus). Subexpressions are wip. | |
59 | At the second highest level are the insns themselves. Above that are | |
60 | pseudo-insns, synthetic insns, and macros, if any. */ | |
61 | \f | |
62 | /* Lots of cpu's have a fixed insn size, or one which rarely changes, | |
63 | and it's generally easier to handle these by treating the insn as an | |
64 | integer type, rather than an array of characters. So we allow targets | |
65 | to control this. When an integer type the value is in host byte order, | |
66 | when an array of characters the value is in target byte order. */ | |
67 | ||
68 | typedef unsigned int CGEN_INSN_INT; | |
69 | #if CGEN_INT_INSN_P | |
70 | typedef CGEN_INSN_INT CGEN_INSN_BYTES; | |
71 | typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; | |
72 | #else | |
73 | typedef unsigned char *CGEN_INSN_BYTES; | |
74 | typedef unsigned char *CGEN_INSN_BYTES_PTR; | |
75 | #endif | |
76 | ||
77 | #ifdef __GNUC__ | |
78 | #define CGEN_INLINE __inline__ | |
79 | #else | |
80 | #define CGEN_INLINE | |
81 | #endif | |
82 | ||
83 | enum cgen_endian | |
84 | { | |
85 | CGEN_ENDIAN_UNKNOWN, | |
86 | CGEN_ENDIAN_LITTLE, | |
87 | CGEN_ENDIAN_BIG | |
88 | }; | |
89 | ||
90 | /* Forward decl. */ | |
91 | ||
92 | typedef struct cgen_insn CGEN_INSN; | |
93 | ||
94 | /* Opaque pointer version for use by external world. */ | |
95 | ||
96 | typedef struct cgen_cpu_desc *CGEN_CPU_DESC; | |
97 | \f | |
98 | /* Attributes. | |
99 | Attributes are used to describe various random things associated with | |
100 | an object (ifield, hardware, operand, insn, whatever) and are specified | |
101 | as name/value pairs. | |
102 | Integer attributes computed at compile time are currently all that's | |
103 | supported, though adding string attributes and run-time computation is | |
104 | straightforward. Integer attribute values are always host int's | |
105 | (signed or unsigned). For portability, this means 32 bits. | |
106 | Integer attributes are further categorized as boolean, bitset, integer, | |
107 | and enum types. Boolean attributes appear frequently enough that they're | |
108 | recorded in one host int. This limits the maximum number of boolean | |
109 | attributes to 32, though that's a *lot* of attributes. */ | |
110 | ||
111 | /* Type of attribute values. */ | |
112 | ||
ea5ca089 DB |
113 | typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; |
114 | typedef int CGEN_ATTR_VALUE_ENUM_TYPE; | |
115 | typedef union | |
116 | { | |
117 | CGEN_ATTR_VALUE_BITSET_TYPE bitset; | |
118 | CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; | |
119 | } CGEN_ATTR_VALUE_TYPE; | |
252b5132 RH |
120 | |
121 | /* Struct to record attribute information. */ | |
122 | ||
123 | typedef struct | |
124 | { | |
125 | /* Boolean attributes. */ | |
126 | unsigned int bool; | |
127 | /* Non-boolean integer attributes. */ | |
128 | CGEN_ATTR_VALUE_TYPE nonbool[1]; | |
129 | } CGEN_ATTR; | |
130 | ||
131 | /* Define a structure member for attributes with N non-boolean entries. | |
132 | There is no maximum number of non-boolean attributes. | |
133 | There is a maximum of 32 boolean attributes (since they are all recorded | |
134 | in one host int). */ | |
135 | ||
136 | #define CGEN_ATTR_TYPE(n) \ | |
137 | struct { unsigned int bool; \ | |
138 | CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } | |
139 | ||
140 | /* Return the boolean attributes. */ | |
141 | ||
142 | #define CGEN_ATTR_BOOLS(a) ((a)->bool) | |
143 | ||
144 | /* Non-boolean attribute numbers are offset by this much. */ | |
145 | ||
146 | #define CGEN_ATTR_NBOOL_OFFSET 32 | |
147 | ||
148 | /* Given a boolean attribute number, return its mask. */ | |
149 | ||
150 | #define CGEN_ATTR_MASK(attr) (1 << (attr)) | |
151 | ||
152 | /* Return the value of boolean attribute ATTR in ATTRS. */ | |
153 | ||
154 | #define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) | |
155 | ||
156 | /* Return value of attribute ATTR in ATTR_TABLE for OBJ. | |
157 | OBJ is a pointer to the entity that has the attributes | |
158 | (??? not used at present but is reserved for future purposes - eventually | |
159 | the goal is to allow recording attributes in source form and computing | |
160 | them lazily at runtime, not sure of the details yet). */ | |
161 | ||
162 | #define CGEN_ATTR_VALUE(obj, attr_table, attr) \ | |
163 | ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ | |
164 | ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ | |
ea5ca089 DB |
165 | : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) |
166 | #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ | |
167 | ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) | |
252b5132 RH |
168 | |
169 | /* Attribute name/value tables. | |
170 | These are used to assist parsing of descriptions at run-time. */ | |
171 | ||
172 | typedef struct | |
173 | { | |
174 | const char * name; | |
ea5ca089 | 175 | unsigned value; |
252b5132 RH |
176 | } CGEN_ATTR_ENTRY; |
177 | ||
178 | /* For each domain (ifld,hw,operand,insn), list of attributes. */ | |
179 | ||
180 | typedef struct | |
181 | { | |
182 | const char * name; | |
183 | const CGEN_ATTR_ENTRY * dfault; | |
184 | const CGEN_ATTR_ENTRY * vals; | |
185 | } CGEN_ATTR_TABLE; | |
186 | \f | |
187 | /* Instruction set variants. */ | |
188 | ||
189 | typedef struct { | |
190 | const char *name; | |
191 | ||
192 | /* Default instruction size (in bits). | |
193 | This is used by the assembler when it encounters an unknown insn. */ | |
194 | unsigned int default_insn_bitsize; | |
195 | ||
196 | /* Base instruction size (in bits). | |
197 | For non-LIW cpus this is generally the length of the smallest insn. | |
198 | For LIW cpus its wip (work-in-progress). For the m32r its 32. */ | |
199 | unsigned int base_insn_bitsize; | |
200 | ||
201 | /* Minimum/maximum instruction size (in bits). */ | |
202 | unsigned int min_insn_bitsize; | |
203 | unsigned int max_insn_bitsize; | |
204 | } CGEN_ISA; | |
205 | ||
206 | /* Machine variants. */ | |
207 | ||
208 | typedef struct { | |
209 | const char *name; | |
210 | /* The argument to bfd_arch_info->scan. */ | |
211 | const char *bfd_name; | |
212 | /* one of enum mach_attr */ | |
213 | int num; | |
81f6038f FCE |
214 | /* parameter from mach->cpu */ |
215 | unsigned int insn_chunk_bitsize; | |
252b5132 RH |
216 | } CGEN_MACH; |
217 | \f | |
218 | /* Parse result (also extraction result). | |
219 | ||
220 | The result of parsing an insn is stored here. | |
221 | To generate the actual insn, this is passed to the insert handler. | |
222 | When printing an insn, the result of extraction is stored here. | |
223 | To print the insn, this is passed to the print handler. | |
224 | ||
225 | It is machine generated so we don't define it here, | |
226 | but we do need a forward decl for the handler fns. | |
227 | ||
228 | There is one member for each possible field in the insn. | |
229 | The type depends on the field. | |
230 | Also recorded here is the computed length of the insn for architectures | |
231 | where it varies. | |
232 | */ | |
233 | ||
234 | typedef struct cgen_fields CGEN_FIELDS; | |
235 | ||
236 | /* Total length of the insn, as recorded in the `fields' struct. */ | |
237 | /* ??? The field insert handler has lots of opportunities for optimization | |
238 | if it ever gets inlined. On architectures where insns all have the same | |
239 | size, may wish to detect that and make this macro a constant - to allow | |
240 | further optimizations. */ | |
241 | ||
242 | #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) | |
243 | \f | |
244 | /* Extraction support for variable length insn sets. */ | |
245 | ||
246 | /* When disassembling we don't know the number of bytes to read at the start. | |
247 | So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest | |
248 | are read when needed. This struct controls this. It is basically the | |
249 | disassemble_info stuff, except that we provide a cache for values already | |
250 | read (since bytes can typically be read several times to fetch multiple | |
251 | operands that may be in them), and that extraction of fields is needed | |
252 | in contexts other than disassembly. */ | |
253 | ||
254 | typedef struct { | |
255 | /* A pointer to the disassemble_info struct. | |
10e05405 | 256 | We don't require dis-asm.h so we use void * for the type here. |
252b5132 | 257 | If NULL, BYTES is full of valid data (VALID == -1). */ |
10e05405 | 258 | void *dis_info; |
252b5132 RH |
259 | /* Points to a working buffer of sufficient size. */ |
260 | unsigned char *insn_bytes; | |
261 | /* Mask of bytes that are valid in INSN_BYTES. */ | |
262 | unsigned int valid; | |
263 | } CGEN_EXTRACT_INFO; | |
264 | \f | |
265 | /* Associated with each insn or expression is a set of "handlers" for | |
266 | performing operations like parsing, printing, etc. These require a bfd_vma | |
267 | value to be passed around but we don't want all applications to need bfd.h. | |
268 | So this stuff is only provided if bfd.h has been included. */ | |
269 | ||
270 | /* Parse handler. | |
271 | CD is a cpu table descriptor. | |
272 | INSN is a pointer to a struct describing the insn being parsed. | |
273 | STRP is a pointer to a pointer to the text being parsed. | |
274 | FIELDS is a pointer to a cgen_fields struct in which the results are placed. | |
275 | If the expression is successfully parsed, *STRP is updated. | |
276 | If not it is left alone. | |
277 | The result is NULL if success or an error message. */ | |
278 | typedef const char * (cgen_parse_fn) | |
10e05405 MM |
279 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
280 | const char **strp_, CGEN_FIELDS *fields_); | |
252b5132 RH |
281 | |
282 | /* Insert handler. | |
283 | CD is a cpu table descriptor. | |
284 | INSN is a pointer to a struct describing the insn being parsed. | |
285 | FIELDS is a pointer to a cgen_fields struct from which the values | |
286 | are fetched. | |
287 | INSNP is a pointer to a buffer in which to place the insn. | |
288 | PC is the pc value of the insn. | |
289 | The result is an error message or NULL if success. */ | |
290 | ||
ea6a213a | 291 | #ifdef __BFD_H_SEEN__ |
252b5132 | 292 | typedef const char * (cgen_insert_fn) |
10e05405 MM |
293 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
294 | CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, | |
295 | bfd_vma pc_); | |
252b5132 RH |
296 | #else |
297 | typedef const char * (cgen_insert_fn) (); | |
298 | #endif | |
299 | ||
300 | /* Extract handler. | |
301 | CD is a cpu table descriptor. | |
302 | INSN is a pointer to a struct describing the insn being parsed. | |
303 | The second argument is a pointer to a struct controlling extraction | |
304 | (only used for variable length insns). | |
305 | EX_INFO is a pointer to a struct for controlling reading of further | |
306 | bytes for the insn. | |
307 | BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). | |
308 | FIELDS is a pointer to a cgen_fields struct in which the results are placed. | |
309 | PC is the pc value of the insn. | |
310 | The result is the length of the insn in bits or zero if not recognized. */ | |
311 | ||
ea6a213a | 312 | #ifdef __BFD_H_SEEN__ |
252b5132 | 313 | typedef int (cgen_extract_fn) |
10e05405 MM |
314 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
315 | CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, | |
316 | CGEN_FIELDS *fields_, bfd_vma pc_); | |
252b5132 RH |
317 | #else |
318 | typedef int (cgen_extract_fn) (); | |
319 | #endif | |
320 | ||
321 | /* Print handler. | |
322 | CD is a cpu table descriptor. | |
323 | INFO is a pointer to the disassembly info. | |
324 | Eg: disassemble_info. It's defined as `PTR' so this file can be included | |
325 | without dis-asm.h. | |
326 | INSN is a pointer to a struct describing the insn being printed. | |
327 | FIELDS is a pointer to a cgen_fields struct. | |
328 | PC is the pc value of the insn. | |
329 | LEN is the length of the insn, in bits. */ | |
330 | ||
ea6a213a | 331 | #ifdef __BFD_H_SEEN__ |
252b5132 | 332 | typedef void (cgen_print_fn) |
10e05405 MM |
333 | (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, |
334 | CGEN_FIELDS *fields_, bfd_vma pc_, int len_); | |
252b5132 RH |
335 | #else |
336 | typedef void (cgen_print_fn) (); | |
337 | #endif | |
338 | ||
339 | /* Parse/insert/extract/print handlers. | |
340 | ||
341 | Indices into the handler tables. | |
342 | We could use pointers here instead, but 90% of them are generally identical | |
343 | and that's a lot of redundant data. Making these unsigned char indices | |
344 | into tables of pointers saves a bit of space. | |
345 | Using indices also keeps assembler code out of the disassembler and | |
346 | vice versa. */ | |
347 | ||
348 | struct cgen_opcode_handler | |
349 | { | |
350 | unsigned char parse, insert, extract, print; | |
351 | }; | |
352 | \f | |
353 | /* Assembler interface. | |
354 | ||
355 | The interface to the assembler is intended to be clean in the sense that | |
356 | libopcodes.a is a standalone entity and could be used with any assembler. | |
357 | Not that one would necessarily want to do that but rather that it helps | |
358 | keep a clean interface. The interface will obviously be slanted towards | |
359 | GAS, but at least it's a start. | |
360 | ??? Note that one possible user of the assembler besides GAS is GDB. | |
361 | ||
362 | Parsing is controlled by the assembler which calls | |
363 | CGEN_SYM (assemble_insn). If it can parse and build the entire insn | |
364 | it doesn't call back to the assembler. If it needs/wants to call back | |
365 | to the assembler, cgen_parse_operand_fn is called which can either | |
366 | ||
367 | - return a number to be inserted in the insn | |
368 | - return a "register" value to be inserted | |
369 | (the register might not be a register per pe) | |
370 | - queue the argument and return a marker saying the expression has been | |
371 | queued (eg: a fix-up) | |
372 | - return an error message indicating the expression wasn't recognizable | |
373 | ||
374 | The result is an error message or NULL for success. | |
375 | The parsed value is stored in the bfd_vma *. */ | |
376 | ||
377 | /* Values for indicating what the caller wants. */ | |
378 | ||
379 | enum cgen_parse_operand_type | |
380 | { | |
381 | CGEN_PARSE_OPERAND_INIT, | |
382 | CGEN_PARSE_OPERAND_INTEGER, | |
90219bd0 AO |
383 | CGEN_PARSE_OPERAND_ADDRESS, |
384 | CGEN_PARSE_OPERAND_SYMBOLIC | |
252b5132 RH |
385 | }; |
386 | ||
387 | /* Values for indicating what was parsed. */ | |
388 | ||
389 | enum cgen_parse_operand_result | |
390 | { | |
391 | CGEN_PARSE_OPERAND_RESULT_NUMBER, | |
392 | CGEN_PARSE_OPERAND_RESULT_REGISTER, | |
393 | CGEN_PARSE_OPERAND_RESULT_QUEUED, | |
394 | CGEN_PARSE_OPERAND_RESULT_ERROR | |
395 | }; | |
396 | ||
ea6a213a | 397 | #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ |
252b5132 | 398 | typedef const char * (cgen_parse_operand_fn) |
10e05405 MM |
399 | (CGEN_CPU_DESC, |
400 | enum cgen_parse_operand_type, const char **, int, int, | |
401 | enum cgen_parse_operand_result *, bfd_vma *); | |
252b5132 RH |
402 | #else |
403 | typedef const char * (cgen_parse_operand_fn) (); | |
404 | #endif | |
405 | ||
406 | /* Set the cgen_parse_operand_fn callback. */ | |
407 | ||
408 | extern void cgen_set_parse_operand_fn | |
10e05405 | 409 | (CGEN_CPU_DESC, cgen_parse_operand_fn); |
252b5132 RH |
410 | |
411 | /* Called before trying to match a table entry with the insn. */ | |
412 | ||
10e05405 | 413 | extern void cgen_init_parse_operand (CGEN_CPU_DESC); |
252b5132 RH |
414 | \f |
415 | /* Operand values (keywords, integers, symbols, etc.) */ | |
416 | ||
417 | /* Types of assembler elements. */ | |
418 | ||
419 | enum cgen_asm_type | |
420 | { | |
421 | CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX | |
422 | }; | |
423 | ||
424 | #ifndef CGEN_ARCH | |
425 | enum cgen_hw_type { CGEN_HW_MAX }; | |
426 | #endif | |
427 | ||
428 | /* List of hardware elements. */ | |
429 | ||
430 | typedef struct | |
431 | { | |
432 | char *name; | |
433 | enum cgen_hw_type type; | |
434 | /* There is currently no example where both index specs and value specs | |
435 | are required, so for now both are clumped under "asm_data". */ | |
436 | enum cgen_asm_type asm_type; | |
10e05405 | 437 | void *asm_data; |
252b5132 RH |
438 | #ifndef CGEN_HW_NBOOL_ATTRS |
439 | #define CGEN_HW_NBOOL_ATTRS 1 | |
440 | #endif | |
441 | CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; | |
442 | #define CGEN_HW_ATTRS(hw) (&(hw)->attrs) | |
443 | } CGEN_HW_ENTRY; | |
444 | ||
445 | /* Return value of attribute ATTR in HW. */ | |
446 | ||
447 | #define CGEN_HW_ATTR_VALUE(hw, attr) \ | |
448 | CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) | |
449 | ||
450 | /* Table of hardware elements for selected mach, computed at runtime. | |
451 | enum cgen_hw_type is an index into this table (specifically `entries'). */ | |
452 | ||
453 | typedef struct { | |
454 | /* Pointer to null terminated table of all compiled in entries. */ | |
455 | const CGEN_HW_ENTRY *init_entries; | |
456 | unsigned int entry_size; /* since the attribute member is variable sized */ | |
457 | /* Array of all entries, initial and run-time added. */ | |
458 | const CGEN_HW_ENTRY **entries; | |
459 | /* Number of elements in `entries'. */ | |
460 | unsigned int num_entries; | |
461 | /* For now, xrealloc is called each time a new entry is added at runtime. | |
462 | ??? May wish to keep track of some slop to reduce the number of calls to | |
463 | xrealloc, except that there's unlikely to be many and not expected to be | |
464 | in speed critical code. */ | |
465 | } CGEN_HW_TABLE; | |
466 | ||
467 | extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name | |
10e05405 | 468 | (CGEN_CPU_DESC, const char *); |
252b5132 | 469 | extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num |
10e05405 | 470 | (CGEN_CPU_DESC, unsigned int); |
252b5132 RH |
471 | |
472 | /* This struct is used to describe things like register names, etc. */ | |
473 | ||
474 | typedef struct cgen_keyword_entry | |
475 | { | |
476 | /* Name (as in register name). */ | |
477 | char * name; | |
478 | ||
479 | /* Value (as in register number). | |
480 | The value cannot be -1 as that is used to indicate "not found". | |
481 | IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ | |
482 | int value; | |
483 | ||
484 | /* Attributes. | |
485 | This should, but technically needn't, appear last. It is a variable sized | |
486 | array in that one architecture may have 1 nonbool attribute and another | |
487 | may have more. Having this last means the non-architecture specific code | |
488 | needn't care. The goal is to eventually record | |
489 | attributes in their raw form, evaluate them at run-time, and cache the | |
490 | values, so this worry will go away anyway. */ | |
491 | /* ??? Moving this last should be done by treating keywords like insn lists | |
492 | and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ | |
493 | /* FIXME: Not used yet. */ | |
494 | #ifndef CGEN_KEYWORD_NBOOL_ATTRS | |
495 | #define CGEN_KEYWORD_NBOOL_ATTRS 1 | |
496 | #endif | |
497 | CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; | |
498 | ||
499 | /* ??? Putting these here means compiled in entries can't be const. | |
500 | Not a really big deal, but something to consider. */ | |
501 | /* Next name hash table entry. */ | |
502 | struct cgen_keyword_entry *next_name; | |
503 | /* Next value hash table entry. */ | |
504 | struct cgen_keyword_entry *next_value; | |
505 | } CGEN_KEYWORD_ENTRY; | |
506 | ||
507 | /* Top level struct for describing a set of related keywords | |
508 | (e.g. register names). | |
509 | ||
510 | This struct supports run-time entry of new values, and hashed lookups. */ | |
511 | ||
512 | typedef struct cgen_keyword | |
513 | { | |
514 | /* Pointer to initial [compiled in] values. */ | |
515 | CGEN_KEYWORD_ENTRY *init_entries; | |
516 | ||
517 | /* Number of entries in `init_entries'. */ | |
518 | unsigned int num_init_entries; | |
519 | ||
520 | /* Hash table used for name lookup. */ | |
521 | CGEN_KEYWORD_ENTRY **name_hash_table; | |
522 | ||
523 | /* Hash table used for value lookup. */ | |
524 | CGEN_KEYWORD_ENTRY **value_hash_table; | |
525 | ||
526 | /* Number of entries in the hash_tables. */ | |
527 | unsigned int hash_table_size; | |
528 | ||
529 | /* Pointer to null keyword "" entry if present. */ | |
530 | const CGEN_KEYWORD_ENTRY *null_entry; | |
3e890047 GK |
531 | |
532 | /* String containing non-alphanumeric characters used | |
533 | in keywords. | |
534 | At present, the highest number of entries used is 1. */ | |
535 | char nonalpha_chars[8]; | |
252b5132 RH |
536 | } CGEN_KEYWORD; |
537 | ||
538 | /* Structure used for searching. */ | |
539 | ||
540 | typedef struct | |
541 | { | |
542 | /* Table being searched. */ | |
543 | const CGEN_KEYWORD *table; | |
544 | ||
545 | /* Specification of what is being searched for. */ | |
546 | const char *spec; | |
547 | ||
548 | /* Current index in hash table. */ | |
549 | unsigned int current_hash; | |
550 | ||
551 | /* Current element in current hash chain. */ | |
552 | CGEN_KEYWORD_ENTRY *current_entry; | |
553 | } CGEN_KEYWORD_SEARCH; | |
554 | ||
555 | /* Lookup a keyword from its name. */ | |
556 | ||
557 | const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name | |
10e05405 | 558 | (CGEN_KEYWORD *, const char *); |
252b5132 RH |
559 | |
560 | /* Lookup a keyword from its value. */ | |
561 | ||
562 | const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value | |
10e05405 | 563 | (CGEN_KEYWORD *, int); |
252b5132 RH |
564 | |
565 | /* Add a keyword. */ | |
566 | ||
10e05405 | 567 | void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); |
252b5132 RH |
568 | |
569 | /* Keyword searching. | |
570 | This can be used to retrieve every keyword, or a subset. */ | |
571 | ||
572 | CGEN_KEYWORD_SEARCH cgen_keyword_search_init | |
10e05405 | 573 | (CGEN_KEYWORD *, const char *); |
252b5132 | 574 | const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next |
10e05405 | 575 | (CGEN_KEYWORD_SEARCH *); |
252b5132 RH |
576 | |
577 | /* Operand value support routines. */ | |
578 | ||
579 | extern const char *cgen_parse_keyword | |
10e05405 | 580 | (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); |
ea6a213a | 581 | #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ |
252b5132 | 582 | extern const char *cgen_parse_signed_integer |
10e05405 | 583 | (CGEN_CPU_DESC, const char **, int, long *); |
252b5132 | 584 | extern const char *cgen_parse_unsigned_integer |
10e05405 | 585 | (CGEN_CPU_DESC, const char **, int, unsigned long *); |
252b5132 | 586 | extern const char *cgen_parse_address |
10e05405 MM |
587 | (CGEN_CPU_DESC, const char **, int, int, |
588 | enum cgen_parse_operand_result *, bfd_vma *); | |
252b5132 | 589 | extern const char *cgen_validate_signed_integer |
10e05405 | 590 | (long, long, long); |
252b5132 | 591 | extern const char *cgen_validate_unsigned_integer |
10e05405 | 592 | (unsigned long, unsigned long, unsigned long); |
252b5132 RH |
593 | #endif |
594 | \f | |
595 | /* Operand modes. */ | |
596 | ||
597 | /* ??? This duplicates the values in arch.h. Revisit. | |
598 | These however need the CGEN_ prefix [as does everything in this file]. */ | |
599 | /* ??? Targets may need to add their own modes so we may wish to move this | |
600 | to <arch>-opc.h, or add a hook. */ | |
601 | ||
602 | enum cgen_mode { | |
603 | CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ | |
604 | CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, | |
605 | CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, | |
606 | CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, | |
607 | CGEN_MODE_TARGET_MAX, | |
608 | CGEN_MODE_INT, CGEN_MODE_UINT, | |
609 | CGEN_MODE_MAX | |
610 | }; | |
611 | ||
612 | /* FIXME: Until simulator is updated. */ | |
613 | ||
614 | #define CGEN_MODE_VM CGEN_MODE_VOID | |
615 | \f | |
616 | /* Operands. */ | |
617 | ||
618 | #ifndef CGEN_ARCH | |
619 | enum cgen_operand_type { CGEN_OPERAND_MAX }; | |
620 | #endif | |
621 | ||
622 | /* "nil" indicator for the operand instance table */ | |
623 | #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX | |
624 | ||
9a2e995d GH |
625 | /* A tree of these structs represents the multi-ifield |
626 | structure of an operand's hw-index value, if it exists. */ | |
627 | ||
628 | struct cgen_ifld; | |
629 | ||
630 | typedef struct cgen_maybe_multi_ifield | |
631 | { | |
632 | int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); | |
633 | n: indexed by array of more cgen_maybe_multi_ifields. */ | |
634 | union | |
635 | { | |
10e05405 | 636 | const void *p; |
4fdf0a75 AM |
637 | const struct cgen_maybe_multi_ifield * multi; |
638 | const struct cgen_ifld * leaf; | |
9a2e995d GH |
639 | } val; |
640 | } | |
641 | CGEN_MAYBE_MULTI_IFLD; | |
642 | ||
252b5132 RH |
643 | /* This struct defines each entry in the operand table. */ |
644 | ||
645 | typedef struct | |
646 | { | |
647 | /* Name as it appears in the syntax string. */ | |
648 | char *name; | |
649 | ||
650 | /* Operand type. */ | |
651 | enum cgen_operand_type type; | |
652 | ||
653 | /* The hardware element associated with this operand. */ | |
654 | enum cgen_hw_type hw_type; | |
655 | ||
656 | /* FIXME: We don't yet record ifield definitions, which we should. | |
657 | When we do it might make sense to delete start/length (since they will | |
658 | be duplicated in the ifield's definition) and replace them with a | |
659 | pointer to the ifield entry. */ | |
660 | ||
661 | /* Bit position. | |
662 | This is just a hint, and may be unused in more complex operands. | |
663 | May be unused for a modifier. */ | |
664 | unsigned char start; | |
665 | ||
666 | /* The number of bits in the operand. | |
667 | This is just a hint, and may be unused in more complex operands. | |
668 | May be unused for a modifier. */ | |
669 | unsigned char length; | |
670 | ||
9a2e995d GH |
671 | /* The (possibly-multi) ifield used as an index for this operand, if it |
672 | is indexed by a field at all. This substitutes / extends the start and | |
673 | length fields above, but unsure at this time whether they are used | |
674 | anywhere. */ | |
675 | CGEN_MAYBE_MULTI_IFLD index_fields; | |
252b5132 RH |
676 | #if 0 /* ??? Interesting idea but relocs tend to get too complicated, |
677 | and ABI dependent, for simple table lookups to work. */ | |
678 | /* Ideally this would be the internal (external?) reloc type. */ | |
679 | int reloc_type; | |
680 | #endif | |
681 | ||
682 | /* Attributes. | |
683 | This should, but technically needn't, appear last. It is a variable sized | |
684 | array in that one architecture may have 1 nonbool attribute and another | |
685 | may have more. Having this last means the non-architecture specific code | |
686 | needn't care, now or tomorrow. The goal is to eventually record | |
687 | attributes in their raw form, evaluate them at run-time, and cache the | |
688 | values, so this worry will go away anyway. */ | |
689 | #ifndef CGEN_OPERAND_NBOOL_ATTRS | |
690 | #define CGEN_OPERAND_NBOOL_ATTRS 1 | |
691 | #endif | |
692 | CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; | |
693 | #define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) | |
694 | } CGEN_OPERAND; | |
695 | ||
696 | /* Return value of attribute ATTR in OPERAND. */ | |
697 | ||
698 | #define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ | |
699 | CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) | |
700 | ||
701 | /* Table of operands for selected mach/isa, computed at runtime. | |
702 | enum cgen_operand_type is an index into this table (specifically | |
703 | `entries'). */ | |
704 | ||
705 | typedef struct { | |
706 | /* Pointer to null terminated table of all compiled in entries. */ | |
707 | const CGEN_OPERAND *init_entries; | |
708 | unsigned int entry_size; /* since the attribute member is variable sized */ | |
709 | /* Array of all entries, initial and run-time added. */ | |
710 | const CGEN_OPERAND **entries; | |
711 | /* Number of elements in `entries'. */ | |
712 | unsigned int num_entries; | |
713 | /* For now, xrealloc is called each time a new entry is added at runtime. | |
714 | ??? May wish to keep track of some slop to reduce the number of calls to | |
715 | xrealloc, except that there's unlikely to be many and not expected to be | |
716 | in speed critical code. */ | |
717 | } CGEN_OPERAND_TABLE; | |
718 | ||
719 | extern const CGEN_OPERAND * cgen_operand_lookup_by_name | |
10e05405 | 720 | (CGEN_CPU_DESC, const char *); |
252b5132 | 721 | extern const CGEN_OPERAND * cgen_operand_lookup_by_num |
10e05405 | 722 | (CGEN_CPU_DESC, int); |
252b5132 RH |
723 | \f |
724 | /* Instruction operand instances. | |
725 | ||
726 | For each instruction, a list of the hardware elements that are read and | |
727 | written are recorded. */ | |
728 | ||
729 | /* The type of the instance. */ | |
730 | ||
731 | enum cgen_opinst_type { | |
732 | /* End of table marker. */ | |
733 | CGEN_OPINST_END = 0, | |
734 | CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT | |
735 | }; | |
736 | ||
737 | typedef struct | |
738 | { | |
739 | /* Input or output indicator. */ | |
740 | enum cgen_opinst_type type; | |
741 | ||
742 | /* Name of operand. */ | |
743 | const char *name; | |
744 | ||
745 | /* The hardware element referenced. */ | |
746 | enum cgen_hw_type hw_type; | |
747 | ||
748 | /* The mode in which the operand is being used. */ | |
749 | enum cgen_mode mode; | |
750 | ||
751 | /* The operand table entry CGEN_OPERAND_NIL if there is none | |
752 | (i.e. an explicit hardware reference). */ | |
753 | enum cgen_operand_type op_type; | |
754 | ||
755 | /* If `operand' is "nil", the index (e.g. into array of registers). */ | |
756 | int index; | |
757 | ||
758 | /* Attributes. | |
759 | ??? This perhaps should be a real attribute struct but there's | |
760 | no current need, so we save a bit of space and just have a set of | |
761 | flags. The interface is such that this can easily be made attributes | |
762 | should it prove useful. */ | |
763 | unsigned int attrs; | |
764 | #define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) | |
765 | /* Return value of attribute ATTR in OPINST. */ | |
766 | #define CGEN_OPINST_ATTR(opinst, attr) \ | |
767 | ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) | |
768 | /* Operand is conditionally referenced (read/written). */ | |
769 | #define CGEN_OPINST_COND_REF 1 | |
770 | } CGEN_OPINST; | |
771 | \f | |
772 | /* Syntax string. | |
773 | ||
774 | Each insn format and subexpression has one of these. | |
775 | ||
776 | The syntax "string" consists of characters (n > 0 && n < 128), and operand | |
777 | values (n >= 128), and is terminated by 0. Operand values are 128 + index | |
778 | into the operand table. The operand table doesn't exist in C, per se, as | |
779 | the data is recorded in the parse/insert/extract/print switch statements. */ | |
780 | ||
f660ee8b | 781 | /* This should be at least as large as necessary for any target. */ |
e281c457 | 782 | #define CGEN_MAX_SYNTAX_ELEMENTS 48 |
f660ee8b FCE |
783 | |
784 | /* A target may know its own precise maximum. Assert that it falls below | |
785 | the above limit. */ | |
0715dc88 PM |
786 | #ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS |
787 | #if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS | |
788 | #error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" | |
252b5132 | 789 | #endif |
f660ee8b FCE |
790 | #endif |
791 | ||
8c1f9e76 | 792 | typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; |
252b5132 RH |
793 | |
794 | typedef struct | |
795 | { | |
0715dc88 | 796 | CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; |
252b5132 RH |
797 | } CGEN_SYNTAX; |
798 | ||
799 | #define CGEN_SYNTAX_STRING(syn) (syn->syntax) | |
800 | #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) | |
8c1f9e76 | 801 | #define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) |
252b5132 RH |
802 | #define CGEN_SYNTAX_FIELD(c) ((c) - 128) |
803 | #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) | |
804 | ||
805 | /* ??? I can't currently think of any case where the mnemonic doesn't come | |
806 | first [and if one ever doesn't building the hash tables will be tricky]. | |
807 | However, we treat mnemonics as just another operand of the instruction. | |
808 | A value of 1 means "this is where the mnemonic appears". 1 isn't | |
809 | special other than it's a non-printable ASCII char. */ | |
810 | ||
811 | #define CGEN_SYNTAX_MNEMONIC 1 | |
812 | #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) | |
813 | \f | |
814 | /* Instruction fields. | |
815 | ||
816 | ??? We currently don't allow adding fields at run-time. | |
817 | Easy to fix when needed. */ | |
818 | ||
819 | typedef struct cgen_ifld { | |
820 | /* Enum of ifield. */ | |
821 | int num; | |
822 | #define CGEN_IFLD_NUM(f) ((f)->num) | |
823 | ||
824 | /* Name of the field, distinguishes it from all other fields. */ | |
825 | const char *name; | |
826 | #define CGEN_IFLD_NAME(f) ((f)->name) | |
827 | ||
828 | /* Default offset, in bits, from the start of the insn to the word | |
829 | containing the field. */ | |
830 | int word_offset; | |
831 | #define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) | |
832 | ||
833 | /* Default length of the word containing the field. */ | |
834 | int word_size; | |
835 | #define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) | |
836 | ||
837 | /* Default starting bit number. | |
838 | Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ | |
839 | int start; | |
840 | #define CGEN_IFLD_START(f) ((f)->start) | |
841 | ||
842 | /* Length of the field, in bits. */ | |
843 | int length; | |
844 | #define CGEN_IFLD_LENGTH(f) ((f)->length) | |
845 | ||
846 | #ifndef CGEN_IFLD_NBOOL_ATTRS | |
847 | #define CGEN_IFLD_NBOOL_ATTRS 1 | |
848 | #endif | |
849 | CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; | |
850 | #define CGEN_IFLD_ATTRS(f) (&(f)->attrs) | |
851 | } CGEN_IFLD; | |
852 | ||
853 | /* Return value of attribute ATTR in IFLD. */ | |
854 | #define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ | |
855 | CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) | |
856 | \f | |
857 | /* Instruction data. */ | |
858 | ||
859 | /* Instruction formats. | |
860 | ||
861 | Instructions are grouped by format. Associated with an instruction is its | |
862 | format. Each insn's opcode table entry contains a format table entry. | |
863 | ??? There is usually very few formats compared with the number of insns, | |
864 | so one can reduce the size of the opcode table by recording the format table | |
865 | as a separate entity. Given that we currently don't, format table entries | |
866 | are also distinguished by their operands. This increases the size of the | |
867 | table, but reduces the number of tables. It's all minutiae anyway so it | |
868 | doesn't really matter [at this point in time]. | |
869 | ||
870 | ??? Support for variable length ISA's is wip. */ | |
871 | ||
872 | /* Accompanying each iformat description is a list of its fields. */ | |
873 | ||
874 | typedef struct { | |
875 | const CGEN_IFLD *ifld; | |
876 | #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) | |
877 | } CGEN_IFMT_IFLD; | |
878 | ||
f660ee8b FCE |
879 | /* This should be at least as large as necessary for any target. */ |
880 | #define CGEN_MAX_IFMT_OPERANDS 16 | |
881 | ||
882 | /* A target may know its own precise maximum. Assert that it falls below | |
883 | the above limit. */ | |
884 | #ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS | |
885 | #if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS | |
886 | #error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" | |
252b5132 | 887 | #endif |
f660ee8b FCE |
888 | #endif |
889 | ||
252b5132 RH |
890 | |
891 | typedef struct | |
892 | { | |
893 | /* Length that MASK and VALUE have been calculated to | |
894 | [VALUE is recorded elsewhere]. | |
895 | Normally it is base_insn_bitsize. On [V]LIW architectures where the base | |
896 | insn size may be larger than the size of an insn, this field is less than | |
897 | base_insn_bitsize. */ | |
898 | unsigned char mask_length; | |
899 | #define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) | |
900 | ||
901 | /* Total length of instruction, in bits. */ | |
902 | unsigned char length; | |
903 | #define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) | |
904 | ||
905 | /* Mask to apply to the first MASK_LENGTH bits. | |
906 | Each insn's value is stored with the insn. | |
907 | The first step in recognizing an insn for disassembly is | |
908 | (opcode & mask) == value. */ | |
909 | CGEN_INSN_INT mask; | |
910 | #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) | |
911 | ||
912 | /* Instruction fields. | |
913 | +1 for trailing NULL. */ | |
914 | CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; | |
915 | #define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) | |
916 | } CGEN_IFMT; | |
917 | ||
918 | /* Instruction values. */ | |
919 | ||
920 | typedef struct | |
921 | { | |
922 | /* The opcode portion of the base insn. */ | |
923 | CGEN_INSN_INT base_value; | |
924 | ||
925 | #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS | |
926 | /* Extra opcode values beyond base_value. */ | |
927 | unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; | |
928 | #endif | |
929 | } CGEN_IVALUE; | |
930 | ||
931 | /* Instruction opcode table. | |
932 | This contains the syntax and format data of an instruction. */ | |
933 | ||
934 | /* ??? Some ports already have an opcode table yet still need to use the rest | |
935 | of what cgen_insn has. Plus keeping the opcode data with the operand | |
936 | instance data can create a pretty big file. So we keep them separately. | |
937 | Not sure this is a good idea in the long run. */ | |
938 | ||
939 | typedef struct | |
940 | { | |
941 | /* Indices into parse/insert/extract/print handler tables. */ | |
942 | struct cgen_opcode_handler handlers; | |
943 | #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) | |
944 | ||
945 | /* Syntax string. */ | |
946 | CGEN_SYNTAX syntax; | |
947 | #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) | |
948 | ||
949 | /* Format entry. */ | |
950 | const CGEN_IFMT *format; | |
951 | #define CGEN_OPCODE_FORMAT(opc) ((opc)->format) | |
952 | #define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) | |
953 | #define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) | |
954 | #define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) | |
955 | ||
956 | /* Instruction opcode value. */ | |
957 | CGEN_IVALUE value; | |
958 | #define CGEN_OPCODE_VALUE(opc) (& (opc)->value) | |
959 | #define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) | |
960 | #define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) | |
961 | } CGEN_OPCODE; | |
962 | ||
963 | /* Instruction attributes. | |
964 | This is made a published type as applications can cache a pointer to | |
965 | the attributes for speed. */ | |
966 | ||
967 | #ifndef CGEN_INSN_NBOOL_ATTRS | |
968 | #define CGEN_INSN_NBOOL_ATTRS 1 | |
969 | #endif | |
970 | typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; | |
971 | ||
972 | /* Enum of architecture independent attributes. */ | |
973 | ||
974 | #ifndef CGEN_ARCH | |
975 | /* ??? Numbers here are recorded in two places. */ | |
976 | typedef enum cgen_insn_attr { | |
977 | CGEN_INSN_ALIAS = 0 | |
978 | } CGEN_INSN_ATTR; | |
ea5ca089 | 979 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS)) |
252b5132 RH |
980 | #endif |
981 | ||
982 | /* This struct defines each entry in the instruction table. */ | |
983 | ||
984 | typedef struct | |
985 | { | |
986 | /* Each real instruction is enumerated. */ | |
987 | /* ??? This may go away in time. */ | |
988 | int num; | |
989 | #define CGEN_INSN_NUM(insn) ((insn)->base->num) | |
990 | ||
991 | /* Name of entry (that distinguishes it from all other entries). */ | |
992 | /* ??? If mnemonics have operands, try to print full mnemonic. */ | |
993 | const char *name; | |
994 | #define CGEN_INSN_NAME(insn) ((insn)->base->name) | |
995 | ||
996 | /* Mnemonic. This is used when parsing and printing the insn. | |
997 | In the case of insns that have operands on the mnemonics, this is | |
998 | only the constant part. E.g. for conditional execution of an `add' insn, | |
999 | where the full mnemonic is addeq, addne, etc., and the condition is | |
1000 | treated as an operand, this is only "add". */ | |
1001 | const char *mnemonic; | |
1002 | #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) | |
1003 | ||
1004 | /* Total length of instruction, in bits. */ | |
1005 | int bitsize; | |
1006 | #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) | |
1007 | ||
1008 | #if 0 /* ??? Disabled for now as there is a problem with embedded newlines | |
1009 | and the table is already pretty big. Should perhaps be moved | |
1010 | to a file of its own. */ | |
1011 | /* Semantics, as RTL. */ | |
1012 | /* ??? Plain text or bytecodes? */ | |
1013 | /* ??? Note that the operand instance table could be computed at run-time | |
1014 | if we parse this and cache the results. Something to eventually do. */ | |
1015 | const char *rtx; | |
1016 | #define CGEN_INSN_RTX(insn) ((insn)->base->rtx) | |
1017 | #endif | |
1018 | ||
1019 | /* Attributes. | |
1020 | This must appear last. It is a variable sized array in that one | |
1021 | architecture may have 1 nonbool attribute and another may have more. | |
1022 | Having this last means the non-architecture specific code needn't | |
1023 | care. The goal is to eventually record attributes in their raw form, | |
1024 | evaluate them at run-time, and cache the values, so this worry will go | |
1025 | away anyway. */ | |
1026 | CGEN_INSN_ATTR_TYPE attrs; | |
1027 | #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) | |
1028 | /* Return value of attribute ATTR in INSN. */ | |
1029 | #define CGEN_INSN_ATTR_VALUE(insn, attr) \ | |
1030 | CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) | |
ea5ca089 DB |
1031 | #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ |
1032 | CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) | |
252b5132 RH |
1033 | } CGEN_IBASE; |
1034 | ||
1035 | /* Return non-zero if INSN is the "invalid" insn marker. */ | |
1036 | ||
1037 | #define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) | |
1038 | ||
1039 | /* Main struct contain instruction information. | |
1040 | BASE is always present, the rest is present only if asked for. */ | |
1041 | ||
1042 | struct cgen_insn | |
1043 | { | |
1044 | /* ??? May be of use to put a type indicator here. | |
1045 | Then this struct could different info for different classes of insns. */ | |
1046 | /* ??? A speedup can be had by moving `base' into this struct. | |
1047 | Maybe later. */ | |
1048 | const CGEN_IBASE *base; | |
1049 | const CGEN_OPCODE *opcode; | |
1050 | const CGEN_OPINST *opinst; | |
3d5c4f10 JJ |
1051 | |
1052 | /* Regex to disambiguate overloaded opcodes */ | |
1053 | void *rx; | |
1054 | #define CGEN_INSN_RX(insn) ((insn)->rx) | |
1055 | #define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) | |
252b5132 RH |
1056 | }; |
1057 | ||
1058 | /* Instruction lists. | |
1059 | This is used for adding new entries and for creating the hash lists. */ | |
1060 | ||
1061 | typedef struct cgen_insn_list | |
1062 | { | |
1063 | struct cgen_insn_list *next; | |
1064 | const CGEN_INSN *insn; | |
1065 | } CGEN_INSN_LIST; | |
1066 | ||
1067 | /* Table of instructions. */ | |
1068 | ||
1069 | typedef struct | |
1070 | { | |
1071 | const CGEN_INSN *init_entries; | |
1072 | unsigned int entry_size; /* since the attribute member is variable sized */ | |
1073 | unsigned int num_init_entries; | |
1074 | CGEN_INSN_LIST *new_entries; | |
1075 | } CGEN_INSN_TABLE; | |
1076 | ||
1077 | /* Return number of instructions. This includes any added at run-time. */ | |
1078 | ||
10e05405 MM |
1079 | extern int cgen_insn_count (CGEN_CPU_DESC); |
1080 | extern int cgen_macro_insn_count (CGEN_CPU_DESC); | |
252b5132 RH |
1081 | |
1082 | /* Macros to access the other insn elements not recorded in CGEN_IBASE. */ | |
1083 | ||
1084 | /* Fetch INSN's operand instance table. */ | |
1085 | /* ??? Doesn't handle insns added at runtime. */ | |
1086 | #define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) | |
1087 | ||
1088 | /* Return INSN's opcode table entry. */ | |
1089 | #define CGEN_INSN_OPCODE(insn) ((insn)->opcode) | |
1090 | ||
1091 | /* Return INSN's handler data. */ | |
1092 | #define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) | |
1093 | ||
1094 | /* Return INSN's syntax. */ | |
1095 | #define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) | |
1096 | ||
1097 | /* Return size of base mask in bits. */ | |
1098 | #define CGEN_INSN_MASK_BITSIZE(insn) \ | |
1099 | CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) | |
1100 | ||
1101 | /* Return mask of base part of INSN. */ | |
1102 | #define CGEN_INSN_BASE_MASK(insn) \ | |
1103 | CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) | |
1104 | ||
1105 | /* Return value of base part of INSN. */ | |
1106 | #define CGEN_INSN_BASE_VALUE(insn) \ | |
1107 | CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) | |
e8da1bf1 DE |
1108 | |
1109 | /* Standard way to test whether INSN is supported by MACH. | |
1110 | MACH is one of enum mach_attr. | |
1111 | The "|1" is because the base mach is always selected. */ | |
1112 | #define CGEN_INSN_MACH_HAS_P(insn, mach) \ | |
1113 | ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) | |
252b5132 RH |
1114 | \f |
1115 | /* Macro instructions. | |
1116 | Macro insns aren't real insns, they map to one or more real insns. | |
1117 | E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or | |
1118 | some such. | |
1119 | ||
1120 | Macro insns can expand to nothing (e.g. a nop that is optimized away). | |
1121 | This is useful in multi-insn macros that build a constant in a register. | |
1122 | Of course this isn't the default behaviour and must be explicitly enabled. | |
1123 | ||
1124 | Assembly of macro-insns is relatively straightforward. Disassembly isn't. | |
1125 | However, disassembly of at least some kinds of macro insns is important | |
1126 | in order that the disassembled code preserve the readability of the original | |
1127 | insn. What is attempted here is to disassemble all "simple" macro-insns, | |
1128 | where "simple" is currently defined to mean "expands to one real insn". | |
1129 | ||
1130 | Simple macro-insns are handled specially. They are emitted as ALIAS's | |
1131 | of real insns. This simplifies their handling since there's usually more | |
1132 | of them than any other kind of macro-insn, and proper disassembly of them | |
1133 | falls out for free. */ | |
1134 | ||
1135 | /* For each macro-insn there may be multiple expansion possibilities, | |
1136 | depending on the arguments. This structure is accessed via the `data' | |
1137 | member of CGEN_INSN. */ | |
1138 | ||
1139 | typedef struct cgen_minsn_expansion { | |
1140 | /* Function to do the expansion. | |
1141 | If the expansion fails (e.g. "no match") NULL is returned. | |
1142 | Space for the expansion is obtained with malloc. | |
1143 | It is up to the caller to free it. */ | |
10e05405 MM |
1144 | const char * (* fn) |
1145 | (const struct cgen_minsn_expansion *, | |
1146 | const char *, const char **, int *, | |
1147 | CGEN_OPERAND **); | |
252b5132 RH |
1148 | #define CGEN_MIEXPN_FN(ex) ((ex)->fn) |
1149 | ||
1150 | /* Instruction(s) the macro expands to. | |
1151 | The format of STR is defined by FN. | |
1152 | It is typically the assembly code of the real insn, but it could also be | |
1153 | the original Scheme expression or a tokenized form of it (with FN being | |
1154 | an appropriate interpreter). */ | |
1155 | const char * str; | |
1156 | #define CGEN_MIEXPN_STR(ex) ((ex)->str) | |
1157 | } CGEN_MINSN_EXPANSION; | |
1158 | ||
1159 | /* Normal expander. | |
1160 | When supported, this function will convert the input string to another | |
1161 | string and the parser will be invoked recursively. The output string | |
1162 | may contain further macro invocations. */ | |
1163 | ||
1164 | extern const char * cgen_expand_macro_insn | |
10e05405 MM |
1165 | (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, |
1166 | const char *, const char **, int *, CGEN_OPERAND **); | |
252b5132 RH |
1167 | \f |
1168 | /* The assembler insn table is hashed based on some function of the mnemonic | |
1169 | (the actually hashing done is up to the target, but we provide a few | |
1170 | examples like the first letter or a function of the entire mnemonic). */ | |
1171 | ||
1172 | extern CGEN_INSN_LIST * cgen_asm_lookup_insn | |
10e05405 | 1173 | (CGEN_CPU_DESC, const char *); |
252b5132 RH |
1174 | #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) |
1175 | #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) | |
1176 | ||
1177 | /* The disassembler insn table is hashed based on some function of machine | |
1178 | instruction (the actually hashing done is up to the target). */ | |
1179 | ||
1180 | extern CGEN_INSN_LIST * cgen_dis_lookup_insn | |
10e05405 | 1181 | (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); |
252b5132 RH |
1182 | /* FIXME: delete these two */ |
1183 | #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) | |
1184 | #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) | |
1185 | \f | |
1186 | /* The CPU description. | |
1187 | A copy of this is created when the cpu table is "opened". | |
1188 | All global state information is recorded here. | |
1189 | Access macros are provided for "public" members. */ | |
1190 | ||
1191 | typedef struct cgen_cpu_desc | |
1192 | { | |
1193 | /* Bitmap of selected machine(s) (a la BFD machine number). */ | |
1194 | int machs; | |
1195 | ||
ea5ca089 DB |
1196 | /* Bitmap of selected isa(s). */ |
1197 | CGEN_BITSET *isas; | |
1198 | #define CGEN_CPU_ISAS(cd) ((cd)->isas) | |
252b5132 RH |
1199 | |
1200 | /* Current endian. */ | |
1201 | enum cgen_endian endian; | |
1202 | #define CGEN_CPU_ENDIAN(cd) ((cd)->endian) | |
1203 | ||
1204 | /* Current insn endian. */ | |
1205 | enum cgen_endian insn_endian; | |
1206 | #define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) | |
1207 | ||
1208 | /* Word size (in bits). */ | |
1209 | /* ??? Or maybe maximum word size - might we ever need to allow a cpu table | |
1210 | to be opened for both sparc32/sparc64? | |
1211 | ??? Another alternative is to create a table of selected machs and | |
1212 | lazily fetch the data from there. */ | |
1213 | unsigned int word_bitsize; | |
1214 | ||
81f6038f FCE |
1215 | /* Instruction chunk size (in bits), for purposes of endianness |
1216 | conversion. */ | |
1217 | unsigned int insn_chunk_bitsize; | |
1218 | ||
252b5132 RH |
1219 | /* Indicator if sizes are unknown. |
1220 | This is used by default_insn_bitsize,base_insn_bitsize if there is a | |
1221 | difference between the selected isa's. */ | |
1222 | #define CGEN_SIZE_UNKNOWN 65535 | |
1223 | ||
1224 | /* Default instruction size (in bits). | |
1225 | This is used by the assembler when it encounters an unknown insn. */ | |
1226 | unsigned int default_insn_bitsize; | |
1227 | ||
1228 | /* Base instruction size (in bits). | |
1229 | For non-LIW cpus this is generally the length of the smallest insn. | |
1230 | For LIW cpus its wip (work-in-progress). For the m32r its 32. */ | |
1231 | unsigned int base_insn_bitsize; | |
1232 | ||
1233 | /* Minimum/maximum instruction size (in bits). */ | |
1234 | unsigned int min_insn_bitsize; | |
1235 | unsigned int max_insn_bitsize; | |
1236 | ||
1237 | /* Instruction set variants. */ | |
1238 | const CGEN_ISA *isa_table; | |
1239 | ||
1240 | /* Machine variants. */ | |
1241 | const CGEN_MACH *mach_table; | |
1242 | ||
1243 | /* Hardware elements. */ | |
1244 | CGEN_HW_TABLE hw_table; | |
1245 | ||
1246 | /* Instruction fields. */ | |
1247 | const CGEN_IFLD *ifld_table; | |
1248 | ||
1249 | /* Operands. */ | |
1250 | CGEN_OPERAND_TABLE operand_table; | |
1251 | ||
1252 | /* Main instruction table. */ | |
1253 | CGEN_INSN_TABLE insn_table; | |
1254 | #define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) | |
1255 | ||
1256 | /* Macro instructions are defined separately and are combined with real | |
1257 | insns during hash table computation. */ | |
1258 | CGEN_INSN_TABLE macro_insn_table; | |
1259 | ||
1260 | /* Copy of CGEN_INT_INSN_P. */ | |
1261 | int int_insn_p; | |
1262 | ||
1263 | /* Called to rebuild the tables after something has changed. */ | |
10e05405 | 1264 | void (*rebuild_tables) (CGEN_CPU_DESC); |
252b5132 RH |
1265 | |
1266 | /* Operand parser callback. */ | |
1267 | cgen_parse_operand_fn * parse_operand_fn; | |
1268 | ||
1269 | /* Parse/insert/extract/print cover fns for operands. */ | |
1270 | const char * (*parse_operand) | |
10e05405 | 1271 | (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); |
ea6a213a | 1272 | #ifdef __BFD_H_SEEN__ |
252b5132 | 1273 | const char * (*insert_operand) |
10e05405 MM |
1274 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, |
1275 | CGEN_INSN_BYTES_PTR, bfd_vma pc_); | |
252b5132 | 1276 | int (*extract_operand) |
10e05405 MM |
1277 | (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, |
1278 | CGEN_FIELDS *fields_, bfd_vma pc_); | |
252b5132 | 1279 | void (*print_operand) |
10e05405 MM |
1280 | (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, |
1281 | void const *attrs_, bfd_vma pc_, int length_); | |
252b5132 RH |
1282 | #else |
1283 | const char * (*insert_operand) (); | |
1284 | int (*extract_operand) (); | |
1285 | void (*print_operand) (); | |
1286 | #endif | |
1287 | #define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) | |
1288 | #define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) | |
1289 | #define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) | |
1290 | #define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) | |
1291 | ||
1292 | /* Size of CGEN_FIELDS struct. */ | |
1293 | unsigned int sizeof_fields; | |
1294 | #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) | |
1295 | ||
1296 | /* Set the bitsize field. */ | |
10e05405 | 1297 | void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); |
252b5132 RH |
1298 | #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) |
1299 | ||
1300 | /* CGEN_FIELDS accessors. */ | |
1301 | int (*get_int_operand) | |
10e05405 | 1302 | (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); |
252b5132 | 1303 | void (*set_int_operand) |
10e05405 | 1304 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); |
ea6a213a | 1305 | #ifdef __BFD_H_SEEN__ |
252b5132 | 1306 | bfd_vma (*get_vma_operand) |
10e05405 | 1307 | (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); |
252b5132 | 1308 | void (*set_vma_operand) |
10e05405 | 1309 | (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); |
252b5132 RH |
1310 | #else |
1311 | long (*get_vma_operand) (); | |
1312 | void (*set_vma_operand) (); | |
1313 | #endif | |
1314 | #define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) | |
1315 | #define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) | |
1316 | #define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) | |
1317 | #define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) | |
1318 | ||
1319 | /* Instruction parse/insert/extract/print handlers. */ | |
1320 | /* FIXME: make these types uppercase. */ | |
1321 | cgen_parse_fn * const *parse_handlers; | |
1322 | cgen_insert_fn * const *insert_handlers; | |
1323 | cgen_extract_fn * const *extract_handlers; | |
1324 | cgen_print_fn * const *print_handlers; | |
1325 | #define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) | |
1326 | #define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) | |
1327 | #define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) | |
1328 | #define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) | |
1329 | ||
1330 | /* Return non-zero if insn should be added to hash table. */ | |
10e05405 | 1331 | int (* asm_hash_p) (const CGEN_INSN *); |
252b5132 RH |
1332 | |
1333 | /* Assembler hash function. */ | |
10e05405 | 1334 | unsigned int (* asm_hash) (const char *); |
252b5132 RH |
1335 | |
1336 | /* Number of entries in assembler hash table. */ | |
1337 | unsigned int asm_hash_size; | |
1338 | ||
1339 | /* Return non-zero if insn should be added to hash table. */ | |
10e05405 | 1340 | int (* dis_hash_p) (const CGEN_INSN *); |
252b5132 RH |
1341 | |
1342 | /* Disassembler hash function. */ | |
10e05405 | 1343 | unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); |
252b5132 RH |
1344 | |
1345 | /* Number of entries in disassembler hash table. */ | |
1346 | unsigned int dis_hash_size; | |
1347 | ||
1348 | /* Assembler instruction hash table. */ | |
1349 | CGEN_INSN_LIST **asm_hash_table; | |
1350 | CGEN_INSN_LIST *asm_hash_table_entries; | |
1351 | ||
1352 | /* Disassembler instruction hash table. */ | |
1353 | CGEN_INSN_LIST **dis_hash_table; | |
1354 | CGEN_INSN_LIST *dis_hash_table_entries; | |
60f036a2 | 1355 | |
68e324a2 NC |
1356 | /* This field could be turned into a bitfield if room for other flags is needed. */ |
1357 | unsigned int signed_overflow_ok_p; | |
60f036a2 | 1358 | |
252b5132 RH |
1359 | } CGEN_CPU_TABLE; |
1360 | ||
1361 | /* wip */ | |
1362 | #ifndef CGEN_WORD_ENDIAN | |
1363 | #define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) | |
1364 | #endif | |
1365 | #ifndef CGEN_INSN_WORD_ENDIAN | |
1366 | #define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) | |
1367 | #endif | |
1368 | \f | |
1369 | /* Prototypes of major functions. */ | |
1370 | /* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. | |
1371 | Not the init fns though, as that would drag in things that mightn't be | |
1372 | used and might not even exist. */ | |
1373 | ||
1374 | /* Argument types to cpu_open. */ | |
1375 | ||
1376 | enum cgen_cpu_open_arg { | |
1377 | CGEN_CPU_OPEN_END, | |
1378 | /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ | |
1379 | CGEN_CPU_OPEN_ISAS, | |
1380 | /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ | |
1381 | CGEN_CPU_OPEN_MACHS, | |
1382 | /* Select machine, arg is mach's bfd name. | |
1383 | Multiple machines can be specified by repeated use. */ | |
1384 | CGEN_CPU_OPEN_BFDMACH, | |
1385 | /* Select endian, arg is CGEN_ENDIAN_*. */ | |
1386 | CGEN_CPU_OPEN_ENDIAN | |
1387 | }; | |
1388 | ||
1389 | /* Open a cpu descriptor table for use. | |
1390 | ??? We only support ISO C stdargs here, not K&R. | |
1391 | Laziness, plus experiment to see if anything requires K&R - eventually | |
1392 | K&R will no longer be supported - e.g. GDB is currently trying this. */ | |
1393 | ||
1394 | extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); | |
1395 | ||
1396 | /* Cover fn to handle simple case. */ | |
1397 | ||
10e05405 MM |
1398 | extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) |
1399 | (const char *mach_name_, enum cgen_endian endian_); | |
252b5132 RH |
1400 | |
1401 | /* Close it. */ | |
1402 | ||
10e05405 | 1403 | extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); |
252b5132 RH |
1404 | |
1405 | /* Initialize the opcode table for use. | |
1406 | Called by init_asm/init_dis. */ | |
1407 | ||
10e05405 | 1408 | extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); |
252b5132 | 1409 | |
3d5c4f10 JJ |
1410 | /* build the insn selection regex. |
1411 | called by init_opcode_table */ | |
1412 | ||
10e05405 | 1413 | extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); |
3d5c4f10 | 1414 | |
252b5132 RH |
1415 | /* Initialize the ibld table for use. |
1416 | Called by init_asm/init_dis. */ | |
1417 | ||
10e05405 | 1418 | extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); |
252b5132 RH |
1419 | |
1420 | /* Initialize an cpu table for assembler or disassembler use. | |
1421 | These must be called immediately after cpu_open. */ | |
1422 | ||
10e05405 MM |
1423 | extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); |
1424 | extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); | |
252b5132 RH |
1425 | |
1426 | /* Initialize the operand instance table for use. */ | |
1427 | ||
10e05405 | 1428 | extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); |
252b5132 RH |
1429 | |
1430 | /* Assemble an instruction. */ | |
1431 | ||
1432 | extern const CGEN_INSN * CGEN_SYM (assemble_insn) | |
10e05405 MM |
1433 | (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, |
1434 | CGEN_INSN_BYTES_PTR, char **); | |
252b5132 RH |
1435 | |
1436 | extern const CGEN_KEYWORD CGEN_SYM (operand_mach); | |
10e05405 | 1437 | extern int CGEN_SYM (get_mach) (const char *); |
252b5132 RH |
1438 | |
1439 | /* Operand index computation. */ | |
1440 | extern const CGEN_INSN * cgen_lookup_insn | |
10e05405 MM |
1441 | (CGEN_CPU_DESC, const CGEN_INSN * insn_, |
1442 | CGEN_INSN_INT int_value_, unsigned char *bytes_value_, | |
1443 | int length_, CGEN_FIELDS *fields_, int alias_p_); | |
252b5132 | 1444 | extern void cgen_get_insn_operands |
10e05405 MM |
1445 | (CGEN_CPU_DESC, const CGEN_INSN * insn_, |
1446 | const CGEN_FIELDS *fields_, int *indices_); | |
252b5132 | 1447 | extern const CGEN_INSN * cgen_lookup_get_insn_operands |
10e05405 MM |
1448 | (CGEN_CPU_DESC, const CGEN_INSN *insn_, |
1449 | CGEN_INSN_INT int_value_, unsigned char *bytes_value_, | |
1450 | int length_, int *indices_, CGEN_FIELDS *fields_); | |
252b5132 RH |
1451 | |
1452 | /* Cover fns to bfd_get/set. */ | |
1453 | ||
1454 | extern CGEN_INSN_INT cgen_get_insn_value | |
10e05405 | 1455 | (CGEN_CPU_DESC, unsigned char *, int); |
252b5132 | 1456 | extern void cgen_put_insn_value |
10e05405 | 1457 | (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); |
252b5132 RH |
1458 | |
1459 | /* Read in a cpu description file. | |
1460 | ??? For future concerns, including adding instructions to the assembler/ | |
1461 | disassembler at run-time. */ | |
1462 | ||
10e05405 | 1463 | extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); |
252b5132 | 1464 | |
60f036a2 | 1465 | /* Allow signed overflow of instruction fields. */ |
10e05405 | 1466 | extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); |
60f036a2 AH |
1467 | |
1468 | /* Generate an error message if a signed field in an instruction overflows. */ | |
10e05405 | 1469 | extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); |
60f036a2 AH |
1470 | |
1471 | /* Will an error message be generated if a signed field in an instruction overflows ? */ | |
10e05405 | 1472 | extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); |
60f036a2 | 1473 | |
ac1e9eca | 1474 | #endif /* OPCODE_CGEN_H */ |