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1 | /* crx.h -- Header file for CRX opcode and register tables. |
2 | Copyright 2004 Free Software Foundation, Inc. | |
3 | Contributed by Tomer Levi, NSC, Israel. | |
4 | Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. | |
5 | Updates, BFDizing, GNUifying and ELF support by Tomer Levi. | |
6 | ||
7 | This file is part of GAS, GDB and the GNU binutils. | |
8 | ||
9 | GAS, GDB, and GNU binutils is free software; you can redistribute it | |
10 | and/or modify it under the terms of the GNU General Public License as | |
11 | published by the Free Software Foundation; either version 2, or (at your | |
12 | option) any later version. | |
13 | ||
14 | GAS, GDB, and GNU binutils are distributed in the hope that they will be | |
15 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #ifndef _CRX_H_ | |
24 | #define _CRX_H_ | |
25 | ||
26 | /* CRX core/debug Registers : | |
27 | The enums are used as indices to CRX registers table (crx_regtab). | |
28 | Therefore, order MUST be preserved. */ | |
29 | ||
30 | typedef enum | |
31 | { | |
32 | /* 32-bit general purpose registers. */ | |
33 | r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, | |
34 | r10, r11, r12, r13, r14, r15, ra, sp, | |
35 | /* 32-bit user registers. */ | |
36 | u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, | |
37 | u10, u11, u12, u13, u14, u15, ura, usp, | |
38 | /* hi and lo registers. */ | |
39 | hi, lo, | |
40 | /* hi and lo user registers. */ | |
41 | uhi, ulo, | |
42 | /* Processor Status Register. */ | |
43 | psr, | |
44 | /* Configuration Register. */ | |
45 | cfg, | |
46 | /* Coprocessor Configuration Register. */ | |
47 | cpcfg, | |
48 | /* Cashe Configuration Register. */ | |
49 | ccfg, | |
50 | /* Interrupt Base Register. */ | |
51 | intbase, | |
52 | /* Interrupt Stack Pointer Register. */ | |
53 | isp, | |
54 | /* Coprocessor Enable Register. */ | |
55 | cen, | |
56 | /* Program Counter Register. */ | |
57 | pc, | |
58 | /* Not a register. */ | |
59 | nullregister, | |
60 | MAX_REG | |
61 | } | |
62 | reg; | |
63 | ||
64 | /* CRX Coprocessor registers and special registers : | |
65 | The enums are used as indices to CRX coprocessor registers table | |
66 | (crx_copregtab). Therefore, order MUST be preserved. */ | |
67 | ||
68 | typedef enum | |
69 | { | |
70 | /* Coprocessor registers. */ | |
71 | c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, | |
72 | c9, c10, c11, c12, c13, c14, c15, | |
73 | /* Coprocessor special registers. */ | |
74 | cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, | |
75 | cs9, cs10, cs11, cs12, cs13, cs14, cs15, | |
76 | /* Not a Coprocessor register. */ | |
77 | nullcopregister, | |
78 | MAX_COPREG | |
79 | } | |
80 | copreg; | |
81 | ||
82 | /* CRX Register types. */ | |
83 | ||
84 | typedef enum | |
85 | { | |
86 | CRX_PC_REGTYPE, /* pc type */ | |
87 | CRX_R_REGTYPE, /* r<N> */ | |
88 | CRX_U_REGTYPE, /* u<N> */ | |
89 | CRX_C_REGTYPE, /* c<N> */ | |
90 | CRX_CS_REGTYPE, /* cs<N> */ | |
91 | CRX_MTPR_REGTYPE, /* mtpr */ | |
92 | CRX_CFG_REGTYPE /* *hi|lo, *cfg, psr */ | |
93 | } | |
94 | reg_type; | |
95 | ||
96 | /* CRX argument types : | |
97 | The argument types correspond to instructions operands | |
98 | ||
99 | Argument types : | |
100 | r - register | |
101 | c - constant | |
102 | d - displacement | |
103 | ic - immediate | |
104 | icr - index register | |
105 | rbase - register base | |
106 | s - star ('*') | |
107 | copr - coprocessor register | |
108 | copsr - coprocessor special register. */ | |
109 | ||
110 | typedef enum | |
111 | { | |
112 | arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc, | |
113 | arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr, | |
114 | /* Not an argument. */ | |
115 | nullargs | |
116 | } | |
117 | argtype; | |
118 | ||
119 | /* CRX operand types : | |
120 | The operand types correspond to instructions operands | |
121 | ||
122 | Operand Types : | |
123 | cst4 - 4-bit encoded constant | |
124 | iN - N-bit immediate field | |
125 | d, dispsN - N-bit immediate signed displacement | |
126 | dispuN - N-bit immediate unsigned displacement | |
127 | absN - N-bit absolute address | |
128 | rbase - 4-bit genaral-purpose register specifier | |
129 | regr - 4-bit genaral-purpose register specifier | |
130 | regr8 - 8-bit register address space | |
131 | copregr - coprocessor register | |
132 | copsregr - coprocessor special register | |
133 | scl2 - 2-bit scaling factor for memory index | |
134 | ridx - register index. */ | |
135 | ||
136 | typedef enum | |
137 | { | |
138 | dummy, cst4, disps9, | |
139 | i3, i4, i5, i8, i12, i16, i32, | |
140 | d5, d9, d17, d25, d33, | |
141 | abs16, abs32, | |
142 | rbase, rbase_cst4, | |
143 | rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32, | |
144 | rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22, | |
145 | regr, regr8, copregr,copregr8,copsregr, | |
146 | /* Not an operand. */ | |
147 | nulloperand, | |
148 | /* Maximum supported operand. */ | |
149 | MAX_OPRD | |
150 | } | |
151 | operand_type; | |
152 | ||
153 | /* CRX instruction types. */ | |
154 | ||
155 | #define ARITH_INS 1 | |
156 | #define LD_STOR_INS 2 | |
157 | #define BRANCH_INS 3 | |
158 | #define ARITH_BYTE_INS 4 | |
159 | #define CMPBR_INS 5 | |
160 | #define SHIFT_INS 6 | |
161 | #define BRANCH_NEQ_INS 7 | |
162 | #define LD_STOR_INS_INC 8 | |
163 | #define STOR_IMM_INS 9 | |
164 | #define CSTBIT_INS 10 | |
165 | #define SYS_INS 11 | |
166 | #define JMP_INS 12 | |
167 | #define MUL_INS 13 | |
168 | #define DIV_INS 14 | |
169 | #define COP_BRANCH_INS 15 | |
170 | #define COP_REG_INS 16 | |
48c9f030 NC |
171 | #define COPS_REG_INS 17 |
172 | #define DCR_BRANCH_INS 18 | |
173 | #define MMC_INS 19 | |
174 | #define MMU_INS 20 | |
1fe1f39c NC |
175 | |
176 | /* Maximum value supported for instruction types. */ | |
177 | #define CRX_INS_MAX (1 << 5) | |
178 | /* Mask to record an instruction type. */ | |
179 | #define CRX_INS_MASK (CRX_INS_MAX - 1) | |
180 | /* Return instruction type, given instruction's attributes. */ | |
181 | #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) | |
182 | ||
183 | /* Indicates whether this instruction has a register list as parameter. */ | |
184 | #define REG_LIST CRX_INS_MAX | |
185 | /* The operands in binary and assembly are placed in reverse order. | |
186 | load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ | |
187 | #define REVERSE_MATCH (REG_LIST << 1) | |
188 | ||
189 | /* Kind of displacement map used DISPU[BWD]4. */ | |
190 | #define DISPUB4 (REVERSE_MATCH << 1) | |
191 | #define DISPUW4 (DISPUB4 << 1) | |
192 | #define DISPUD4 (DISPUW4 << 1) | |
193 | #define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4) | |
194 | ||
195 | /* Printing formats, where the instruction prefix isn't consecutive. */ | |
196 | #define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */ | |
197 | #define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */ | |
198 | #define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */ | |
199 | #define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */ | |
200 | #define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */ | |
201 | #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) | |
202 | ||
203 | #define RELAXABLE (FMT_5 << 1) | |
204 | ||
205 | /* Maximum operands per instruction. */ | |
206 | #define MAX_OPERANDS 5 | |
207 | /* Maximum words per instruction. */ | |
208 | #define MAX_WORDS 3 | |
209 | /* Maximum register name length. */ | |
210 | #define MAX_REGNAME_LEN 10 | |
211 | /* Maximum instruction length. */ | |
212 | #define MAX_INST_LEN 256 | |
213 | ||
214 | /* Single operand description. */ | |
215 | ||
216 | typedef struct | |
217 | { | |
218 | /* Operand type. */ | |
219 | operand_type op_type; | |
220 | /* Operand location within the opcode. */ | |
221 | unsigned int shift; | |
222 | } | |
223 | operand_desc; | |
224 | ||
225 | /* Instruction data structure used in instruction table. */ | |
226 | ||
227 | typedef struct | |
228 | { | |
229 | /* Name. */ | |
230 | const char *mnemonic; | |
231 | /* Size (in words). */ | |
232 | unsigned int size; | |
233 | /* Constant prefix (matched by the disassembler). */ | |
234 | unsigned long match; | |
235 | /* Match size (in bits). */ | |
236 | int match_bits; | |
237 | /* Attributes. */ | |
238 | unsigned int flags; | |
239 | /* Operands (always last, so unreferenced operands are initialized). */ | |
240 | operand_desc operands[MAX_OPERANDS]; | |
241 | } | |
242 | inst; | |
243 | ||
244 | /* Data structure for a single instruction's arguments (Operands). */ | |
245 | ||
246 | typedef struct | |
247 | { | |
248 | /* Register or base register. */ | |
249 | reg r; | |
250 | /* Index register. */ | |
251 | reg i_r; | |
252 | /* Coprocessor register. */ | |
253 | copreg cr; | |
254 | /* Constant/immediate/absolute value. */ | |
255 | unsigned long int constant; | |
256 | /* Scaled index mode. */ | |
257 | unsigned int scale; | |
258 | /* Argument type. */ | |
259 | argtype type; | |
260 | /* Size of the argument (in bits) required to represent. */ | |
261 | int size; | |
262 | /* Indicates whether a constant is positive or negative. */ | |
263 | int signflag; | |
264 | } | |
265 | argument; | |
266 | ||
267 | /* Internal structure to hold the various entities | |
268 | corresponding to the current assembling instruction. */ | |
269 | ||
270 | typedef struct | |
271 | { | |
272 | /* Number of arguments. */ | |
273 | int nargs; | |
274 | /* The argument data structure for storing args (operands). */ | |
275 | argument arg[MAX_OPERANDS]; | |
276 | /* The following fields are required only by CRX-assembler. */ | |
277 | #ifdef TC_CRX | |
278 | /* Expression used for setting the fixups (if any). */ | |
279 | expressionS exp; | |
280 | bfd_reloc_code_real_type rtype; | |
281 | #endif /* TC_CRX */ | |
282 | /* Instruction size (in bytes). */ | |
283 | int size; | |
284 | } | |
285 | ins; | |
286 | ||
287 | /* Structure to hold information about predefined operands. */ | |
288 | ||
289 | typedef struct | |
290 | { | |
291 | /* Size (in bits). */ | |
292 | unsigned int bit_size; | |
293 | /* Argument type. */ | |
294 | argtype arg_type; | |
295 | } | |
296 | operand_entry; | |
297 | ||
298 | /* Structure to hold trap handler information. */ | |
299 | ||
300 | typedef struct | |
301 | { | |
302 | /* Trap name. */ | |
303 | char *name; | |
304 | /* Index in dispatch table. */ | |
305 | unsigned int entry; | |
306 | } | |
307 | trap_entry; | |
308 | ||
309 | /* Structure to hold information about predefined registers. */ | |
310 | ||
311 | typedef struct | |
312 | { | |
313 | /* Name (string representation). */ | |
314 | char *name; | |
315 | /* Value (enum representation). */ | |
316 | union | |
317 | { | |
318 | /* Register. */ | |
319 | reg reg_val; | |
320 | /* Coprocessor register. */ | |
321 | copreg copreg_val; | |
322 | } value; | |
323 | /* Register image. */ | |
324 | int image; | |
325 | /* Register type. */ | |
326 | reg_type type; | |
327 | } | |
328 | reg_entry; | |
329 | ||
330 | /* Structure to hold a cst4 operand mapping. */ | |
331 | ||
332 | typedef struct | |
333 | { | |
334 | /* The binary value which is written to the object file. */ | |
335 | int binary; | |
336 | /* The value which is mapped. */ | |
337 | int value; | |
338 | } | |
339 | cst4_entry; | |
340 | ||
341 | /* CRX opcode table. */ | |
342 | extern const inst crx_instruction[]; | |
343 | extern const int crx_num_opcodes; | |
344 | #define NUMOPCODES crx_num_opcodes | |
345 | ||
346 | /* CRX operands table. */ | |
347 | extern const operand_entry crx_optab[]; | |
348 | ||
349 | /* CRX registers table. */ | |
350 | extern const reg_entry crx_regtab[]; | |
351 | extern const int crx_num_regs; | |
352 | #define NUMREGS crx_num_regs | |
353 | ||
354 | /* CRX coprocessor registers table. */ | |
355 | extern const reg_entry crx_copregtab[]; | |
356 | extern const int crx_num_copregs; | |
357 | #define NUMCOPREGS crx_num_copregs | |
358 | ||
359 | /* CRX trap/interrupt table. */ | |
360 | extern const trap_entry crx_traps[]; | |
361 | extern const int crx_num_traps; | |
362 | #define NUMTRAPS crx_num_traps | |
363 | ||
364 | /* cst4 operand mapping. */ | |
365 | extern const cst4_entry cst4_map[]; | |
366 | extern const int cst4_maps; | |
367 | ||
368 | /* Current instruction we're assembling. */ | |
369 | extern const inst *instruction; | |
370 | ||
371 | /* A macro for representing the instruction "constant" opcode, that is, | |
372 | the FIXED part of the instruction. The "constant" opcode is represented | |
373 | as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) | |
374 | over that range. */ | |
375 | #define BIN(OPC,SHIFT) (OPC << SHIFT) | |
376 | ||
377 | /* Is the current instruction type is TYPE ? */ | |
378 | #define IS_INSN_TYPE(TYPE) \ | |
379 | (CRX_INS_TYPE(instruction->flags) == TYPE) | |
380 | ||
381 | /* Is the current instruction mnemonic is MNEMONIC ? */ | |
382 | #define IS_INSN_MNEMONIC(MNEMONIC) \ | |
383 | (strcmp(instruction->mnemonic,MNEMONIC) == 0) | |
384 | ||
385 | /* Does the current instruction has register list ? */ | |
386 | #define INST_HAS_REG_LIST \ | |
387 | (instruction->flags & REG_LIST) | |
388 | ||
389 | /* Long long type handling. */ | |
390 | /* Replace all appearances of 'long long int' with LONGLONG. */ | |
391 | typedef long long int LONGLONG; | |
392 | typedef unsigned long long ULONGLONG; | |
393 | /* A mask for the upper 31 bits of a 64 bits type. */ | |
394 | #define UPPER31_MASK 0xFFFFFFFE00000000LL | |
395 | ||
396 | #endif /* _CRX_H_ */ |