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0b1cf022 | 1 | /* opcode/i386.h -- Intel 80386 opcode macros |
4f1d9bd8 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
e4e42b45 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4f1d9bd8 | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
543613e9 | 6 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
252b5132 | 7 | |
543613e9 NC |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
e4e42b45 | 10 | the Free Software Foundation; either version 3 of the License, or |
543613e9 | 11 | (at your option) any later version. |
252b5132 | 12 | |
543613e9 NC |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
252b5132 | 17 | |
543613e9 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
e4e42b45 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
252b5132 | 22 | |
d0b47220 AM |
23 | /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
24 | ix86 Unix assemblers, generate floating point instructions with | |
25 | reversed source and destination registers in certain cases. | |
26 | Unfortunately, gcc and possibly many other programs use this | |
27 | reversed syntax, so we're stuck with it. | |
252b5132 | 28 | |
7f3f1ea2 AM |
29 | eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
30 | `fsub %st,%st(3)' results in st(3) = st - st(3), rather than | |
31 | the expected st(3) = st(3) - st | |
252b5132 RH |
32 | |
33 | This happens with all the non-commutative arithmetic floating point | |
34 | operations with two register operands, where the source register is | |
d796c0ad | 35 | %st, and destination register is %st(i). |
7f3f1ea2 AM |
36 | |
37 | The affected opcode map is dceX, dcfX, deeX, defX. */ | |
252b5132 | 38 | |
35669430 DE |
39 | #ifndef OPCODE_I386_H |
40 | #define OPCODE_I386_H | |
41 | ||
d0b47220 | 42 | #ifndef SYSV386_COMPAT |
252b5132 | 43 | /* Set non-zero for broken, compatible instructions. Set to zero for |
d0b47220 | 44 | non-broken opcodes at your peril. gcc generates SystemV/386 |
252b5132 | 45 | compatible instructions. */ |
d0b47220 AM |
46 | #define SYSV386_COMPAT 1 |
47 | #endif | |
48 | #ifndef OLDGCC_COMPAT | |
49 | /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could | |
50 | generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands | |
51 | reversed. */ | |
52 | #define OLDGCC_COMPAT SYSV386_COMPAT | |
252b5132 | 53 | #endif |
252b5132 | 54 | |
252b5132 | 55 | #define MOV_AX_DISP32 0xa0 |
252b5132 | 56 | #define POP_SEG_SHORT 0x07 |
252b5132 | 57 | #define JUMP_PC_RELATIVE 0xeb |
543613e9 | 58 | #define INT_OPCODE 0xcd |
252b5132 | 59 | #define INT3_OPCODE 0xcc |
0b1cf022 L |
60 | /* The opcode for the fwait instruction, which disassembler treats as a |
61 | prefix when it can. */ | |
252b5132 | 62 | #define FWAIT_OPCODE 0x9b |
fedc618e DE |
63 | |
64 | /* Instruction prefixes. | |
65 | NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as | |
66 | part of the opcode. Other prefixes may still appear between them | |
67 | and the 0x0f part of the opcode. */ | |
252b5132 | 68 | #define ADDR_PREFIX_OPCODE 0x67 |
252b5132 | 69 | #define DATA_PREFIX_OPCODE 0x66 |
252b5132 | 70 | #define LOCK_PREFIX_OPCODE 0xf0 |
252b5132 | 71 | #define CS_PREFIX_OPCODE 0x2e |
252b5132 | 72 | #define DS_PREFIX_OPCODE 0x3e |
252b5132 | 73 | #define ES_PREFIX_OPCODE 0x26 |
252b5132 | 74 | #define FS_PREFIX_OPCODE 0x64 |
252b5132 | 75 | #define GS_PREFIX_OPCODE 0x65 |
252b5132 | 76 | #define SS_PREFIX_OPCODE 0x36 |
252b5132 RH |
77 | #define REPNE_PREFIX_OPCODE 0xf2 |
78 | #define REPE_PREFIX_OPCODE 0xf3 | |
050dfa73 | 79 | |
0b1cf022 L |
80 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f |
81 | #define NOP_OPCODE (char) 0x90 | |
050dfa73 | 82 | |
0b1cf022 | 83 | /* register numbers */ |
35669430 DE |
84 | #define EAX_REG_NUM 0 |
85 | #define ECX_REG_NUM 1 | |
86 | #define EDX_REG_NUM 2 | |
87 | #define EBX_REG_NUM 3 | |
0b1cf022 | 88 | #define ESP_REG_NUM 4 |
35669430 DE |
89 | #define EBP_REG_NUM 5 |
90 | #define ESI_REG_NUM 6 | |
91 | #define EDI_REG_NUM 7 | |
050dfa73 | 92 | |
0b1cf022 L |
93 | /* modrm_byte.regmem for twobyte escape */ |
94 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM | |
95 | /* index_base_byte.index for no index register addressing */ | |
96 | #define NO_INDEX_REGISTER ESP_REG_NUM | |
97 | /* index_base_byte.base for no base register addressing */ | |
98 | #define NO_BASE_REGISTER EBP_REG_NUM | |
99 | #define NO_BASE_REGISTER_16 6 | |
0f10071e | 100 | |
0b1cf022 L |
101 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ |
102 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ | |
103 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) | |
252b5132 | 104 | |
35669430 DE |
105 | /* Extract fields from the mod/rm byte. */ |
106 | #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) | |
107 | #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) | |
108 | #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) | |
109 | ||
110 | /* Extract fields from the sib byte. */ | |
111 | #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) | |
112 | #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) | |
113 | #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) | |
114 | ||
0b1cf022 L |
115 | /* x86-64 extension prefix. */ |
116 | #define REX_OPCODE 0x40 | |
252b5132 | 117 | |
35669430 DE |
118 | /* Non-zero if OPCODE is the rex prefix. */ |
119 | #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) | |
120 | ||
0b1cf022 | 121 | /* Indicates 64 bit operand size. */ |
161a04f6 | 122 | #define REX_W 8 |
0b1cf022 | 123 | /* High extension to reg field of modrm byte. */ |
161a04f6 | 124 | #define REX_R 4 |
0b1cf022 | 125 | /* High extension to SIB index field. */ |
161a04f6 | 126 | #define REX_X 2 |
0b1cf022 | 127 | /* High extension to base field of modrm or SIB, or reg field of opcode. */ |
161a04f6 | 128 | #define REX_B 1 |
252b5132 | 129 | |
0b1cf022 | 130 | /* max operands per insn */ |
c0f3af97 | 131 | #define MAX_OPERANDS 5 |
252b5132 | 132 | |
0b1cf022 L |
133 | /* max immediates per insn (lcall, ljmp, insertq, extrq) */ |
134 | #define MAX_IMMEDIATE_OPERANDS 2 | |
5f47d35b | 135 | |
0b1cf022 L |
136 | /* max memory refs per insn (string ops) */ |
137 | #define MAX_MEMORY_OPERANDS 2 | |
252b5132 | 138 | |
0b1cf022 | 139 | /* max size of insn mnemonics. */ |
c0f3af97 | 140 | #define MAX_MNEM_SIZE 20 |
252b5132 | 141 | |
0b1cf022 L |
142 | /* max size of register name in insn mnemonics. */ |
143 | #define MAX_REG_NAME_SIZE 8 | |
35669430 DE |
144 | |
145 | #endif /* OPCODE_I386_H */ |