projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Update the address and phone number of the FSF organization
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
252b5132 1/* opcode/i386.h -- Intel 80386 opcode table
4f1d9bd8 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c3aa17e9 3 2000, 2001, 2002, 2003, 2004, 2005
4f1d9bd8 4 Free Software Foundation, Inc.
252b5132 5
543613e9 6 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
252b5132 7
543613e9
NC		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
252b5132 12
543613e9
NC		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
252b5132 17
543613e9
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
e172dbf8 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
d0b47220
AM		 22/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
23 ix86 Unix assemblers, generate floating point instructions with
24 reversed source and destination registers in certain cases.
25 Unfortunately, gcc and possibly many other programs use this
26 reversed syntax, so we're stuck with it.
252b5132 27
7f3f1ea2
AM		 28 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
29 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
30 the expected st(3) = st(3) - st
252b5132
RH		 31
32 This happens with all the non-commutative arithmetic floating point
33 operations with two register operands, where the source register is
7f3f1ea2
AM		 34 %st, and destination register is %st(i). See FloatDR below.
35
36 The affected opcode map is dceX, dcfX, deeX, defX. */
252b5132 37
d0b47220 38#ifndef SYSV386_COMPAT
252b5132 39/* Set non-zero for broken, compatible instructions. Set to zero for
d0b47220 40 non-broken opcodes at your peril. gcc generates SystemV/386
252b5132 41 compatible instructions. */
d0b47220
AM		 42#define SYSV386_COMPAT 1
43#endif
44#ifndef OLDGCC_COMPAT
45/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
46 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
47 reversed. */
48#define OLDGCC_COMPAT SYSV386_COMPAT
252b5132 49#endif
252b5132 50
543613e9
NC		 51static const template i386_optab[] =
52{
252b5132
RH		 53
54#define X None
c0d8940f
JH		 55#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
56#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
57#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
58#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf)
59#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
60#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf)
61#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf)
62#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf)
63#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
64#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
65#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
85a33fe2 66#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
c0d8940f 67#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
c0d8940f
JH		 68#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
69#define bwlq_Suf (No_sSuf|No_xSuf)
9306ca4a
JB		 70#define FP (NoSuf)
71#define l_FP (l_Suf)
72#define q_FP (q_Suf|NoRex64)
73#define x_FP (x_Suf|FloatMF)
74#define sl_FP (sl_Suf|FloatMF)
d0b47220 75#if SYSV386_COMPAT
7f3f1ea2
AM		 76/* Someone forgot that the FloatR bit reverses the operation when not
77 equal to the FloatD bit. ie. Changing only FloatD results in the
78 destination being swapped *and* the direction being reversed. */
252b5132
RH		 79#define FloatDR FloatD
80#else
81#define FloatDR (FloatD|FloatR)
82#endif
83
d0b47220 84/* Move instructions. */
252b5132 85#define MOV_AX_DISP32 0xa0
c0d8940f
JH		 86/* In the 64bit mode the short form mov immediate is redefined to have
87 64bit displacement value. */
37edbb65 88{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
c0d8940f
JH		 89{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
90/* In the 64bit mode the short form mov immediate is redefined to have
91 64bit displacement value. */
92{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } },
93{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } },
94{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
e413e4e9 95/* The segment register moves accept WordReg so that a segment register
252b5132
RH		 96 can be copied to a 32 bit register, and vice versa, without using a
97 size prefix. When moving to a 32 bit register, the upper 16 bits
98 are set to an implementation defined value (on the Pentium Pro,
99 the implementation defined value is zero). */
9306ca4a 100{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } },
4cc91dba 101{ "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } },
9306ca4a 102{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } },
4cc91dba
L		 103{ "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } },
104{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } },
105{ "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } },
106{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } },
107{ "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } },
c0d8940f
JH		 108/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
109 mode they are 64bit.*/
110{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} },
111{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
112{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
113{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
37edbb65 114{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
c0d8940f
JH		 115{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
116{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
252b5132 117
d0b47220 118/* Move with sign extend. */
252b5132
RH		 119/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
120 conflict with the "movs" string move instruction. */
e413e4e9
AM		 121{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
122{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
c0d8940f
JH		 123{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} },
124{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
125{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
126{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
9306ca4a 127/* Intel Syntax next 3 insns */
e413e4e9 128{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
9306ca4a 129{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} },
c0d8940f 130{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
252b5132 131
bcb9eebe
L		 132/* Move with zero extend. We can't remove "movzb" since existing
133 assembly codes may use it. */
134{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
9306ca4a
JB		 135/* "movzbl" & "movzbw" should not be unified into "movzb" for
136 consistency with the sign extending moves above. */
137{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
138{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
e413e4e9 139{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
9306ca4a 140/* These instructions are not particulary useful, since the zero extend
c0d8940f
JH		 141 32->64 is implicit, but we can encode them. */
142{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
143{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
9306ca4a
JB		 144/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
145 since the zero extend 32->64 is implicit, but we can encode them). */
e413e4e9 146{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
9306ca4a 147{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} },
252b5132 148
d0b47220 149/* Push instructions. */
c0d8940f
JH		 150{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
151{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
152{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
153{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
543613e9 154{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
c0d8940f
JH		 155{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
156/* In 64bit mode, the operand size is implicitly 64bit. */
543613e9
NC		 157{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
158{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
159{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
160{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
161{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
c0d8940f 162
e2914f48 163{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 164
d0b47220 165/* Pop instructions. */
c0d8940f
JH		 166{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
167{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
252b5132 168#define POP_SEG_SHORT 0x07
c0d8940f
JH		 169{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
170{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
171/* In 64bit mode, the operand size is implicitly 64bit. */
543613e9
NC		 172{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
173{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
85a33fe2 174{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
c0d8940f
JH		 175
176{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 177
d0b47220 178/* Exchange instructions.
c0d8940f
JH		 179 xchg commutes: we allow both operand orders.
180
543613e9
NC		 181 In the 64bit code, xchg eax, eax is reused for new nop instruction. */
182#if 0 /* While the two entries that are disabled generate shorter code
183 for xchg eax, reg (on x86_64), the special case xchg eax, eax
184 does not get handled correctly - it degenerates into nop, but
185 that way the side effect of zero-extending eax to rax is lost. */
85a33fe2
JH		 186{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } },
187{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } },
543613e9
NC		 188#else
189{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
190{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
191{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } },
192{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } },
193#endif
c0d8940f
JH		 194{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
195{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
252b5132 196
d0b47220 197/* In/out from ports. */
543613e9 198/* XXX should reject %rax */
85a33fe2
JH		 199{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } },
200{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
201{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
202{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
203{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } },
204{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
205{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
206{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
252b5132 207
d0b47220 208/* Load effective address. */
c0d8940f 209{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } },
252b5132 210
d0b47220 211/* Load segment registers from memory. */
543613e9
NC		 212{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
213{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
214{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
215{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
216{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
252b5132 217
d0b47220 218/* Flags register instructions. */
e413e4e9
AM		 219{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
220{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} },
221{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
222{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
223{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
37edbb65
JB		 224{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} },
225{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} },
543613e9 226{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
85a33fe2 227{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
543613e9 228{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
85a33fe2 229{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
e413e4e9
AM		 230{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
231{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
232{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} },
252b5132 233
d0b47220 234/* Arithmetic. */
c0d8940f
JH		 235{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
236{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
237{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
238{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
239
240{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} },
241{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
242
243{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
244{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
245{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
246{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
247
248{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} },
249{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
250
251{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
252{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
253{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
254{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
255
256{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
257{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
258{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
259{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
260
261{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
262{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
263{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
264{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
265
266{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
267{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
268{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
269{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
270
271{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
272{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
273{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
274{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
275
276{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
277{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
278{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
279{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
e413e4e9
AM		 280
281/* clr with 1 operand is really xor with 2 operands. */
c0d8940f 282{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
e413e4e9 283
c0d8940f
JH		 284{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
285{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
286{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
287{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
e413e4e9 288
c0d8940f
JH		 289{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
290{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
e413e4e9 291
543613e9
NC		 292{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} },
293{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} },
294{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} },
295{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} },
296{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} },
297{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8S, 0, 0} },
298{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} },
299{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8S, 0, 0} },
252b5132 300
d0b47220
AM		 301/* Conversion insns. */
302/* Intel naming */
e413e4e9 303{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
c0d8940f 304{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
e413e4e9
AM		 305{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
306{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
307{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
c0d8940f 308{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
d0b47220 309/* AT&T naming */
e413e4e9 310{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
c0d8940f 311{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
e413e4e9
AM		 312{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
313{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
314{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
c0d8940f 315{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
252b5132
RH		 316
317/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
318 expanding 64-bit multiplies, and *cannot* be selected to accomplish
319 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
320 These multiplies can only be selected with single operand forms. */
c0d8940f
JH		 321{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
322{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
323{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
324{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
325{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
252b5132
RH		 326/* imul with 2 operands mimics imul with 3 by putting the register in
327 both i.rm.reg & i.rm.regmem fields. regKludge enables this
328 transformation. */
c0d8940f
JH		 329{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
330{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
331
332{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
333{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
334{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
335{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
336
337{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
338{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
339{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
340{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
341
342{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
343{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
344{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
345{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
346
347{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
348{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
349{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
350{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
351
352{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
353{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
354{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
355{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
356
357{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
358{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
359{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
360{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
361
362{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
363{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
364{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
365{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
366
367{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
368{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
369{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
370{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
371
372{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
373{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
374{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
375{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
376
377{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
378{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
379{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
380
381{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
382{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
383{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
252b5132 384
d0b47220 385/* Control transfer instructions. */
543613e9
NC		 386{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
387{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} },
85a33fe2 388{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
543613e9 389{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} },
252b5132 390/* Intel Syntax */
543613e9 391{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
3138f287 392/* Intel Syntax */
9306ca4a 393{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} },
543613e9
NC		 394{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
395{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} },
252b5132
RH		 396
397#define JUMP_PC_RELATIVE 0xeb
543613e9 398{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} },
85a33fe2 399{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
543613e9
NC		 400{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} },
401/* Intel Syntax. */
c0d8940f 402{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
543613e9 403/* Intel Syntax. */
9306ca4a 404{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
543613e9
NC		 405{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
406{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
407
408{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
409{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} },
410{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
411{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
c0d8940f
JH		 412{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
413{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
543613e9
NC		 414{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
415{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} },
416{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} },
417{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} },
252b5132 418
d0b47220 419/* Conditional jumps. */
e413e4e9
AM		 420{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
421{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} },
422{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
423{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
424{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
425{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
426{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
427{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
428{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
429{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
430{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
431{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
432{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
433{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
434{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
435{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
436{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} },
437{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} },
438{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
439{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
440{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
441{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
442{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
443{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
444{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
445{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
446{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
447{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
448{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
449{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
252b5132
RH		 450
451/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
85a33fe2
JH		 452{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
453{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
454{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
455{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
252b5132
RH		 456
457/* The loop instructions also use the address size prefix to select
458 %cx rather than %ecx for the loop count, so the `w' form of these
459 instructions emit an address size prefix rather than a data size
460 prefix. */
85a33fe2
JH		 461{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
462{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
463{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
464{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
465{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
466{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
467{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
468{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
469{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
470{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
252b5132 471
d0b47220 472/* Set byte on flag instructions. */
e413e4e9
AM		 473{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
474{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
475{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
476{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
477{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
478{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
479{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
480{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
481{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
482{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
483{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
484{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
485{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
486{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
487{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
488{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
489{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
490{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
491{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
492{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
493{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
494{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
495{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
496{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
497{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
498{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
499{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
500{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
501{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
502{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
252b5132 503
d0b47220 504/* String manipulation. */
c0d8940f
JH		 505{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
506{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
507{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
508{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
85a33fe2
JH		 509{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
510{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
511{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
512{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
c0d8940f
JH		 513{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
514{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
515{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
516{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
517{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
518{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
519{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
520{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
521{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
522{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
523{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
524{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
525{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
526{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
527{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
528{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
529{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
530{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
531{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
532{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
533{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
534{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
e413e4e9
AM		 535{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} },
536{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} },
252b5132 537
d0b47220 538/* Bit manipulation. */
c0d8940f
JH		 539{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
540{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
541{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
542{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
543{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
544{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
545{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
546{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
547{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
548{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
252b5132 549
d0b47220 550/* Interrupts & op. sys insns. */
252b5132 551/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
d0b47220 552 int 3 insn. */
543613e9 553#define INT_OPCODE 0xcd
252b5132 554#define INT3_OPCODE 0xcc
e413e4e9
AM		 555{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
556{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
543613e9 557{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} },
c0d8940f 558{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
d0b47220 559/* i386sl, i486sl, later 486, and Pentium. */
e413e4e9 560{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
252b5132 561
543613e9 562{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} },
252b5132 563
e413e4e9 564{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
d0b47220 565/* nop is actually 'xchgl %eax, %eax'. */
e413e4e9 566{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
252b5132 567
d0b47220 568/* Protection control. */
543613e9 569{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
c0d8940f 570{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
543613e9
NC		 571{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
572{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
573{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
574{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
e413e4e9
AM		 575{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
576{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
c0d8940f 577{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
e413e4e9
AM		 578{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
579
543613e9
NC		 580{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
581{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
582{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
37edbb65 583{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
e5470cdc
AM		 584{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
585{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
586{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
587{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
588{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
589{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
e413e4e9
AM		 590
591{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
592{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
252b5132 593
d0b47220 594/* Floating point instructions. */
252b5132
RH		 595
596/* load */
e413e4e9 597{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
9306ca4a
JB		 598{"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
599{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
252b5132 600/* Intel Syntax */
e413e4e9 601{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
9306ca4a
JB		 602{"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
603{"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 604{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
605{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
9ae09ff9 606{"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 607
608/* store (no pop) */
e413e4e9 609{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
9306ca4a
JB		 610{"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
611{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
612{"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 613
614/* store (with pop) */
e413e4e9 615{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
9306ca4a
JB		 616{"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
617{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
252b5132 618/* Intel Syntax */
e413e4e9 619{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
9306ca4a
JB		 620{"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
621{"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 622{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
623{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
9ae09ff9 624{"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 625
626/* exchange %st<n> with %st0 */
e413e4e9
AM		 627{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
628/* alias for fxch %st(1) */
629{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 630
631/* comparison (without pop) */
e413e4e9
AM		 632{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
633/* alias for fcom %st(1) */
634{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
9306ca4a
JB		 635{"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
636{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
637{"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 638
639/* comparison (with pop) */
e413e4e9
AM		 640{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
641/* alias for fcomp %st(1) */
642{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
9306ca4a
JB		 643{"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
644{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
645{"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
e413e4e9 646{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 647
648/* unordered comparison (with pop) */
e413e4e9
AM		 649{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
650/* alias for fucom %st(1) */
651{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
652{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
653/* alias for fucomp %st(1) */
654{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
655{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
252b5132 656
e413e4e9
AM		 657{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
658{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 659
660/* load constants into %st0 */
e413e4e9
AM		 661{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
662{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
663{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
664{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
665{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
666{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
667{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
252b5132 668
543613e9 669/* Arithmetic. */
252b5132
RH		 670
671/* add */
e413e4e9
AM		 672{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
673/* alias for fadd %st(i), %st */
674{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 675#if SYSV386_COMPAT
e413e4e9
AM		 676/* alias for faddp */
677{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 678#endif
9306ca4a
JB		 679{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
680{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 681
e413e4e9
AM		 682{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
683{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
684/* alias for faddp %st, %st(1) */
685{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
686{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 687
688/* subtract */
e413e4e9
AM		 689{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
690{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 691#if SYSV386_COMPAT
e413e4e9
AM		 692/* alias for fsubp */
693{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 694#endif
9306ca4a
JB		 695{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
696{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 697
d0b47220 698#if SYSV386_COMPAT
e413e4e9
AM		 699{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
700{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
701{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
d0b47220 702#if OLDGCC_COMPAT
e413e4e9 703{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 704#endif
252b5132 705#else
e413e4e9
AM		 706{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
707{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
708{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 709#endif
710
711/* subtract reverse */
e413e4e9
AM		 712{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
713{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 714#if SYSV386_COMPAT
e413e4e9
AM		 715/* alias for fsubrp */
716{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 717#endif
9306ca4a
JB		 718{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
719{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 720
d0b47220 721#if SYSV386_COMPAT
e413e4e9
AM		 722{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
723{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
724{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
d0b47220 725#if OLDGCC_COMPAT
e413e4e9 726{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 727#endif
252b5132 728#else
e413e4e9
AM		 729{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
730{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
731{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 732#endif
733
734/* multiply */
e413e4e9
AM		 735{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
736{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 737#if SYSV386_COMPAT
e413e4e9
AM		 738/* alias for fmulp */
739{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 740#endif
9306ca4a
JB		 741{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
742{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 743
e413e4e9
AM		 744{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
745{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
746{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
747{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 748
749/* divide */
e413e4e9
AM		 750{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
751{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 752#if SYSV386_COMPAT
e413e4e9
AM		 753/* alias for fdivp */
754{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 755#endif
9306ca4a
JB		 756{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
757{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 758
d0b47220 759#if SYSV386_COMPAT
e413e4e9
AM		 760{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
761{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
762{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
d0b47220 763#if OLDGCC_COMPAT
e413e4e9 764{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 765#endif
252b5132 766#else
e413e4e9
AM		 767{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
768{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
769{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 770#endif
771
772/* divide reverse */
e413e4e9
AM		 773{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
774{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 775#if SYSV386_COMPAT
e413e4e9
AM		 776/* alias for fdivrp */
777{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 778#endif
9306ca4a
JB		 779{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
780{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 781
d0b47220 782#if SYSV386_COMPAT
e413e4e9
AM		 783{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
784{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
785{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
d0b47220 786#if OLDGCC_COMPAT
e413e4e9 787{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 788#endif
252b5132 789#else
e413e4e9
AM		 790{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
791{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
792{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 793#endif
794
e413e4e9
AM		 795{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
796{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
797{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
798{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
799{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
800{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
801{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
802{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
803{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
804{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
805{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
806{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
807{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
808{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
809{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
810{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
811{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
812{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 813
814/* processor control */
e413e4e9
AM		 815{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
816{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
9ae09ff9
JB		 817{"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
818{"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
819{"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
9306ca4a
JB		 820/* XXX should reject %al, %eax, and %rax */
821{"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} },
9ae09ff9 822{"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
e413e4e9 823{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
9306ca4a
JB		 824/* XXX should reject %al, %eax, and %rax */
825{"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} },
9ae09ff9 826{"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
e413e4e9
AM		 827{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
828{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
829{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
d0b47220 830/* Short forms of fldenv, fstenv use data size prefix. */
9306ca4a
JB		 831{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
832{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} },
833{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
834{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
835{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} },
836{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
e413e4e9
AM		 837
838{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 839/* P6:free st(i), pop st */
e413e4e9
AM		 840{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
841{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
252b5132 842#define FWAIT_OPCODE 0x9b
e413e4e9 843{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
252b5132 844
d0b47220
AM		 845/* Opcode prefixes; we allow them as separate insns too. */
846
252b5132 847#define ADDR_PREFIX_OPCODE 0x67
543613e9
NC		 848{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
849{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
850{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
851{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 852#define DATA_PREFIX_OPCODE 0x66
543613e9
NC		 853{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
854{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
855{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
856{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 857#define LOCK_PREFIX_OPCODE 0xf0
e413e4e9
AM		 858{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
859{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 860#define CS_PREFIX_OPCODE 0x2e
9a45f1c2 861{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 862#define DS_PREFIX_OPCODE 0x3e
9a45f1c2 863{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 864#define ES_PREFIX_OPCODE 0x26
543613e9 865{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 866#define FS_PREFIX_OPCODE 0x64
e413e4e9 867{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 868#define GS_PREFIX_OPCODE 0x65
e413e4e9 869{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 870#define SS_PREFIX_OPCODE 0x36
543613e9 871{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132
RH		 872#define REPNE_PREFIX_OPCODE 0xf2
873#define REPE_PREFIX_OPCODE 0xf3
e413e4e9
AM		 874{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
875{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
876{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
877{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
878{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
e44823cf
JB		 879{"ht", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
880{"hnt", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
c0d8940f
JH		 881{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
882{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
883{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
884{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
885{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
886{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
887{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
888{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
889{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
890{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
891{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
892{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
893{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
894{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
895{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
896{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 897
d0b47220 898/* 486 extensions. */
252b5132 899
c0d8940f
JH		 900{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } },
901{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
902{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
e413e4e9
AM		 903{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
904{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
9306ca4a 905{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
252b5132 906
d0b47220 907/* 586 and late 486 extensions. */
e413e4e9 908{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
252b5132 909
d0b47220 910/* Pentium extensions. */
e413e4e9
AM		 911{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
912{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
913{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
9306ca4a 914{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} },
252b5132 915
558b0a60 916/* Pentium II/Pentium Pro extensions. */
4fd61dcb
JJ		 917{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },
918{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },
37edbb65
JB		 919{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
920{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 921{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
922/* official undefined instr. */
923{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
924/* alias for ud2 */
925{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
926/* 2nd. official undefined instr. */
927{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} },
928
c0d8940f
JH		 929{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
930{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
931{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
932{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
933{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
934{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
935{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
936{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
937{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
938{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
939{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
940{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
941{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
942{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
943{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
944{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
945{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
946{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
947{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
948{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
949{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
950{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
951{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
952{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
953{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
954{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
955{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
956{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
e413e4e9
AM		 957
958{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
959{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
960{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
961{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
962{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
963{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
964{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
965{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
966{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
967{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
968{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
969{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
970
971{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
972{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
973{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
974{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
975{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
976{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
977{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
978{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
979{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
980{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
981{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
982{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
983{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
984{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 985
6f8c0c4c
JH		 986/* Pentium4 extensions. */
987
9306ca4a
JB		 988{"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } },
989{"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } },
990{"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } },
991{"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } },
992{"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } },
6f8c0c4c
JH		 993
994/* MMX/SSE2 instructions. */
252b5132 995
9306ca4a
JB		 996{"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } },
997{"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
998{"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
999{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } },
1000{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } },
85a33fe2
JH		 1001/* In the 64bit mode the short form mov immediate is redefined to have
1002 64bit displacement value. */
9306ca4a
JB		 1003{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1004{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
1005{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1006{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
c0d8940f
JH		 1007{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
1008{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } },
1009{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
4cc91dba
L		 1010/* The segment register moves accept Reg64 so that a segment register
1011 can be copied to a 64 bit register, and vice versa. */
1012{"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } },
1013{"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } },
c0d8940f
JH		 1014/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
1015 mode they are 64bit.*/
1016{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
1017{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
9306ca4a
JB		 1018/* Real MMX instructions. */
1019{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1020{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1021{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1022{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1023{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1024{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1025{"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1026{"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1027{"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1028{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1029{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1030{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1031{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a
JB		 1032{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1033{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1034{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1035{"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1036{"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1037{"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1038{"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1039{"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1040{"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1041{"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1042{"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1043{"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1044{"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1045{"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1046{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1047{"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1048{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1049{"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1050{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1051{"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1052{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1053{"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1054{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1055{"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1056{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1057{"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1058{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1059{"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1060{"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1061{"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1062{"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1063{"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1064{"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1065{"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1066{"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1067{"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1068{"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1069{"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1070{"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1071{"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1072{"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1073{"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1074{"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1075{"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1076{"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1077{"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1078{"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1079{"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1080{"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1081{"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1082{"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1083{"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1084{"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1085{"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1086{"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1087{"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1088{"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1089{"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1090{"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1091{"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1092{"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1093{"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1094{"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1095{"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
1096{"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1097{"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1098{"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1099{"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1100{"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1101{"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1102{"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1103{"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1104{"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1105{"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1106{"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1107{"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1108{"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1109{"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1110{"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1111{"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1112{"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1113{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1114{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1115{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1116{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1117{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1118{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1119{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1120{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1121{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1122{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1123{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1124{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1125{"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1126{"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1127
d0b47220 1128/* PIII Katmai New Instructions / SIMD instructions. */
c608c12e 1129
9306ca4a
JB		 1130{"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1131{"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1132{"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1133{"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1134{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1135{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1136{"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1137{"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1138{"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1139{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1140{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1141{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1142{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1143{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1144{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1145{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1146{"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1147{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1148{"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1149{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1150{"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1151{"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
1152{"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1153{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
1154{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5
JH		 1155{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1156{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
9306ca4a 1157{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5 1158{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },
9306ca4a
JB		 1159{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1160{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1161{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
5c6af06e 1162{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
9306ca4a
JB		 1163{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1164{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1165{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1166{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1167{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1168{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1169{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1170{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1171{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1172{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1173{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1174{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
85a33fe2 1175{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
9306ca4a 1176{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
5c6af06e 1177{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } },
9306ca4a
JB		 1178{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1179{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1180{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
1181{"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1182{"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1183{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1184{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1185{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1186{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1187{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1188{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1189{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1190{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
85a33fe2 1191{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
5c6af06e 1192{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
9306ca4a 1193{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
5c6af06e 1194{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1195{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1196{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1197{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1198{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1199{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1200{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1201{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1202{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
85a33fe2 1203{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
5c6af06e 1204{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1205{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e
JB		 1206{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
1207{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
1208{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
1209{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
1210{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
9306ca4a 1211{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
5c6af06e 1212{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
9306ca4a
JB		 1213{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1214{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1215{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1216{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
5c6af06e 1217{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
9306ca4a
JB		 1218{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1219{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1220{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1221{"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
1222{"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1223{"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1224{"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1225{"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1226{"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1227{"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1228
6f8c0c4c
JH		 1229/* SSE-2 instructions. */
1230
9306ca4a
JB		 1231{"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1232{"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1233{"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1234{"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1235{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1236{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1237{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1238{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1239{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1240{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1241{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1242{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1243{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1244{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1245{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1246{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1247{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1248{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1249{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1250{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1251{"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
cd47f4f1
AM		 1252/* Intel mode string compare. */
1253{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1254{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
9306ca4a
JB		 1255{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
1256{"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1257{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
76f227a5 1258{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
9306ca4a
JB		 1259{"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1260{"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1261{"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1262{"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1263{"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1264{"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1265{"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1266{"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1267{"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1268{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1269{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1270{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
85a33fe2 1271{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
9306ca4a 1272{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
cd47f4f1
AM		 1273/* Intel mode string move. */
1274{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1275{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
9306ca4a
JB		 1276{"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1277{"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
1278{"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1279{"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1280{"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1281{"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1282{"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1283{"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1284{"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1285{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1286{"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1287{"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1288{"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1289{"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1290{"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1291{"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1292{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1293{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1294{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1295{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1296{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1297{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1298{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
76f227a5 1299{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
9306ca4a
JB		 1300{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1301{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1302{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5 1303{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
9306ca4a
JB		 1304{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1305{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1306{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1307{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1308{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1309{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1310{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1311{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } },
1312{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
1313{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1314{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1315{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1316{"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1317{"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1318{"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1319{"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1320{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1321{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
6f8c0c4c 1322
ca164297
L		 1323/* Prescott New Instructions. */
1324
9306ca4a
JB		 1325{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1326{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
37edbb65 1327{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
9306ca4a
JB		 1328{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
1329{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} },
ca164297 1330{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
9306ca4a
JB		 1331{"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1332{"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1333{"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1334{"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1335{"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1336{"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} },
ca164297 1337/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
9306ca4a
JB		 1338{"monitor", 3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, Reg32} },
1339{"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1340{"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1341{"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1342{"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} },
ca164297 1343/* Need to ensure only "mwait %eax,%ecx" is accepted. */
9306ca4a 1344{"mwait", 2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, 0} },
ca164297 1345
d0b47220 1346/* AMD 3DNow! instructions. */
c608c12e 1347
9306ca4a
JB		 1348{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1349{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1350{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } },
1351{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1352{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
5c6af06e 1353{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
9306ca4a
JB		 1354{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1355{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1356{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1357{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1358{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1359{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1360{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1361{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
5c6af06e
JB		 1362{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1363{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
9306ca4a
JB		 1364{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1365{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1366{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1367{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1368{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1369{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1370{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1371{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
5c6af06e 1372{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
9306ca4a 1373{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
5c6af06e 1374{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
e413e4e9 1375
c0d8940f 1376/* AMD extensions. */
296bc568
AM		 1377{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} },
1378{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} },
1379{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} },
373ff435 1380{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} },
c0d8940f 1381
543613e9 1382/* VIA PadLock extensions. */
791fe849
MK		 1383{"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1384{"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1385{"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1386{"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1387{"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1388{"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1389{"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1390{"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1391{"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1392/* Aliases without hyphens. */
bc4bd9ab
MK		 1393{"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1394{"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1395{"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
791fe849 1396{"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
bc4bd9ab
MK		 1397{"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1398{"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
791fe849 1399/* Alias for xstore-rng. */
bc4bd9ab 1400{"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
0f10071e 1401
e413e4e9
AM		 1402/* sentinel */
1403{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
252b5132
RH		 1404};
1405#undef X
252b5132
RH		 1406#undef NoSuf
1407#undef b_Suf
1408#undef w_Suf
1409#undef l_Suf
c0d8940f 1410#undef q_Suf
eecb386c 1411#undef x_Suf
252b5132
RH		 1412#undef bw_Suf
1413#undef bl_Suf
1414#undef wl_Suf
c0d8940f 1415#undef wlq_Suf
252b5132
RH		 1416#undef sl_Suf
1417#undef bwl_Suf
c0d8940f 1418#undef bwlq_Suf
252b5132
RH		 1419#undef FP
1420#undef l_FP
9306ca4a 1421#undef q_FP
eecb386c 1422#undef x_FP
252b5132
RH		 1423#undef sl_FP
1424
543613e9 1425#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */
252b5132 1426
d0b47220 1427/* 386 register table. */
252b5132 1428
543613e9
NC		 1429static const reg_entry i386_regtab[] =
1430{
1431 /* Make %st first as we test for it. */
3e73aa7c 1432 {"st", FloatReg|FloatAcc, 0, 0},
252b5132 1433 /* 8 bit regs */
2e98d2de 1434#define REGNAM_AL 1 /* Entry in i386_regtab. */
3e73aa7c
JH		 1435 {"al", Reg8|Acc, 0, 0},
1436 {"cl", Reg8|ShiftCount, 0, 1},
1437 {"dl", Reg8, 0, 2},
1438 {"bl", Reg8, 0, 3},
1439 {"ah", Reg8, 0, 4},
1440 {"ch", Reg8, 0, 5},
1441 {"dh", Reg8, 0, 6},
1442 {"bh", Reg8, 0, 7},
c0d8940f
JH		 1443 {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */
1444 {"cxl", Reg8, RegRex64, 1},
1445 {"dxl", Reg8, RegRex64, 2},
1446 {"bxl", Reg8, RegRex64, 3},
1447 {"spl", Reg8, RegRex64, 4},
1448 {"bpl", Reg8, RegRex64, 5},
1449 {"sil", Reg8, RegRex64, 6},
1450 {"dil", Reg8, RegRex64, 7},
1451 {"r8b", Reg8, RegRex64|RegRex, 0},
1452 {"r9b", Reg8, RegRex64|RegRex, 1},
1453 {"r10b", Reg8, RegRex64|RegRex, 2},
1454 {"r11b", Reg8, RegRex64|RegRex, 3},
1455 {"r12b", Reg8, RegRex64|RegRex, 4},
1456 {"r13b", Reg8, RegRex64|RegRex, 5},
1457 {"r14b", Reg8, RegRex64|RegRex, 6},
1458 {"r15b", Reg8, RegRex64|RegRex, 7},
252b5132 1459 /* 16 bit regs */
2e98d2de 1460#define REGNAM_AX 25
3e73aa7c
JH		 1461 {"ax", Reg16|Acc, 0, 0},
1462 {"cx", Reg16, 0, 1},
1463 {"dx", Reg16|InOutPortReg, 0, 2},
1464 {"bx", Reg16|BaseIndex, 0, 3},
1465 {"sp", Reg16, 0, 4},
1466 {"bp", Reg16|BaseIndex, 0, 5},
1467 {"si", Reg16|BaseIndex, 0, 6},
1468 {"di", Reg16|BaseIndex, 0, 7},
c0d8940f
JH		 1469 {"r8w", Reg16, RegRex, 0},
1470 {"r9w", Reg16, RegRex, 1},
1471 {"r10w", Reg16, RegRex, 2},
1472 {"r11w", Reg16, RegRex, 3},
1473 {"r12w", Reg16, RegRex, 4},
1474 {"r13w", Reg16, RegRex, 5},
1475 {"r14w", Reg16, RegRex, 6},
1476 {"r15w", Reg16, RegRex, 7},
252b5132 1477 /* 32 bit regs */
2e98d2de 1478#define REGNAM_EAX 41
543613e9 1479 {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */
3e73aa7c
JH		 1480 {"ecx", Reg32|BaseIndex, 0, 1},
1481 {"edx", Reg32|BaseIndex, 0, 2},
1482 {"ebx", Reg32|BaseIndex, 0, 3},
1483 {"esp", Reg32, 0, 4},
1484 {"ebp", Reg32|BaseIndex, 0, 5},
1485 {"esi", Reg32|BaseIndex, 0, 6},
1486 {"edi", Reg32|BaseIndex, 0, 7},
c0d8940f
JH		 1487 {"r8d", Reg32|BaseIndex, RegRex, 0},
1488 {"r9d", Reg32|BaseIndex, RegRex, 1},
1489 {"r10d", Reg32|BaseIndex, RegRex, 2},
1490 {"r11d", Reg32|BaseIndex, RegRex, 3},
1491 {"r12d", Reg32|BaseIndex, RegRex, 4},
1492 {"r13d", Reg32|BaseIndex, RegRex, 5},
1493 {"r14d", Reg32|BaseIndex, RegRex, 6},
1494 {"r15d", Reg32|BaseIndex, RegRex, 7},
1495 {"rax", Reg64|BaseIndex|Acc, 0, 0},
1496 {"rcx", Reg64|BaseIndex, 0, 1},
1497 {"rdx", Reg64|BaseIndex, 0, 2},
1498 {"rbx", Reg64|BaseIndex, 0, 3},
1499 {"rsp", Reg64, 0, 4},
1500 {"rbp", Reg64|BaseIndex, 0, 5},
1501 {"rsi", Reg64|BaseIndex, 0, 6},
1502 {"rdi", Reg64|BaseIndex, 0, 7},
1503 {"r8", Reg64|BaseIndex, RegRex, 0},
1504 {"r9", Reg64|BaseIndex, RegRex, 1},
1505 {"r10", Reg64|BaseIndex, RegRex, 2},
1506 {"r11", Reg64|BaseIndex, RegRex, 3},
1507 {"r12", Reg64|BaseIndex, RegRex, 4},
1508 {"r13", Reg64|BaseIndex, RegRex, 5},
1509 {"r14", Reg64|BaseIndex, RegRex, 6},
1510 {"r15", Reg64|BaseIndex, RegRex, 7},
543613e9 1511 /* Segment registers. */
3e73aa7c
JH		 1512 {"es", SReg2, 0, 0},
1513 {"cs", SReg2, 0, 1},
1514 {"ss", SReg2, 0, 2},
1515 {"ds", SReg2, 0, 3},
1516 {"fs", SReg3, 0, 4},
1517 {"gs", SReg3, 0, 5},
543613e9 1518 /* Control registers. */
3e73aa7c
JH		 1519 {"cr0", Control, 0, 0},
1520 {"cr1", Control, 0, 1},
1521 {"cr2", Control, 0, 2},
1522 {"cr3", Control, 0, 3},
1523 {"cr4", Control, 0, 4},
1524 {"cr5", Control, 0, 5},
1525 {"cr6", Control, 0, 6},
1526 {"cr7", Control, 0, 7},
c0d8940f
JH		 1527 {"cr8", Control, RegRex, 0},
1528 {"cr9", Control, RegRex, 1},
1529 {"cr10", Control, RegRex, 2},
1530 {"cr11", Control, RegRex, 3},
1531 {"cr12", Control, RegRex, 4},
1532 {"cr13", Control, RegRex, 5},
1533 {"cr14", Control, RegRex, 6},
1534 {"cr15", Control, RegRex, 7},
543613e9 1535 /* Debug registers. */
3e73aa7c
JH		 1536 {"db0", Debug, 0, 0},
1537 {"db1", Debug, 0, 1},
1538 {"db2", Debug, 0, 2},
1539 {"db3", Debug, 0, 3},
1540 {"db4", Debug, 0, 4},
1541 {"db5", Debug, 0, 5},
1542 {"db6", Debug, 0, 6},
1543 {"db7", Debug, 0, 7},
c0d8940f
JH		 1544 {"db8", Debug, RegRex, 0},
1545 {"db9", Debug, RegRex, 1},
1546 {"db10", Debug, RegRex, 2},
1547 {"db11", Debug, RegRex, 3},
1548 {"db12", Debug, RegRex, 4},
1549 {"db13", Debug, RegRex, 5},
1550 {"db14", Debug, RegRex, 6},
1551 {"db15", Debug, RegRex, 7},
3e73aa7c
JH		 1552 {"dr0", Debug, 0, 0},
1553 {"dr1", Debug, 0, 1},
1554 {"dr2", Debug, 0, 2},
1555 {"dr3", Debug, 0, 3},
1556 {"dr4", Debug, 0, 4},
1557 {"dr5", Debug, 0, 5},
1558 {"dr6", Debug, 0, 6},
1559 {"dr7", Debug, 0, 7},
c0d8940f
JH		 1560 {"dr8", Debug, RegRex, 0},
1561 {"dr9", Debug, RegRex, 1},
1562 {"dr10", Debug, RegRex, 2},
1563 {"dr11", Debug, RegRex, 3},
1564 {"dr12", Debug, RegRex, 4},
1565 {"dr13", Debug, RegRex, 5},
1566 {"dr14", Debug, RegRex, 6},
1567 {"dr15", Debug, RegRex, 7},
543613e9 1568 /* Test registers. */
3e73aa7c
JH		 1569 {"tr0", Test, 0, 0},
1570 {"tr1", Test, 0, 1},
1571 {"tr2", Test, 0, 2},
1572 {"tr3", Test, 0, 3},
1573 {"tr4", Test, 0, 4},
1574 {"tr5", Test, 0, 5},
1575 {"tr6", Test, 0, 6},
1576 {"tr7", Test, 0, 7},
543613e9 1577 /* MMX and simd registers. */
3e73aa7c
JH		 1578 {"mm0", RegMMX, 0, 0},
1579 {"mm1", RegMMX, 0, 1},
1580 {"mm2", RegMMX, 0, 2},
1581 {"mm3", RegMMX, 0, 3},
1582 {"mm4", RegMMX, 0, 4},
1583 {"mm5", RegMMX, 0, 5},
1584 {"mm6", RegMMX, 0, 6},
1585 {"mm7", RegMMX, 0, 7},
1586 {"xmm0", RegXMM, 0, 0},
1587 {"xmm1", RegXMM, 0, 1},
1588 {"xmm2", RegXMM, 0, 2},
1589 {"xmm3", RegXMM, 0, 3},
1590 {"xmm4", RegXMM, 0, 4},
1591 {"xmm5", RegXMM, 0, 5},
1592 {"xmm6", RegXMM, 0, 6},
c0d8940f
JH		 1593 {"xmm7", RegXMM, 0, 7},
1594 {"xmm8", RegXMM, RegRex, 0},
1595 {"xmm9", RegXMM, RegRex, 1},
1596 {"xmm10", RegXMM, RegRex, 2},
1597 {"xmm11", RegXMM, RegRex, 3},
1598 {"xmm12", RegXMM, RegRex, 4},
1599 {"xmm13", RegXMM, RegRex, 5},
1600 {"xmm14", RegXMM, RegRex, 6},
1601 {"xmm15", RegXMM, RegRex, 7},
543613e9 1602 /* No type will make this register rejected for all purposes except
c0d8940f
JH		 1603 for addressing. This saves creating one extra type for RIP. */
1604 {"rip", BaseIndex, 0, 0}
252b5132
RH		 1605};
1606
543613e9
NC		 1607static const reg_entry i386_float_regtab[] =
1608{
3e73aa7c
JH		 1609 {"st(0)", FloatReg|FloatAcc, 0, 0},
1610 {"st(1)", FloatReg, 0, 1},
1611 {"st(2)", FloatReg, 0, 2},
1612 {"st(3)", FloatReg, 0, 3},
1613 {"st(4)", FloatReg, 0, 4},
1614 {"st(5)", FloatReg, 0, 5},
1615 {"st(6)", FloatReg, 0, 6},
1616 {"st(7)", FloatReg, 0, 7}
5f47d35b
AM		 1617};
1618
543613e9 1619#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */
252b5132 1620
543613e9 1621/* Segment stuff. */
252b5132
RH		 1622static const seg_entry cs = { "cs", 0x2e };
1623static const seg_entry ds = { "ds", 0x3e };
1624static const seg_entry ss = { "ss", 0x36 };
1625static const seg_entry es = { "es", 0x26 };
1626static const seg_entry fs = { "fs", 0x64 };
1627static const seg_entry gs = { "gs", 0x65 };
1628
GDB Binutils - Deliverables
This page took 0.364516 seconds and 4 git commands to generate.