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include/opcode/
[deliverable/binutils-gdb.git] / include / opcode / mips.h
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252b5132 1/* mips.h. Mips opcode list for GDB, the GNU debugger.
c3aa17e9 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
c67a084a 3 2003, 2004, 2005, 2008, 2009, 2010
4f1d9bd8 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
7
e4e42b45 8 This file is part of GDB, GAS, and the GNU binutils.
252b5132 9
e4e42b45
NC		 10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
252b5132 14
e4e42b45
NC		 15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
252b5132 19
e4e42b45
NC		 20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
252b5132
RH		 24
25#ifndef _MIPS_H_
26#define _MIPS_H_
27
28/* These are bit masks and shift counts to use to access the various
29 fields of an instruction. To retrieve the X field of an
30 instruction, use the expression
31 (i >> OP_SH_X) & OP_MASK_X
32 To set the same field (to j), use
33 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
34
35 Make sure you use fields that are appropriate for the instruction,
8eaec934 36 of course.
252b5132 37
8eaec934 38 The 'i' format uses OP, RS, RT and IMMEDIATE.
252b5132
RH		 39
40 The 'j' format uses OP and TARGET.
41
42 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
43
44 The 'b' format uses OP, RS, RT and DELTA.
45
46 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
47
48 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
49
50 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
51 breakpoint instruction are not defined; Kane says the breakpoint
52 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
53 only use ten bits). An optional two-operand form of break/sdbbp
4372b673
NC		 54 allows the lower ten bits to be set too, and MIPS32 and later
55 architectures allow 20 bits to be set with a signal operand
56 (using CODE20).
252b5132 57
4372b673 58 The syscall instruction uses CODE20.
252b5132
RH		 59
60 The general coprocessor instructions use COPZ. */
61
62#define OP_MASK_OP 0x3f
63#define OP_SH_OP 26
64#define OP_MASK_RS 0x1f
65#define OP_SH_RS 21
66#define OP_MASK_FR 0x1f
67#define OP_SH_FR 21
68#define OP_MASK_FMT 0x1f
69#define OP_SH_FMT 21
70#define OP_MASK_BCC 0x7
71#define OP_SH_BCC 18
72#define OP_MASK_CODE 0x3ff
73#define OP_SH_CODE 16
74#define OP_MASK_CODE2 0x3ff
75#define OP_SH_CODE2 6
76#define OP_MASK_RT 0x1f
77#define OP_SH_RT 16
78#define OP_MASK_FT 0x1f
79#define OP_SH_FT 16
80#define OP_MASK_CACHE 0x1f
81#define OP_SH_CACHE 16
82#define OP_MASK_RD 0x1f
83#define OP_SH_RD 11
84#define OP_MASK_FS 0x1f
85#define OP_SH_FS 11
86#define OP_MASK_PREFX 0x1f
87#define OP_SH_PREFX 11
88#define OP_MASK_CCC 0x7
89#define OP_SH_CCC 8
4372b673
NC		 90#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
91#define OP_SH_CODE20 6
252b5132
RH		 92#define OP_MASK_SHAMT 0x1f
93#define OP_SH_SHAMT 6
df58fc94
RS		 94#define OP_MASK_EXTLSB OP_MASK_SHAMT
95#define OP_SH_EXTLSB OP_SH_SHAMT
96#define OP_MASK_STYPE OP_MASK_SHAMT
97#define OP_SH_STYPE OP_SH_SHAMT
252b5132
RH		 98#define OP_MASK_FD 0x1f
99#define OP_SH_FD 6
100#define OP_MASK_TARGET 0x3ffffff
101#define OP_SH_TARGET 0
102#define OP_MASK_COPZ 0x1ffffff
103#define OP_SH_COPZ 0
104#define OP_MASK_IMMEDIATE 0xffff
105#define OP_SH_IMMEDIATE 0
106#define OP_MASK_DELTA 0xffff
107#define OP_SH_DELTA 0
108#define OP_MASK_FUNCT 0x3f
109#define OP_SH_FUNCT 0
110#define OP_MASK_SPEC 0x3f
111#define OP_SH_SPEC 0
4372b673
NC		 112#define OP_SH_LOCC 8 /* FP condition code. */
113#define OP_SH_HICC 18 /* FP condition code. */
252b5132 114#define OP_MASK_CC 0x7
4372b673
NC		 115#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
116#define OP_MASK_COP1NORM 0x1 /* a single bit. */
117#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
252b5132
RH		 118#define OP_MASK_COP1SPEC 0xf
119#define OP_MASK_COP1SCLR 0x4
120#define OP_MASK_COP1CMP 0x3
121#define OP_SH_COP1CMP 4
4372b673 122#define OP_SH_FORMAT 21 /* FP short format field. */
252b5132
RH		 123#define OP_MASK_FORMAT 0x7
124#define OP_SH_TRUE 16
125#define OP_MASK_TRUE 0x1
126#define OP_SH_GE 17
127#define OP_MASK_GE 0x01
128#define OP_SH_UNSIGNED 16
129#define OP_MASK_UNSIGNED 0x1
130#define OP_SH_HINT 16
131#define OP_MASK_HINT 0x1f
4372b673 132#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
8eaec934 133#define OP_MASK_MMI 0x3f
252b5132
RH		 134#define OP_SH_MMISUB 6
135#define OP_MASK_MMISUB 0x1f
4372b673 136#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
252b5132 137#define OP_SH_PERFREG 1
4372b673
NC		 138#define OP_SH_SEL 0 /* Coprocessor select field. */
139#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
140#define OP_SH_CODE19 6 /* 19 bit wait code. */
141#define OP_MASK_CODE19 0x7ffff
deec1734
CD		 142#define OP_SH_ALN 21
143#define OP_MASK_ALN 0x7
144#define OP_SH_VSEL 21
145#define OP_MASK_VSEL 0x1f
9752cf1b
RS		 146#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
147 but 0x8-0xf don't select bytes. */
148#define OP_SH_VECBYTE 22
149#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
150#define OP_SH_VECALIGN 21
af7ee8bf
CD		 151#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
152#define OP_SH_INSMSB 11
153#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
154#define OP_SH_EXTMSBD 11
deec1734 155
93c34b9b
CF		 156/* MIPS DSP ASE */
157#define OP_SH_DSPACC 11
158#define OP_MASK_DSPACC 0x3
159#define OP_SH_DSPACC_S 21
160#define OP_MASK_DSPACC_S 0x3
161#define OP_SH_DSPSFT 20
162#define OP_MASK_DSPSFT 0x3f
163#define OP_SH_DSPSFT_7 19
164#define OP_MASK_DSPSFT_7 0x7f
165#define OP_SH_SA3 21
166#define OP_MASK_SA3 0x7
167#define OP_SH_SA4 21
168#define OP_MASK_SA4 0xf
169#define OP_SH_IMM8 16
170#define OP_MASK_IMM8 0xff
171#define OP_SH_IMM10 16
172#define OP_MASK_IMM10 0x3ff
173#define OP_SH_WRDSP 11
174#define OP_MASK_WRDSP 0x3f
175#define OP_SH_RDDSP 16
176#define OP_MASK_RDDSP 0x3f
8b082fb1
TS		 177#define OP_SH_BP 11
178#define OP_MASK_BP 0x3
93c34b9b 179
089b39de
CF		 180/* MIPS MT ASE */
181#define OP_SH_MT_U 5
182#define OP_MASK_MT_U 0x1
183#define OP_SH_MT_H 4
184#define OP_MASK_MT_H 0x1
185#define OP_SH_MTACC_T 18
186#define OP_MASK_MTACC_T 0x3
187#define OP_SH_MTACC_D 13
188#define OP_MASK_MTACC_D 0x3
189
640c0ccd
CD		 190#define OP_OP_COP0 0x10
191#define OP_OP_COP1 0x11
192#define OP_OP_COP2 0x12
193#define OP_OP_COP3 0x13
194#define OP_OP_LWC1 0x31
195#define OP_OP_LWC2 0x32
196#define OP_OP_LWC3 0x33 /* a.k.a. pref */
197#define OP_OP_LDC1 0x35
198#define OP_OP_LDC2 0x36
199#define OP_OP_LDC3 0x37 /* a.k.a. ld */
200#define OP_OP_SWC1 0x39
201#define OP_OP_SWC2 0x3a
202#define OP_OP_SWC3 0x3b
203#define OP_OP_SDC1 0x3d
204#define OP_OP_SDC2 0x3e
205#define OP_OP_SDC3 0x3f /* a.k.a. sd */
206
deec1734
CD		 207/* Values in the 'VSEL' field. */
208#define MDMX_FMTSEL_IMM_QH 0x1d
209#define MDMX_FMTSEL_IMM_OB 0x1e
210#define MDMX_FMTSEL_VEC_QH 0x15
211#define MDMX_FMTSEL_VEC_OB 0x16
4372b673 212
9bcd4f99
TS		 213/* UDI */
214#define OP_SH_UDI1 6
215#define OP_MASK_UDI1 0x1f
216#define OP_SH_UDI2 6
217#define OP_MASK_UDI2 0x3ff
218#define OP_SH_UDI3 6
219#define OP_MASK_UDI3 0x7fff
220#define OP_SH_UDI4 6
221#define OP_MASK_UDI4 0xfffff
222
bb35fb24
NC		 223/* Octeon */
224#define OP_SH_BBITIND 16
225#define OP_MASK_BBITIND 0x1f
226#define OP_SH_CINSPOS 6
227#define OP_MASK_CINSPOS 0x1f
228#define OP_SH_CINSLM1 11
229#define OP_MASK_CINSLM1 0x1f
dd3cbb7e
NC		 230#define OP_SH_SEQI 6
231#define OP_MASK_SEQI 0x3ff
bb35fb24 232
98675402
RS		 233/* Loongson */
234#define OP_SH_OFFSET_A 6
235#define OP_MASK_OFFSET_A 0xff
236#define OP_SH_OFFSET_B 3
237#define OP_MASK_OFFSET_B 0xff
238#define OP_SH_OFFSET_C 6
239#define OP_MASK_OFFSET_C 0x1ff
240#define OP_SH_RZ 0
241#define OP_MASK_RZ 0x1f
242#define OP_SH_FZ 0
243#define OP_MASK_FZ 0x1f
244
df58fc94
RS		 245/* Every MICROMIPSOP_X definition requires a corresponding OP_X
246 definition, and vice versa. This simplifies various parts
247 of the operand handling in GAS. The fields below only exist
248 in the microMIPS encoding, so define each one to have an empty
249 range. */
250#define OP_MASK_CODE10 0
251#define OP_SH_CODE10 0
252#define OP_MASK_TRAP 0
253#define OP_SH_TRAP 0
254#define OP_MASK_OFFSET12 0
255#define OP_SH_OFFSET12 0
256#define OP_MASK_OFFSET10 0
257#define OP_SH_OFFSET10 0
258#define OP_MASK_RS3 0
259#define OP_SH_RS3 0
260#define OP_MASK_MB 0
261#define OP_SH_MB 0
262#define OP_MASK_MC 0
263#define OP_SH_MC 0
264#define OP_MASK_MD 0
265#define OP_SH_MD 0
266#define OP_MASK_ME 0
267#define OP_SH_ME 0
268#define OP_MASK_MF 0
269#define OP_SH_MF 0
270#define OP_MASK_MG 0
271#define OP_SH_MG 0
272#define OP_MASK_MH 0
273#define OP_SH_MH 0
274#define OP_MASK_MI 0
275#define OP_SH_MI 0
276#define OP_MASK_MJ 0
277#define OP_SH_MJ 0
278#define OP_MASK_ML 0
279#define OP_SH_ML 0
280#define OP_MASK_MM 0
281#define OP_SH_MM 0
282#define OP_MASK_MN 0
283#define OP_SH_MN 0
284#define OP_MASK_MP 0
285#define OP_SH_MP 0
286#define OP_MASK_MQ 0
287#define OP_SH_MQ 0
288#define OP_MASK_IMMA 0
289#define OP_SH_IMMA 0
290#define OP_MASK_IMMB 0
291#define OP_SH_IMMB 0
292#define OP_MASK_IMMC 0
293#define OP_SH_IMMC 0
294#define OP_MASK_IMMF 0
295#define OP_SH_IMMF 0
296#define OP_MASK_IMMG 0
297#define OP_SH_IMMG 0
298#define OP_MASK_IMMH 0
299#define OP_SH_IMMH 0
300#define OP_MASK_IMMI 0
301#define OP_SH_IMMI 0
302#define OP_MASK_IMMJ 0
303#define OP_SH_IMMJ 0
304#define OP_MASK_IMML 0
305#define OP_SH_IMML 0
306#define OP_MASK_IMMM 0
307#define OP_SH_IMMM 0
308#define OP_MASK_IMMN 0
309#define OP_SH_IMMN 0
310#define OP_MASK_IMMO 0
311#define OP_SH_IMMO 0
312#define OP_MASK_IMMP 0
313#define OP_SH_IMMP 0
314#define OP_MASK_IMMQ 0
315#define OP_SH_IMMQ 0
316#define OP_MASK_IMMU 0
317#define OP_SH_IMMU 0
318#define OP_MASK_IMMW 0
319#define OP_SH_IMMW 0
320#define OP_MASK_IMMX 0
321#define OP_SH_IMMX 0
322#define OP_MASK_IMMY 0
323#define OP_SH_IMMY 0
324
252b5132
RH		 325/* This structure holds information for a particular instruction. */
326
327struct mips_opcode
328{
329 /* The name of the instruction. */
330 const char *name;
331 /* A string describing the arguments for this instruction. */
332 const char *args;
333 /* The basic opcode for the instruction. When assembling, this
334 opcode is modified by the arguments to produce the actual opcode
335 that is used. If pinfo is INSN_MACRO, then this is 0. */
336 unsigned long match;
337 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
338 relevant portions of the opcode when disassembling. If the
339 actual opcode anded with the match field equals the opcode field,
340 then we have found the correct instruction. If pinfo is
341 INSN_MACRO, then this field is the macro identifier. */
342 unsigned long mask;
343 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
344 of bits describing the instruction, notably any relevant hazard
345 information. */
346 unsigned long pinfo;
dc9a9f39
FF		 347 /* A collection of additional bits describing the instruction. */
348 unsigned long pinfo2;
252b5132
RH		 349 /* A collection of bits describing the instruction sets of which this
350 instruction or macro is a member. */
351 unsigned long membership;
352};
353
27abff54 354/* These are the characters which may appear in the args field of an
252b5132
RH		 355 instruction. They appear in the order in which the fields appear
356 when the instruction is used. Commas and parentheses in the args
357 string are ignored when assembling, and written into the output
358 when disassembling.
359
360 Each of these characters corresponds to a mask field defined above.
361
de9a3e51 362 "1" 5 bit sync type (OP_*_SHAMT)
252b5132
RH		 363 "<" 5 bit shift amount (OP_*_SHAMT)
364 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
365 "a" 26 bit target address (OP_*_TARGET)
366 "b" 5 bit base register (OP_*_RS)
367 "c" 10 bit breakpoint code (OP_*_CODE)
368 "d" 5 bit destination register specifier (OP_*_RD)
369 "h" 5 bit prefx hint (OP_*_PREFX)
370 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
371 "j" 16 bit signed immediate (OP_*_DELTA)
372 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
9752cf1b 373 Also used for immediate operands in vr5400 vector insns.
252b5132
RH		 374 "o" 16 bit signed offset (OP_*_DELTA)
375 "p" 16 bit PC relative branch target address (OP_*_DELTA)
376 "q" 10 bit extra breakpoint code (OP_*_CODE2)
377 "r" 5 bit same register used as both source and target (OP_*_RS)
378 "s" 5 bit source register specifier (OP_*_RS)
379 "t" 5 bit target register (OP_*_RT)
380 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
381 "v" 5 bit same register used as both source and destination (OP_*_RS)
382 "w" 5 bit same register used as both target and destination (OP_*_RT)
4372b673
NC		 383 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
384 (used by clo and clz)
252b5132 385 "C" 25 bit coprocessor function code (OP_*_COPZ)
4372b673
NC		 386 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
387 "J" 19 bit wait function code (OP_*_CODE19)
252b5132
RH		 388 "x" accept and ignore register name
389 "z" must be zero register
af7ee8bf 390 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
ef0ee844 391 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
df58fc94
RS		 392 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
393 microMIPS compatibility).
071742cf 394 Enforces: 0 <= pos < 32.
ef0ee844 395 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
5f74bc13 396 Requires that "+A" or "+E" occur first to set position.
071742cf 397 Enforces: 0 < (pos+size) <= 32.
ef0ee844 398 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
5f74bc13 399 Requires that "+A" or "+E" occur first to set position.
071742cf 400 Enforces: 0 < (pos+size) <= 32.
5f74bc13
CD		 401 (Also used by "dext" w/ different limits, but limits for
402 that are checked by the M_DEXT macro.)
ef0ee844 403 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
5f74bc13 404 Enforces: 32 <= pos < 64.
ef0ee844 405 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
5f74bc13
CD		 406 Requires that "+A" or "+E" occur first to set position.
407 Enforces: 32 < (pos+size) <= 64.
408 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
409 Requires that "+A" or "+E" occur first to set position.
410 Enforces: 32 < (pos+size) <= 64.
411 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
412 Requires that "+A" or "+E" occur first to set position.
413 Enforces: 32 < (pos+size) <= 64.
252b5132
RH		 414
415 Floating point instructions:
416 "D" 5 bit destination register (OP_*_FD)
417 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
418 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
419 "S" 5 bit fs source 1 register (OP_*_FS)
420 "T" 5 bit ft source 2 register (OP_*_FT)
421 "R" 5 bit fr source 3 register (OP_*_FR)
422 "V" 5 bit same register used as floating source and destination (OP_*_FS)
423 "W" 5 bit same register used as floating target and destination (OP_*_FT)
424
425 Coprocessor instructions:
426 "E" 5 bit target register (OP_*_RT)
427 "G" 5 bit destination register (OP_*_RD)
8ff529d8 428 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
252b5132 429 "P" 5 bit performance-monitor register (OP_*_PERFREG)
9752cf1b
RS		 430 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
431 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
432 see also "k" above
bbcc0807
CD		 433 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
434 for pretty-printing in disassembly only.
252b5132
RH		 435
436 Macro instructions:
437 "A" General 32 bit expression
5f74bc13
CD		 438 "I" 32 bit immediate (value placed in imm_expr).
439 "+I" 32 bit immediate (value placed in imm2_expr).
252b5132
RH		 440 "F" 64 bit floating point constant in .rdata
441 "L" 64 bit floating point constant in .lit8
442 "f" 32 bit floating point constant
443 "l" 32 bit floating point constant in .lit4
444
deec1734
CD		 445 MDMX instruction operands (note that while these use the FP register
446 fields, they accept both $fN and $vN names for the registers):
447 "O" MDMX alignment offset (OP_*_ALN)
448 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
449 "X" MDMX destination register (OP_*_FD)
450 "Y" MDMX source register (OP_*_FS)
451 "Z" MDMX source register (OP_*_FT)
452
93c34b9b 453 DSP ASE usage:
8b082fb1 454 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
93c34b9b
CF		 455 "3" 3 bit unsigned immediate (OP_*_SA3)
456 "4" 4 bit unsigned immediate (OP_*_SA4)
457 "5" 8 bit unsigned immediate (OP_*_IMM8)
458 "6" 5 bit unsigned immediate (OP_*_RS)
459 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
460 "8" 6 bit unsigned immediate (OP_*_WRDSP)
461 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
462 "0" 6 bit signed immediate (OP_*_DSPSFT)
463 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
464 "'" 6 bit unsigned immediate (OP_*_RDDSP)
465 "@" 10 bit signed immediate (OP_*_IMM10)
466
089b39de 467 MT ASE usage:
a9e24354
TS		 468 "!" 1 bit usermode flag (OP_*_MT_U)
469 "$" 1 bit load high flag (OP_*_MT_H)
089b39de
CF		 470 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
471 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
472 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
473 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
474 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
475
9bcd4f99
TS		 476 UDI immediates:
477 "+1" UDI immediate bits 6-10
478 "+2" UDI immediate bits 6-15
479 "+3" UDI immediate bits 6-20
480 "+4" UDI immediate bits 6-25
481
bb35fb24
NC		 482 Octeon:
483 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
484 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
485 otherwise skips to next candidate.
486 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
487 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
488 32 <= pos < 64, otherwise skips to next candidate.
dd3cbb7e 489 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
bb35fb24
NC		 490 "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
491 "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
492 cint32/exts32. Enforces non-negative value and that
493 pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
494 position field is "+p" or "+P".
495
1bec78e9
RS		 496 Loongson-3A:
497 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
498 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
499 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
500 "+z" 5-bit rz register (OP_*_RZ)
501 "+Z" 5-bit fz register (OP_*_FZ)
502
252b5132
RH		 503 Other:
504 "()" parens surrounding optional value
505 "," separates operands
9752cf1b 506 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
af7ee8bf 507 "+" Start of extension sequence.
252b5132
RH		 508
509 Characters used so far, for quick reference when adding more:
de9a3e51 510 "1234567890"
089b39de 511 "%[]<>(),+:'@!$*&"
af7ee8bf 512 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
089b39de 513 "abcdefghijklopqrstuvwxz"
af7ee8bf
CD		 514
515 Extension character sequences used so far ("+" followed by the
516 following), for quick reference when adding more:
9bcd4f99 517 "1234"
1bec78e9
RS		 518 "ABCDEFGHIPQSTXZ"
519 "abcpstxz"
252b5132
RH		 520*/
521
522/* These are the bits which may be set in the pinfo field of an
523 instructions, if it is not equal to INSN_MACRO. */
524
525/* Modifies the general purpose register in OP_*_RD. */
526#define INSN_WRITE_GPR_D 0x00000001
527/* Modifies the general purpose register in OP_*_RT. */
528#define INSN_WRITE_GPR_T 0x00000002
529/* Modifies general purpose register 31. */
530#define INSN_WRITE_GPR_31 0x00000004
531/* Modifies the floating point register in OP_*_FD. */
532#define INSN_WRITE_FPR_D 0x00000008
533/* Modifies the floating point register in OP_*_FS. */
534#define INSN_WRITE_FPR_S 0x00000010
535/* Modifies the floating point register in OP_*_FT. */
536#define INSN_WRITE_FPR_T 0x00000020
537/* Reads the general purpose register in OP_*_RS. */
538#define INSN_READ_GPR_S 0x00000040
539/* Reads the general purpose register in OP_*_RT. */
540#define INSN_READ_GPR_T 0x00000080
541/* Reads the floating point register in OP_*_FS. */
542#define INSN_READ_FPR_S 0x00000100
543/* Reads the floating point register in OP_*_FT. */
544#define INSN_READ_FPR_T 0x00000200
545/* Reads the floating point register in OP_*_FR. */
546#define INSN_READ_FPR_R 0x00000400
547/* Modifies coprocessor condition code. */
548#define INSN_WRITE_COND_CODE 0x00000800
549/* Reads coprocessor condition code. */
550#define INSN_READ_COND_CODE 0x00001000
551/* TLB operation. */
552#define INSN_TLB 0x00002000
553/* Reads coprocessor register other than floating point register. */
554#define INSN_COP 0x00004000
555/* Instruction loads value from memory, requiring delay. */
556#define INSN_LOAD_MEMORY_DELAY 0x00008000
557/* Instruction loads value from coprocessor, requiring delay. */
558#define INSN_LOAD_COPROC_DELAY 0x00010000
559/* Instruction has unconditional branch delay slot. */
560#define INSN_UNCOND_BRANCH_DELAY 0x00020000
561/* Instruction has conditional branch delay slot. */
562#define INSN_COND_BRANCH_DELAY 0x00040000
563/* Conditional branch likely: if branch not taken, insn nullified. */
564#define INSN_COND_BRANCH_LIKELY 0x00080000
565/* Moves to coprocessor register, requiring delay. */
566#define INSN_COPROC_MOVE_DELAY 0x00100000
567/* Loads coprocessor register from memory, requiring delay. */
568#define INSN_COPROC_MEMORY_DELAY 0x00200000
569/* Reads the HI register. */
570#define INSN_READ_HI 0x00400000
571/* Reads the LO register. */
572#define INSN_READ_LO 0x00800000
573/* Modifies the HI register. */
574#define INSN_WRITE_HI 0x01000000
575/* Modifies the LO register. */
576#define INSN_WRITE_LO 0x02000000
bcd530a7
RS		 577/* Not to be placed in a branch delay slot, either architecturally
578 or for ease of handling (such as with instructions that take a trap). */
579#define INSN_NO_DELAY_SLOT 0x04000000
252b5132
RH		 580/* Instruction stores value into memory. */
581#define INSN_STORE_MEMORY 0x08000000
582/* Instruction uses single precision floating point. */
583#define FP_S 0x10000000
584/* Instruction uses double precision floating point. */
585#define FP_D 0x20000000
586/* Instruction is part of the tx39's integer multiply family. */
587#define INSN_MULT 0x40000000
2b0c8b40
MR		 588/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
589#define INSN_WRITE_GPR_S 0x80000000
d0799671
AN		 590/* Instruction is actually a macro. It should be ignored by the
591 disassembler, and requires special treatment by the assembler. */
592#define INSN_MACRO 0xffffffff
dc9a9f39
FF		 593
594/* These are the bits which may be set in the pinfo2 field of an
595 instruction. */
596
597/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
239cb185 598#define INSN2_ALIAS 0x00000001
dc9a9f39 599/* Instruction reads MDMX accumulator. */
239cb185 600#define INSN2_READ_MDMX_ACC 0x00000002
dc9a9f39 601/* Instruction writes MDMX accumulator. */
239cb185 602#define INSN2_WRITE_MDMX_ACC 0x00000004
d0799671
AN		 603/* Macro uses single-precision floating-point instructions. This should
604 only be set for macros. For instructions, FP_S in pinfo carries the
605 same information. */
606#define INSN2_M_FP_S 0x00000008
607/* Macro uses double-precision floating-point instructions. This should
608 only be set for macros. For instructions, FP_D in pinfo carries the
609 same information. */
610#define INSN2_M_FP_D 0x00000010
98675402
RS		 611/* Modifies the general purpose register in OP_*_RZ. */
612#define INSN2_WRITE_GPR_Z 0x00000020
613/* Modifies the floating point register in OP_*_FZ. */
614#define INSN2_WRITE_FPR_Z 0x00000040
615/* Reads the general purpose register in OP_*_RZ. */
616#define INSN2_READ_GPR_Z 0x00000080
617/* Reads the floating point register in OP_*_FZ. */
618#define INSN2_READ_FPR_Z 0x00000100
619/* Reads the general purpose register in OP_*_RD. */
620#define INSN2_READ_GPR_D 0x00000200
621
252b5132 622
df58fc94
RS		 623/* Instruction has a branch delay slot that requires a 16-bit instruction. */
624#define INSN2_BRANCH_DELAY_16BIT 0x00000400
625/* Instruction has a branch delay slot that requires a 32-bit instruction. */
626#define INSN2_BRANCH_DELAY_32BIT 0x00000800
df58fc94 627/* Reads the floating point register in MICROMIPSOP_*_FD. */
2b0c8b40
MR		 628#define INSN2_READ_FPR_D 0x00001000
629/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
630#define INSN2_WRITE_GPR_MB 0x00002000
631/* Reads the general purpose register in MICROMIPSOP_*_MC. */
632#define INSN2_READ_GPR_MC 0x00004000
633/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
634#define INSN2_MOD_GPR_MD 0x00008000
635/* Reads the general purpose register in MICROMIPSOP_*_ME. */
636#define INSN2_READ_GPR_ME 0x00010000
637/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
638#define INSN2_MOD_GPR_MF 0x00020000
639/* Reads the general purpose register in MICROMIPSOP_*_MG. */
640#define INSN2_READ_GPR_MG 0x00040000
641/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
642#define INSN2_READ_GPR_MJ 0x00080000
643/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
644#define INSN2_WRITE_GPR_MJ 0x00100000
645/* Reads the general purpose register in MICROMIPSOP_*_MP. */
646#define INSN2_READ_GPR_MP 0x00200000
647/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
648#define INSN2_WRITE_GPR_MP 0x00400000
649/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
650#define INSN2_READ_GPR_MQ 0x00800000
df58fc94 651/* Reads/Writes the stack pointer ($29). */
2b0c8b40 652#define INSN2_MOD_SP 0x01000000
df58fc94 653/* Reads the RA ($31) register. */
2b0c8b40 654#define INSN2_READ_GPR_31 0x02000000
df58fc94 655/* Reads the global pointer ($28). */
2b0c8b40 656#define INSN2_READ_GP 0x04000000
df58fc94 657/* Reads the program counter ($pc). */
2b0c8b40 658#define INSN2_READ_PC 0x08000000
df58fc94 659/* Is an unconditional branch insn. */
2b0c8b40 660#define INSN2_UNCOND_BRANCH 0x10000000
df58fc94 661/* Is a conditional branch insn. */
2b0c8b40
MR		 662#define INSN2_COND_BRANCH 0x20000000
663/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
664#define INSN2_WRITE_GPR_MHI 0x40000000
665/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
666#define INSN2_READ_GPR_MMN 0x80000000
df58fc94 667
e7af610e 668/* Masks used to mark instructions to indicate which MIPS ISA level
56950294
MS		 669 they were introduced in. INSN_ISA_MASK masks an enumeration that
670 specifies the base ISA level(s). The remainder of a 32-bit
671 word constructed using these macros is a bitmask of the remaining
672 INSN_* values below. */
673
674#define INSN_ISA_MASK 0x0000000ful
675
676/* We cannot start at zero due to ISA_UNKNOWN below. */
677#define INSN_ISA1 1
678#define INSN_ISA2 2
679#define INSN_ISA3 3
680#define INSN_ISA4 4
681#define INSN_ISA5 5
682#define INSN_ISA32 6
683#define INSN_ISA32R2 7
684#define INSN_ISA64 8
685#define INSN_ISA64R2 9
686/* Below this point the INSN_* values correspond to combinations of ISAs.
687 They are only for use in the opcodes table to indicate membership of
688 a combination of ISAs that cannot be expressed using the usual inclusion
689 ordering on the above INSN_* values. */
690#define INSN_ISA3_32 10
691#define INSN_ISA3_32R2 11
692#define INSN_ISA4_32 12
693#define INSN_ISA4_32R2 13
694#define INSN_ISA5_32R2 14
695
696/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
697 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
698 this table describes whether at least one of the ISAs described by X
699 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
700 a particular core and X as the ISA level(s) at which a certain instruction
701 is defined.) The ISA(s) described by X is/are implemented by Y iff
702 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
703 is non-zero. */
704static const unsigned int mips_isa_table[] =
705 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
252b5132 706
e6429699 707/* Masks used for Chip specific instructions. */
d051516a 708#define INSN_CHIP_MASK 0xc3ff0c20
e6429699
AN		 709
710/* Cavium Networks Octeon instructions. */
711#define INSN_OCTEON 0x00000800
712
1f25f5d3 713/* Masks used for MIPS-defined ASEs. */
8b082fb1 714#define INSN_ASE_MASK 0x3c00f000
1f25f5d3 715
93c34b9b
CF		 716/* DSP ASE */
717#define INSN_DSP 0x00001000
65263ce3 718#define INSN_DSP64 0x00002000
f79e2745
CM		 719
720/* 0x00004000 is unused. */
721
1f25f5d3 722/* MIPS-3D ASE */
65263ce3 723#define INSN_MIPS3D 0x00008000
1f25f5d3 724
252b5132 725/* MIPS R4650 instruction. */
e7af610e 726#define INSN_4650 0x00010000
252b5132 727/* LSI R4010 instruction. */
e7af610e
NC		 728#define INSN_4010 0x00020000
729/* NEC VR4100 instruction. */
bf40d919 730#define INSN_4100 0x00040000
252b5132 731/* Toshiba R3900 instruction. */
bf40d919 732#define INSN_3900 0x00080000
99c14723
TS		 733/* MIPS R10000 instruction. */
734#define INSN_10000 0x00100000
2228315b
CD		 735/* Broadcom SB-1 instruction. */
736#define INSN_SB1 0x00200000
9752cf1b
RS		 737/* NEC VR4111/VR4181 instruction. */
738#define INSN_4111 0x00400000
739/* NEC VR4120 instruction. */
740#define INSN_4120 0x00800000
741/* NEC VR5400 instruction. */
742#define INSN_5400 0x01000000
743/* NEC VR5500 instruction. */
744#define INSN_5500 0x02000000
39a7806d 745
65263ce3
TS		 746/* MDMX ASE */
747#define INSN_MDMX 0x04000000
089b39de 748/* MT ASE */
65263ce3 749#define INSN_MT 0x08000000
8b082fb1 750/* SmartMIPS ASE */
65263ce3 751#define INSN_SMARTMIPS 0x10000000
8b082fb1
TS		 752/* DSP R2 ASE */
753#define INSN_DSPR2 0x20000000
350cc38d
MS		 754/* ST Microelectronics Loongson 2E. */
755#define INSN_LOONGSON_2E 0x40000000
756/* ST Microelectronics Loongson 2F. */
435b94a4 757#define INSN_LOONGSON_2F 0x80000000
fd503541 758/* Loongson 3A. */
435b94a4 759#define INSN_LOONGSON_3A 0x00000400
52b6b6b9
JM		 760/* RMI Xlr instruction */
761#define INSN_XLR 0x00000020
39a7806d 762
e7af610e
NC		 763/* MIPS ISA defines, use instead of hardcoding ISA level. */
764
765#define ISA_UNKNOWN 0 /* Gas internal use. */
56950294
MS		 766#define ISA_MIPS1 INSN_ISA1
767#define ISA_MIPS2 INSN_ISA2
768#define ISA_MIPS3 INSN_ISA3
769#define ISA_MIPS4 INSN_ISA4
770#define ISA_MIPS5 INSN_ISA5
af7ee8bf 771
56950294
MS		 772#define ISA_MIPS32 INSN_ISA32
773#define ISA_MIPS64 INSN_ISA64
367c01af 774
56950294
MS		 775#define ISA_MIPS32R2 INSN_ISA32R2
776#define ISA_MIPS64R2 INSN_ISA64R2
5f74bc13 777
af7ee8bf 778
156c2f8b
NC		 779/* CPU defines, use instead of hardcoding processor number. Keep this
780 in sync with bfd/archures.c in order for machine selection to work. */
e7af610e 781#define CPU_UNKNOWN 0 /* Gas internal use. */
156c2f8b
NC		 782#define CPU_R3000 3000
783#define CPU_R3900 3900
784#define CPU_R4000 4000
785#define CPU_R4010 4010
786#define CPU_VR4100 4100
787#define CPU_R4111 4111
9752cf1b 788#define CPU_VR4120 4120
156c2f8b
NC		 789#define CPU_R4300 4300
790#define CPU_R4400 4400
791#define CPU_R4600 4600
792#define CPU_R4650 4650
793#define CPU_R5000 5000
9752cf1b
RS		 794#define CPU_VR5400 5400
795#define CPU_VR5500 5500
156c2f8b 796#define CPU_R6000 6000
5a7ea749 797#define CPU_RM7000 7000
156c2f8b 798#define CPU_R8000 8000
98e7aba8 799#define CPU_RM9000 9000
156c2f8b 800#define CPU_R10000 10000
d1cf510e 801#define CPU_R12000 12000
3aa3176b
TS		 802#define CPU_R14000 14000
803#define CPU_R16000 16000
156c2f8b
NC		 804#define CPU_MIPS16 16
805#define CPU_MIPS32 32
af7ee8bf 806#define CPU_MIPS32R2 33
84ea6cf2
NC		 807#define CPU_MIPS5 5
808#define CPU_MIPS64 64
5f74bc13 809#define CPU_MIPS64R2 65
c6c98b38 810#define CPU_SB1 12310201 /* octal 'SB', 01. */
350cc38d
MS		 811#define CPU_LOONGSON_2E 3001
812#define CPU_LOONGSON_2F 3002
fd503541 813#define CPU_LOONGSON_3A 3003
e6429699 814#define CPU_OCTEON 6501
52b6b6b9 815#define CPU_XLR 887682 /* decimal 'XLR' */
156c2f8b 816
1f25f5d3
CD		 817/* Test for membership in an ISA including chip specific ISAs. INSN
818 is pointer to an element of the opcode table; ISA is the specified
819 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
820 test, or zero if no CPU specific ISA test is desired. */
a58ec95a
RS		 821
822#define OPCODE_IS_MEMBER(insn, isa, cpu) \
56950294
MS		 823 (((isa & INSN_ISA_MASK) != 0 \
824 && ((insn)->membership & INSN_ISA_MASK) != 0 \
825 && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
826 (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
827 || ((isa & ~INSN_ISA_MASK) \
828 & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
156c2f8b 829 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
5a7ea749 830 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
98e7aba8 831 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
156c2f8b 832 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
9752cf1b 833 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
99c14723 834 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
3aa3176b
TS		 835 || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
836 || cpu == CPU_R16000) \
2228315b 837 && ((insn)->membership & INSN_10000) != 0) \
5d84d93f 838 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
9752cf1b
RS		 839 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
840 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
841 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
842 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
350cc38d
MS		 843 || (cpu == CPU_LOONGSON_2E \
844 && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
845 || (cpu == CPU_LOONGSON_2F \
846 && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
fd503541
NC		 847 || (cpu == CPU_LOONGSON_3A \
848 && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
e6429699
AN		 849 || (cpu == CPU_OCTEON \
850 && ((insn)->membership & INSN_OCTEON) != 0) \
52b6b6b9 851 || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
e4432525 852 || 0) /* Please keep this term for easier source merging. */
252b5132
RH		 853
854/* This is a list of macro expanded instructions.
8eaec934 855
e7af610e
NC		 856 _I appended means immediate
857 _A appended means address
858 _AB appended means address with base register
859 _D appended means 64 bit floating point constant
860 _S appended means 32 bit floating point constant. */
861
862enum
863{
864 M_ABS,
865 M_ADD_I,
866 M_ADDU_I,
867 M_AND_I,
8b082fb1 868 M_BALIGN,
df58fc94
RS		 869 M_BC1FL,
870 M_BC1TL,
871 M_BC2FL,
872 M_BC2TL,
e7af610e
NC		 873 M_BEQ,
874 M_BEQ_I,
df58fc94 875 M_BEQL,
e7af610e
NC		 876 M_BEQL_I,
877 M_BGE,
878 M_BGEL,
879 M_BGE_I,
880 M_BGEL_I,
881 M_BGEU,
882 M_BGEUL,
883 M_BGEU_I,
884 M_BGEUL_I,
df58fc94
RS		 885 M_BGEZ,
886 M_BGEZL,
887 M_BGEZALL,
e7af610e
NC		 888 M_BGT,
889 M_BGTL,
890 M_BGT_I,
891 M_BGTL_I,
892 M_BGTU,
893 M_BGTUL,
894 M_BGTU_I,
895 M_BGTUL_I,
df58fc94
RS		 896 M_BGTZ,
897 M_BGTZL,
e7af610e
NC		 898 M_BLE,
899 M_BLEL,
900 M_BLE_I,
901 M_BLEL_I,
902 M_BLEU,
903 M_BLEUL,
904 M_BLEU_I,
905 M_BLEUL_I,
df58fc94
RS		 906 M_BLEZ,
907 M_BLEZL,
e7af610e
NC		 908 M_BLT,
909 M_BLTL,
910 M_BLT_I,
911 M_BLTL_I,
912 M_BLTU,
913 M_BLTUL,
914 M_BLTU_I,
915 M_BLTUL_I,
df58fc94
RS		 916 M_BLTZ,
917 M_BLTZL,
918 M_BLTZALL,
e7af610e 919 M_BNE,
df58fc94 920 M_BNEL,
e7af610e
NC		 921 M_BNE_I,
922 M_BNEL_I,
d43b4baf 923 M_CACHE_AB,
df58fc94 924 M_CACHE_OB,
e7af610e
NC		 925 M_DABS,
926 M_DADD_I,
927 M_DADDU_I,
928 M_DDIV_3,
929 M_DDIV_3I,
930 M_DDIVU_3,
931 M_DDIVU_3I,
5f74bc13
CD		 932 M_DEXT,
933 M_DINS,
e7af610e
NC		 934 M_DIV_3,
935 M_DIV_3I,
936 M_DIVU_3,
937 M_DIVU_3I,
938 M_DLA_AB,
1abe91b1 939 M_DLCA_AB,
e7af610e
NC		 940 M_DLI,
941 M_DMUL,
8eaec934 942 M_DMUL_I,
e7af610e 943 M_DMULO,
8eaec934 944 M_DMULO_I,
e7af610e 945 M_DMULOU,
8eaec934 946 M_DMULOU_I,
e7af610e
NC		 947 M_DREM_3,
948 M_DREM_3I,
949 M_DREMU_3,
950 M_DREMU_3I,
951 M_DSUB_I,
952 M_DSUBU_I,
953 M_DSUBU_I_2,
954 M_J_A,
955 M_JAL_1,
956 M_JAL_2,
957 M_JAL_A,
df58fc94
RS		 958 M_JALS_1,
959 M_JALS_2,
960 M_JALS_A,
e7af610e
NC		 961 M_L_DOB,
962 M_L_DAB,
963 M_LA_AB,
964 M_LB_A,
965 M_LB_AB,
966 M_LBU_A,
967 M_LBU_AB,
1abe91b1 968 M_LCA_AB,
e7af610e
NC		 969 M_LD_A,
970 M_LD_OB,
971 M_LD_AB,
972 M_LDC1_AB,
973 M_LDC2_AB,
df58fc94 974 M_LDC2_OB,
e7af610e
NC		 975 M_LDC3_AB,
976 M_LDL_AB,
df58fc94
RS		 977 M_LDL_OB,
978 M_LDM_AB,
979 M_LDM_OB,
980 M_LDP_AB,
981 M_LDP_OB,
e7af610e 982 M_LDR_AB,
df58fc94 983 M_LDR_OB,
e7af610e
NC		 984 M_LH_A,
985 M_LH_AB,
986 M_LHU_A,
987 M_LHU_AB,
988 M_LI,
989 M_LI_D,
990 M_LI_DD,
991 M_LI_S,
992 M_LI_SS,
993 M_LL_AB,
df58fc94 994 M_LL_OB,
e7af610e 995 M_LLD_AB,
df58fc94 996 M_LLD_OB,
e7af610e
NC		 997 M_LS_A,
998 M_LW_A,
999 M_LW_AB,
1000 M_LWC0_A,
1001 M_LWC0_AB,
1002 M_LWC1_A,
1003 M_LWC1_AB,
1004 M_LWC2_A,
1005 M_LWC2_AB,
df58fc94 1006 M_LWC2_OB,
e7af610e
NC		 1007 M_LWC3_A,
1008 M_LWC3_AB,
1009 M_LWL_A,
1010 M_LWL_AB,
df58fc94
RS		 1011 M_LWL_OB,
1012 M_LWM_AB,
1013 M_LWM_OB,
1014 M_LWP_AB,
1015 M_LWP_OB,
e7af610e
NC		 1016 M_LWR_A,
1017 M_LWR_AB,
df58fc94 1018 M_LWR_OB,
e7af610e 1019 M_LWU_AB,
df58fc94 1020 M_LWU_OB,
52b6b6b9
JM		 1021 M_MSGSND,
1022 M_MSGLD,
1023 M_MSGLD_T,
1024 M_MSGWAIT,
1025 M_MSGWAIT_T,
a58ec95a 1026 M_MOVE,
e7af610e 1027 M_MUL,
8eaec934 1028 M_MUL_I,
e7af610e 1029 M_MULO,
8eaec934 1030 M_MULO_I,
e7af610e 1031 M_MULOU,
8eaec934 1032 M_MULOU_I,
e7af610e
NC		 1033 M_NOR_I,
1034 M_OR_I,
3eebd5eb 1035 M_PREF_AB,
df58fc94 1036 M_PREF_OB,
e7af610e
NC		 1037 M_REM_3,
1038 M_REM_3I,
1039 M_REMU_3,
1040 M_REMU_3I,
771c7ce4 1041 M_DROL,
e7af610e 1042 M_ROL,
771c7ce4 1043 M_DROL_I,
e7af610e 1044 M_ROL_I,
771c7ce4 1045 M_DROR,
e7af610e 1046 M_ROR,
771c7ce4 1047 M_DROR_I,
e7af610e
NC		 1048 M_ROR_I,
1049 M_S_DA,
1050 M_S_DOB,
1051 M_S_DAB,
1052 M_S_S,
1053 M_SC_AB,
df58fc94 1054 M_SC_OB,
e7af610e 1055 M_SCD_AB,
df58fc94 1056 M_SCD_OB,
e7af610e
NC		 1057 M_SD_A,
1058 M_SD_OB,
1059 M_SD_AB,
1060 M_SDC1_AB,
1061 M_SDC2_AB,
df58fc94 1062 M_SDC2_OB,
e7af610e
NC		 1063 M_SDC3_AB,
1064 M_SDL_AB,
df58fc94
RS		 1065 M_SDL_OB,
1066 M_SDM_AB,
1067 M_SDM_OB,
1068 M_SDP_AB,
1069 M_SDP_OB,
e7af610e 1070 M_SDR_AB,
df58fc94 1071 M_SDR_OB,
e7af610e
NC		 1072 M_SEQ,
1073 M_SEQ_I,
1074 M_SGE,
1075 M_SGE_I,
1076 M_SGEU,
1077 M_SGEU_I,
1078 M_SGT,
1079 M_SGT_I,
1080 M_SGTU,
1081 M_SGTU_I,
1082 M_SLE,
1083 M_SLE_I,
1084 M_SLEU,
1085 M_SLEU_I,
1086 M_SLT_I,
1087 M_SLTU_I,
1088 M_SNE,
1089 M_SNE_I,
1090 M_SB_A,
1091 M_SB_AB,
1092 M_SH_A,
1093 M_SH_AB,
1094 M_SW_A,
1095 M_SW_AB,
1096 M_SWC0_A,
1097 M_SWC0_AB,
1098 M_SWC1_A,
1099 M_SWC1_AB,
1100 M_SWC2_A,
1101 M_SWC2_AB,
df58fc94 1102 M_SWC2_OB,
e7af610e
NC		 1103 M_SWC3_A,
1104 M_SWC3_AB,
1105 M_SWL_A,
1106 M_SWL_AB,
df58fc94
RS		 1107 M_SWL_OB,
1108 M_SWM_AB,
1109 M_SWM_OB,
1110 M_SWP_AB,
1111 M_SWP_OB,
e7af610e
NC		 1112 M_SWR_A,
1113 M_SWR_AB,
df58fc94 1114 M_SWR_OB,
e7af610e
NC		 1115 M_SUB_I,
1116 M_SUBU_I,
1117 M_SUBU_I_2,
1118 M_TEQ_I,
1119 M_TGE_I,
1120 M_TGEU_I,
1121 M_TLT_I,
1122 M_TLTU_I,
1123 M_TNE_I,
1124 M_TRUNCWD,
1125 M_TRUNCWS,
1126 M_ULD,
1127 M_ULD_A,
1128 M_ULH,
1129 M_ULH_A,
1130 M_ULHU,
1131 M_ULHU_A,
1132 M_ULW,
1133 M_ULW_A,
1134 M_USH,
1135 M_USH_A,
1136 M_USW,
1137 M_USW_A,
1138 M_USD,
1139 M_USD_A,
1140 M_XOR_I,
1141 M_COP0,
1142 M_COP1,
1143 M_COP2,
1144 M_COP3,
1145 M_NUM_MACROS
252b5132
RH		 1146};
1147
1148
1149/* The order of overloaded instructions matters. Label arguments and
1150 register arguments look the same. Instructions that can have either
1151 for arguments must apear in the correct order in this table for the
1152 assembler to pick the right one. In other words, entries with
1153 immediate operands must apear after the same instruction with
1154 registers.
1155
1156 Many instructions are short hand for other instructions (i.e., The
1157 jal <register> instruction is short for jalr <register>). */
1158
1159extern const struct mips_opcode mips_builtin_opcodes[];
1160extern const int bfd_mips_num_builtin_opcodes;
1161extern struct mips_opcode *mips_opcodes;
1162extern int bfd_mips_num_opcodes;
1163#define NUMOPCODES bfd_mips_num_opcodes
1164
1165\f
1166/* The rest of this file adds definitions for the mips16 TinyRISC
1167 processor. */
1168
1169/* These are the bitmasks and shift counts used for the different
1170 fields in the instruction formats. Other than OP, no masks are
1171 provided for the fixed portions of an instruction, since they are
1172 not needed.
1173
1174 The I format uses IMM11.
1175
1176 The RI format uses RX and IMM8.
1177
1178 The RR format uses RX, and RY.
1179
1180 The RRI format uses RX, RY, and IMM5.
1181
1182 The RRR format uses RX, RY, and RZ.
1183
1184 The RRI_A format uses RX, RY, and IMM4.
1185
1186 The SHIFT format uses RX, RY, and SHAMT.
1187
1188 The I8 format uses IMM8.
1189
1190 The I8_MOVR32 format uses RY and REGR32.
1191
1192 The IR_MOV32R format uses REG32R and MOV32Z.
1193
1194 The I64 format uses IMM8.
1195
1196 The RI64 format uses RY and IMM5.
1197 */
1198
1199#define MIPS16OP_MASK_OP 0x1f
1200#define MIPS16OP_SH_OP 11
1201#define MIPS16OP_MASK_IMM11 0x7ff
1202#define MIPS16OP_SH_IMM11 0
1203#define MIPS16OP_MASK_RX 0x7
1204#define MIPS16OP_SH_RX 8
1205#define MIPS16OP_MASK_IMM8 0xff
1206#define MIPS16OP_SH_IMM8 0
1207#define MIPS16OP_MASK_RY 0x7
1208#define MIPS16OP_SH_RY 5
1209#define MIPS16OP_MASK_IMM5 0x1f
1210#define MIPS16OP_SH_IMM5 0
1211#define MIPS16OP_MASK_RZ 0x7
1212#define MIPS16OP_SH_RZ 2
1213#define MIPS16OP_MASK_IMM4 0xf
1214#define MIPS16OP_SH_IMM4 0
1215#define MIPS16OP_MASK_REGR32 0x1f
1216#define MIPS16OP_SH_REGR32 0
1217#define MIPS16OP_MASK_REG32R 0x1f
1218#define MIPS16OP_SH_REG32R 3
1219#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1220#define MIPS16OP_MASK_MOVE32Z 0x7
1221#define MIPS16OP_SH_MOVE32Z 0
1222#define MIPS16OP_MASK_IMM6 0x3f
1223#define MIPS16OP_SH_IMM6 5
1224
bb35fb24
NC		 1225/* These are the characters which may appears in the args field of a MIPS16
1226 instruction. They appear in the order in which the fields appear when the
1227 instruction is used. Commas and parentheses in the args string are ignored
1228 when assembling, and written into the output when disassembling.
252b5132
RH		 1229
1230 "y" 3 bit register (MIPS16OP_*_RY)
1231 "x" 3 bit register (MIPS16OP_*_RX)
1232 "z" 3 bit register (MIPS16OP_*_RZ)
1233 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1234 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1235 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1236 "0" zero register ($0)
1237 "S" stack pointer ($sp or $29)
1238 "P" program counter
1239 "R" return address register ($ra or $31)
1240 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1241 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1242 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1243 "a" 26 bit jump address
1244 "e" 11 bit extension value
1245 "l" register list for entry instruction
1246 "L" register list for exit instruction
1247
1248 The remaining codes may be extended. Except as otherwise noted,
1249 the full extended operand is a 16 bit signed value.
1250 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1251 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1252 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1253 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1254 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1255 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1256 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1257 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1258 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1259 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1260 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1261 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1262 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1263 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1264 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1265 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1266 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1267 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1268 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1269 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1270 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
0499d65b
TS		 1271 "m" 7 bit register list for save instruction (18 bit extended)
1272 "M" 7 bit register list for restore instruction (18 bit extended)
1273 */
1274
1275/* Save/restore encoding for the args field when all 4 registers are
1276 either saved as arguments or saved/restored as statics. */
1277#define MIPS16_ALL_ARGS 0xe
1278#define MIPS16_ALL_STATICS 0xb
252b5132
RH		 1279
1280/* For the mips16, we use the same opcode table format and a few of
1281 the same flags. However, most of the flags are different. */
1282
1283/* Modifies the register in MIPS16OP_*_RX. */
1284#define MIPS16_INSN_WRITE_X 0x00000001
1285/* Modifies the register in MIPS16OP_*_RY. */
1286#define MIPS16_INSN_WRITE_Y 0x00000002
1287/* Modifies the register in MIPS16OP_*_RZ. */
1288#define MIPS16_INSN_WRITE_Z 0x00000004
1289/* Modifies the T ($24) register. */
1290#define MIPS16_INSN_WRITE_T 0x00000008
1291/* Modifies the SP ($29) register. */
1292#define MIPS16_INSN_WRITE_SP 0x00000010
1293/* Modifies the RA ($31) register. */
1294#define MIPS16_INSN_WRITE_31 0x00000020
1295/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1296#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1297/* Reads the register in MIPS16OP_*_RX. */
1298#define MIPS16_INSN_READ_X 0x00000080
1299/* Reads the register in MIPS16OP_*_RY. */
1300#define MIPS16_INSN_READ_Y 0x00000100
1301/* Reads the register in MIPS16OP_*_MOVE32Z. */
1302#define MIPS16_INSN_READ_Z 0x00000200
1303/* Reads the T ($24) register. */
1304#define MIPS16_INSN_READ_T 0x00000400
1305/* Reads the SP ($29) register. */
1306#define MIPS16_INSN_READ_SP 0x00000800
1307/* Reads the RA ($31) register. */
1308#define MIPS16_INSN_READ_31 0x00001000
1309/* Reads the program counter. */
1310#define MIPS16_INSN_READ_PC 0x00002000
1311/* Reads the general purpose register in MIPS16OP_*_REGR32. */
1312#define MIPS16_INSN_READ_GPR_X 0x00004000
9a2c7088
MR		 1313/* Is an unconditional branch insn. */
1314#define MIPS16_INSN_UNCOND_BRANCH 0x00008000
1315/* Is a conditional branch insn. */
1316#define MIPS16_INSN_COND_BRANCH 0x00010000
252b5132
RH		 1317
1318/* The following flags have the same value for the mips16 opcode
1319 table:
7c176fa8
MR		 1320
1321 INSN_ISA3
1322
252b5132
RH		 1323 INSN_UNCOND_BRANCH_DELAY
1324 INSN_COND_BRANCH_DELAY
1325 INSN_COND_BRANCH_LIKELY (never used)
1326 INSN_READ_HI
1327 INSN_READ_LO
1328 INSN_WRITE_HI
1329 INSN_WRITE_LO
1330 INSN_TRAP
7c176fa8 1331 FP_D (never used)
252b5132
RH		 1332 */
1333
1334extern const struct mips_opcode mips16_opcodes[];
1335extern const int bfd_mips16_num_opcodes;
1336
2309ddf2
MR		 1337/* These are the bit masks and shift counts used for the different fields
1338 in the microMIPS instruction formats. No masks are provided for the
1339 fixed portions of an instruction, since they are not needed. */
df58fc94 1340
df58fc94
RS		 1341#define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1342#define MICROMIPSOP_SH_IMMEDIATE 0
1343#define MICROMIPSOP_MASK_DELTA 0xffff
1344#define MICROMIPSOP_SH_DELTA 0
1345#define MICROMIPSOP_MASK_CODE10 0x3ff
1346#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1347#define MICROMIPSOP_MASK_TRAP 0xf
1348#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1349#define MICROMIPSOP_MASK_SHAMT 0x1f
1350#define MICROMIPSOP_SH_SHAMT 11
1351#define MICROMIPSOP_MASK_TARGET 0x3ffffff
1352#define MICROMIPSOP_SH_TARGET 0
1353#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1354#define MICROMIPSOP_SH_EXTLSB 6
1355#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1356#define MICROMIPSOP_SH_EXTMSBD 11
1357#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1358#define MICROMIPSOP_SH_INSMSB 11
1359#define MICROMIPSOP_MASK_CODE 0x3ff
1360#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1361#define MICROMIPSOP_MASK_CODE2 0x3ff
1362#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1363#define MICROMIPSOP_MASK_CACHE 0x1f
1364#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1365#define MICROMIPSOP_MASK_SEL 0x7
1366#define MICROMIPSOP_SH_SEL 11
1367#define MICROMIPSOP_MASK_OFFSET12 0xfff
1368#define MICROMIPSOP_SH_OFFSET12 0
1369#define MICROMIPSOP_MASK_STYPE 0x1f
1370#define MICROMIPSOP_SH_STYPE 16
1371#define MICROMIPSOP_MASK_OFFSET10 0x3ff
1372#define MICROMIPSOP_SH_OFFSET10 6
1373#define MICROMIPSOP_MASK_RS 0x1f
1374#define MICROMIPSOP_SH_RS 16
1375#define MICROMIPSOP_MASK_RT 0x1f
1376#define MICROMIPSOP_SH_RT 21
1377#define MICROMIPSOP_MASK_RD 0x1f
1378#define MICROMIPSOP_SH_RD 11
1379#define MICROMIPSOP_MASK_FS 0x1f
1380#define MICROMIPSOP_SH_FS 16
1381#define MICROMIPSOP_MASK_FT 0x1f
1382#define MICROMIPSOP_SH_FT 21
1383#define MICROMIPSOP_MASK_FD 0x1f
1384#define MICROMIPSOP_SH_FD 11
1385#define MICROMIPSOP_MASK_FR 0x1f
1386#define MICROMIPSOP_SH_FR 6
1387#define MICROMIPSOP_MASK_RS3 0x1f
1388#define MICROMIPSOP_SH_RS3 6
1389#define MICROMIPSOP_MASK_PREFX 0x1f
1390#define MICROMIPSOP_SH_PREFX 11
1391#define MICROMIPSOP_MASK_BCC 0x7
1392#define MICROMIPSOP_SH_BCC 18
1393#define MICROMIPSOP_MASK_CCC 0x7
1394#define MICROMIPSOP_SH_CCC 13
1395#define MICROMIPSOP_MASK_COPZ 0x7fffff
1396#define MICROMIPSOP_SH_COPZ 3
1397
1398#define MICROMIPSOP_MASK_MB 0x7
1399#define MICROMIPSOP_SH_MB 23
1400#define MICROMIPSOP_MASK_MC 0x7
1401#define MICROMIPSOP_SH_MC 4
1402#define MICROMIPSOP_MASK_MD 0x7
1403#define MICROMIPSOP_SH_MD 7
1404#define MICROMIPSOP_MASK_ME 0x7
1405#define MICROMIPSOP_SH_ME 1
1406#define MICROMIPSOP_MASK_MF 0x7
1407#define MICROMIPSOP_SH_MF 3
1408#define MICROMIPSOP_MASK_MG 0x7
1409#define MICROMIPSOP_SH_MG 0
1410#define MICROMIPSOP_MASK_MH 0x7
1411#define MICROMIPSOP_SH_MH 7
1412#define MICROMIPSOP_MASK_MI 0x7
1413#define MICROMIPSOP_SH_MI 7
1414#define MICROMIPSOP_MASK_MJ 0x1f
1415#define MICROMIPSOP_SH_MJ 0
1416#define MICROMIPSOP_MASK_ML 0x7
1417#define MICROMIPSOP_SH_ML 4
1418#define MICROMIPSOP_MASK_MM 0x7
1419#define MICROMIPSOP_SH_MM 1
1420#define MICROMIPSOP_MASK_MN 0x7
1421#define MICROMIPSOP_SH_MN 4
1422#define MICROMIPSOP_MASK_MP 0x1f
1423#define MICROMIPSOP_SH_MP 5
1424#define MICROMIPSOP_MASK_MQ 0x7
1425#define MICROMIPSOP_SH_MQ 7
1426
1427#define MICROMIPSOP_MASK_IMMA 0x7f
1428#define MICROMIPSOP_SH_IMMA 0
1429#define MICROMIPSOP_MASK_IMMB 0x7
1430#define MICROMIPSOP_SH_IMMB 1
1431#define MICROMIPSOP_MASK_IMMC 0xf
1432#define MICROMIPSOP_SH_IMMC 0
1433#define MICROMIPSOP_MASK_IMMD 0x3ff
1434#define MICROMIPSOP_SH_IMMD 0
1435#define MICROMIPSOP_MASK_IMME 0x7f
1436#define MICROMIPSOP_SH_IMME 0
1437#define MICROMIPSOP_MASK_IMMF 0xf
1438#define MICROMIPSOP_SH_IMMF 0
1439#define MICROMIPSOP_MASK_IMMG 0xf
1440#define MICROMIPSOP_SH_IMMG 0
1441#define MICROMIPSOP_MASK_IMMH 0xf
1442#define MICROMIPSOP_SH_IMMH 0
1443#define MICROMIPSOP_MASK_IMMI 0x7f
1444#define MICROMIPSOP_SH_IMMI 0
1445#define MICROMIPSOP_MASK_IMMJ 0xf
1446#define MICROMIPSOP_SH_IMMJ 0
1447#define MICROMIPSOP_MASK_IMML 0xf
1448#define MICROMIPSOP_SH_IMML 0
1449#define MICROMIPSOP_MASK_IMMM 0x7
1450#define MICROMIPSOP_SH_IMMM 1
1451#define MICROMIPSOP_MASK_IMMN 0x3
1452#define MICROMIPSOP_SH_IMMN 4
1453#define MICROMIPSOP_MASK_IMMO 0xf
1454#define MICROMIPSOP_SH_IMMO 0
1455#define MICROMIPSOP_MASK_IMMP 0x1f
1456#define MICROMIPSOP_SH_IMMP 0
1457#define MICROMIPSOP_MASK_IMMQ 0x7fffff
1458#define MICROMIPSOP_SH_IMMQ 0
1459#define MICROMIPSOP_MASK_IMMU 0x1f
1460#define MICROMIPSOP_SH_IMMU 0
1461#define MICROMIPSOP_MASK_IMMW 0x3f
1462#define MICROMIPSOP_SH_IMMW 1
1463#define MICROMIPSOP_MASK_IMMX 0xf
1464#define MICROMIPSOP_SH_IMMX 1
1465#define MICROMIPSOP_MASK_IMMY 0x1ff
1466#define MICROMIPSOP_SH_IMMY 1
1467
1468/* Placeholders for fields that only exist in the traditional 32-bit
1469 instruction encoding; see the comment above for details. */
1470#define MICROMIPSOP_MASK_CODE20 0
1471#define MICROMIPSOP_SH_CODE20 0
1472#define MICROMIPSOP_MASK_PERFREG 0
1473#define MICROMIPSOP_SH_PERFREG 0
1474#define MICROMIPSOP_MASK_CODE19 0
1475#define MICROMIPSOP_SH_CODE19 0
1476#define MICROMIPSOP_MASK_ALN 0
1477#define MICROMIPSOP_SH_ALN 0
1478#define MICROMIPSOP_MASK_VECBYTE 0
1479#define MICROMIPSOP_SH_VECBYTE 0
1480#define MICROMIPSOP_MASK_VECALIGN 0
1481#define MICROMIPSOP_SH_VECALIGN 0
1482#define MICROMIPSOP_MASK_DSPACC 0
1483#define MICROMIPSOP_SH_DSPACC 0
1484#define MICROMIPSOP_MASK_DSPACC_S 0
1485#define MICROMIPSOP_SH_DSPACC_S 0
1486#define MICROMIPSOP_MASK_DSPSFT 0
1487#define MICROMIPSOP_SH_DSPSFT 0
1488#define MICROMIPSOP_MASK_DSPSFT_7 0
1489#define MICROMIPSOP_SH_DSPSFT_7 0
1490#define MICROMIPSOP_MASK_SA3 0
1491#define MICROMIPSOP_SH_SA3 0
1492#define MICROMIPSOP_MASK_SA4 0
1493#define MICROMIPSOP_SH_SA4 0
1494#define MICROMIPSOP_MASK_IMM8 0
1495#define MICROMIPSOP_SH_IMM8 0
1496#define MICROMIPSOP_MASK_IMM10 0
1497#define MICROMIPSOP_SH_IMM10 0
1498#define MICROMIPSOP_MASK_WRDSP 0
1499#define MICROMIPSOP_SH_WRDSP 0
1500#define MICROMIPSOP_MASK_RDDSP 0
1501#define MICROMIPSOP_SH_RDDSP 0
1502#define MICROMIPSOP_MASK_BP 0
1503#define MICROMIPSOP_SH_BP 0
1504#define MICROMIPSOP_MASK_MT_U 0
1505#define MICROMIPSOP_SH_MT_U 0
1506#define MICROMIPSOP_MASK_MT_H 0
1507#define MICROMIPSOP_SH_MT_H 0
1508#define MICROMIPSOP_MASK_MTACC_T 0
1509#define MICROMIPSOP_SH_MTACC_T 0
1510#define MICROMIPSOP_MASK_MTACC_D 0
1511#define MICROMIPSOP_SH_MTACC_D 0
1512#define MICROMIPSOP_MASK_BBITIND 0
1513#define MICROMIPSOP_SH_BBITIND 0
1514#define MICROMIPSOP_MASK_CINSPOS 0
1515#define MICROMIPSOP_SH_CINSPOS 0
1516#define MICROMIPSOP_MASK_CINSLM1 0
1517#define MICROMIPSOP_SH_CINSLM1 0
1518#define MICROMIPSOP_MASK_SEQI 0
1519#define MICROMIPSOP_SH_SEQI 0
1520#define MICROMIPSOP_SH_OFFSET_A 0
1521#define MICROMIPSOP_MASK_OFFSET_A 0
1522#define MICROMIPSOP_SH_OFFSET_B 0
1523#define MICROMIPSOP_MASK_OFFSET_B 0
1524#define MICROMIPSOP_SH_OFFSET_C 0
1525#define MICROMIPSOP_MASK_OFFSET_C 0
1526#define MICROMIPSOP_SH_RZ 0
1527#define MICROMIPSOP_MASK_RZ 0
1528#define MICROMIPSOP_SH_FZ 0
1529#define MICROMIPSOP_MASK_FZ 0
1530
1531/* These are the characters which may appears in the args field of a microMIPS
1532 instruction. They appear in the order in which the fields appear
1533 when the instruction is used. Commas and parentheses in the args
1534 string are ignored when assembling, and written into the output
1535 when disassembling.
1536
1537 The followings are for 16-bit microMIPS instructions.
1538
1539 "ma" must be $28
1540 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1541 The same register used as both source and target.
1542 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1543 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1544 The same register used as both source and target.
1545 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1546 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1547 "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
1548 "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
1549 ("mh" and "mi" form a valid 3-bit register pair)
1550 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1551 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1552 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1553 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1554 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1555 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1556 "mr" must be program counter
1557 "ms" must be $29
1558 "mt" must be the same as the previous register
1559 "mx" must be the same as the destination register
1560 "my" must be $31
1561 "mz" must be $0
1562
1563 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1564 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1565 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1566 32768, 65535) (MICROMIPSOP_*_IMMC)
1567 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1568 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1569 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1570 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1571 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1572 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1573 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1574 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1575 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1576 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1577 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1578 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1579 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1580 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1581 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1582 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1583 "mZ" must be zero
1584
1585 In most cases 32-bit microMIPS instructions use the same characters
1586 as MIPS (with ADDIUPC being a notable exception, but there are some
1587 others too).
1588
1589 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1590 "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
1591 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1592 ">" shift amount between 32 and 63, stored after subtracting 32
1593 (MICROMIPSOP_*_SHAMT)
1594 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1595 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1596 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1597 "b" 5-bit base register (MICROMIPSOP_*_RS)
1598 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1599 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1600 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1601 "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1602 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1603 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1604 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1605 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1606 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1607 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1608 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1609 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1610 "t" 5-bit target register (MICROMIPSOP_*_RT)
1611 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1612 "v" 5-bit same register used as both source and destination
1613 (MICROMIPSOP_*_RS)
1614 "w" 5-bit same register used as both target and destination
1615 (MICROMIPSOP_*_RT)
1616 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1617 "z" must be zero register
1618 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1619 "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1620 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1621
1622 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1623 LSB (MICROMIPSOP_*_EXTLSB).
1624 Enforces: 0 <= pos < 32.
1625 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1626 Requires that "+A" or "+E" occur first to set position.
1627 Enforces: 0 < (pos+size) <= 32.
1628 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1629 Requires that "+A" or "+E" occur first to set position.
1630 Enforces: 0 < (pos+size) <= 32.
1631 (Also used by DEXT w/ different limits, but limits for
1632 that are checked by the M_DEXT macro.)
1633 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1634 Enforces: 32 <= pos < 64.
1635 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1636 Requires that "+A" or "+E" occur first to set position.
1637 Enforces: 32 < (pos+size) <= 64.
1638 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1639 Requires that "+A" or "+E" occur first to set position.
1640 Enforces: 32 < (pos+size) <= 64.
1641 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1642 Requires that "+A" or "+E" occur first to set position.
1643 Enforces: 32 < (pos+size) <= 64.
1644
1645 PC-relative addition (ADDIUPC) instruction:
1646 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1647 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1648
1649 Floating point instructions:
1650 "D" 5-bit destination register (MICROMIPSOP_*_FD)
1651 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1652 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1653 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1654 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1655 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1656 "V" 5-bit same register used as floating source and destination or target
1657 (MICROMIPSOP_*_FS)
1658
1659 Coprocessor instructions:
1660 "E" 5-bit target register (MICROMIPSOP_*_RT)
1661 "G" 5-bit destination register (MICROMIPSOP_*_RD)
1662 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1663 "+D" combined destination register ("G") and sel ("H") for CP0 ops,
1664 for pretty-printing in disassembly only
1665
1666 Macro instructions:
1667 "A" general 32 bit expression
1668 "I" 32-bit immediate (value placed in imm_expr).
1669 "+I" 32-bit immediate (value placed in imm2_expr).
1670 "F" 64-bit floating point constant in .rdata
1671 "L" 64-bit floating point constant in .lit8
1672 "f" 32-bit floating point constant
1673 "l" 32-bit floating point constant in .lit4
1674
1675 Other:
1676 "()" parens surrounding optional value
1677 "," separates operands
1678 "+" start of extension sequence
1679 "m" start of microMIPS extension sequence
1680
1681 Characters used so far, for quick reference when adding more:
1682 "1234567890"
1683 "<>(),+.|~"
1684 "ABCDEFGHI KLMN RST V "
1685 "abcd f hijklmnopqrstuvw yz"
1686
1687 Extension character sequences used so far ("+" followed by the
1688 following), for quick reference when adding more:
1689 ""
1690 ""
1691 "ABCDEFGHI"
1692 ""
1693
1694 Extension character sequences used so far ("m" followed by the
1695 following), for quick reference when adding more:
1696 ""
1697 ""
1698 " BCDEFGHIJ LMNOPQ U WXYZ"
1699 " bcdefghij lmn pq st xyz"
1700*/
1701
1702extern const struct mips_opcode micromips_opcodes[];
1703extern const int bfd_micromips_num_opcodes;
1704
c67a084a
NC		 1705/* A NOP insn impemented as "or at,at,zero".
1706 Used to implement -mfix-loongson2f. */
1707#define LOONGSON2F_NOP_INSN 0x00200825
1708
252b5132 1709#endif /* _MIPS_H_ */
GDB Binutils - Deliverables
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