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252b5132 | 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
4b95cf5c | 2 | Copyright (C) 1993-2014 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by Ralph Campbell and OSF |
4 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
5 | ||
e4e42b45 | 6 | This file is part of GDB, GAS, and the GNU binutils. |
252b5132 | 7 | |
e4e42b45 NC |
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version 3, | |
11 | or (at your option) any later version. | |
252b5132 | 12 | |
e4e42b45 NC |
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
252b5132 | 17 | |
e4e42b45 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this file; see the file COPYING3. If not, write to the Free | |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
21 | MA 02110-1301, USA. */ | |
252b5132 RH |
22 | |
23 | #ifndef _MIPS_H_ | |
24 | #define _MIPS_H_ | |
25 | ||
35d0a169 MR |
26 | #include "bfd.h" |
27 | ||
252b5132 RH |
28 | /* These are bit masks and shift counts to use to access the various |
29 | fields of an instruction. To retrieve the X field of an | |
30 | instruction, use the expression | |
31 | (i >> OP_SH_X) & OP_MASK_X | |
32 | To set the same field (to j), use | |
33 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) | |
34 | ||
35 | Make sure you use fields that are appropriate for the instruction, | |
8eaec934 | 36 | of course. |
252b5132 | 37 | |
8eaec934 | 38 | The 'i' format uses OP, RS, RT and IMMEDIATE. |
252b5132 RH |
39 | |
40 | The 'j' format uses OP and TARGET. | |
41 | ||
42 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. | |
43 | ||
44 | The 'b' format uses OP, RS, RT and DELTA. | |
45 | ||
46 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. | |
47 | ||
48 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. | |
49 | ||
50 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the | |
51 | breakpoint instruction are not defined; Kane says the breakpoint | |
52 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers | |
53 | only use ten bits). An optional two-operand form of break/sdbbp | |
4372b673 NC |
54 | allows the lower ten bits to be set too, and MIPS32 and later |
55 | architectures allow 20 bits to be set with a signal operand | |
56 | (using CODE20). | |
252b5132 | 57 | |
4372b673 | 58 | The syscall instruction uses CODE20. |
252b5132 RH |
59 | |
60 | The general coprocessor instructions use COPZ. */ | |
61 | ||
62 | #define OP_MASK_OP 0x3f | |
63 | #define OP_SH_OP 26 | |
64 | #define OP_MASK_RS 0x1f | |
65 | #define OP_SH_RS 21 | |
66 | #define OP_MASK_FR 0x1f | |
67 | #define OP_SH_FR 21 | |
68 | #define OP_MASK_FMT 0x1f | |
69 | #define OP_SH_FMT 21 | |
70 | #define OP_MASK_BCC 0x7 | |
71 | #define OP_SH_BCC 18 | |
72 | #define OP_MASK_CODE 0x3ff | |
73 | #define OP_SH_CODE 16 | |
74 | #define OP_MASK_CODE2 0x3ff | |
75 | #define OP_SH_CODE2 6 | |
76 | #define OP_MASK_RT 0x1f | |
77 | #define OP_SH_RT 16 | |
78 | #define OP_MASK_FT 0x1f | |
79 | #define OP_SH_FT 16 | |
80 | #define OP_MASK_CACHE 0x1f | |
81 | #define OP_SH_CACHE 16 | |
82 | #define OP_MASK_RD 0x1f | |
83 | #define OP_SH_RD 11 | |
84 | #define OP_MASK_FS 0x1f | |
85 | #define OP_SH_FS 11 | |
86 | #define OP_MASK_PREFX 0x1f | |
87 | #define OP_SH_PREFX 11 | |
88 | #define OP_MASK_CCC 0x7 | |
89 | #define OP_SH_CCC 8 | |
4372b673 NC |
90 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
91 | #define OP_SH_CODE20 6 | |
252b5132 RH |
92 | #define OP_MASK_SHAMT 0x1f |
93 | #define OP_SH_SHAMT 6 | |
df58fc94 RS |
94 | #define OP_MASK_EXTLSB OP_MASK_SHAMT |
95 | #define OP_SH_EXTLSB OP_SH_SHAMT | |
96 | #define OP_MASK_STYPE OP_MASK_SHAMT | |
97 | #define OP_SH_STYPE OP_SH_SHAMT | |
252b5132 RH |
98 | #define OP_MASK_FD 0x1f |
99 | #define OP_SH_FD 6 | |
100 | #define OP_MASK_TARGET 0x3ffffff | |
101 | #define OP_SH_TARGET 0 | |
102 | #define OP_MASK_COPZ 0x1ffffff | |
103 | #define OP_SH_COPZ 0 | |
104 | #define OP_MASK_IMMEDIATE 0xffff | |
105 | #define OP_SH_IMMEDIATE 0 | |
106 | #define OP_MASK_DELTA 0xffff | |
107 | #define OP_SH_DELTA 0 | |
108 | #define OP_MASK_FUNCT 0x3f | |
109 | #define OP_SH_FUNCT 0 | |
110 | #define OP_MASK_SPEC 0x3f | |
111 | #define OP_SH_SPEC 0 | |
4372b673 NC |
112 | #define OP_SH_LOCC 8 /* FP condition code. */ |
113 | #define OP_SH_HICC 18 /* FP condition code. */ | |
252b5132 | 114 | #define OP_MASK_CC 0x7 |
4372b673 NC |
115 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
116 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ | |
117 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ | |
252b5132 RH |
118 | #define OP_MASK_COP1SPEC 0xf |
119 | #define OP_MASK_COP1SCLR 0x4 | |
120 | #define OP_MASK_COP1CMP 0x3 | |
121 | #define OP_SH_COP1CMP 4 | |
4372b673 | 122 | #define OP_SH_FORMAT 21 /* FP short format field. */ |
252b5132 RH |
123 | #define OP_MASK_FORMAT 0x7 |
124 | #define OP_SH_TRUE 16 | |
125 | #define OP_MASK_TRUE 0x1 | |
126 | #define OP_SH_GE 17 | |
127 | #define OP_MASK_GE 0x01 | |
128 | #define OP_SH_UNSIGNED 16 | |
129 | #define OP_MASK_UNSIGNED 0x1 | |
130 | #define OP_SH_HINT 16 | |
131 | #define OP_MASK_HINT 0x1f | |
4372b673 | 132 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
8eaec934 | 133 | #define OP_MASK_MMI 0x3f |
252b5132 RH |
134 | #define OP_SH_MMISUB 6 |
135 | #define OP_MASK_MMISUB 0x1f | |
4372b673 | 136 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
252b5132 | 137 | #define OP_SH_PERFREG 1 |
4372b673 NC |
138 | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
139 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ | |
140 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ | |
141 | #define OP_MASK_CODE19 0x7ffff | |
deec1734 CD |
142 | #define OP_SH_ALN 21 |
143 | #define OP_MASK_ALN 0x7 | |
144 | #define OP_SH_VSEL 21 | |
145 | #define OP_MASK_VSEL 0x1f | |
9752cf1b RS |
146 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
147 | but 0x8-0xf don't select bytes. */ | |
148 | #define OP_SH_VECBYTE 22 | |
149 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ | |
150 | #define OP_SH_VECALIGN 21 | |
af7ee8bf CD |
151 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
152 | #define OP_SH_INSMSB 11 | |
153 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
154 | #define OP_SH_EXTMSBD 11 | |
deec1734 | 155 | |
93c34b9b CF |
156 | /* MIPS DSP ASE */ |
157 | #define OP_SH_DSPACC 11 | |
158 | #define OP_MASK_DSPACC 0x3 | |
159 | #define OP_SH_DSPACC_S 21 | |
160 | #define OP_MASK_DSPACC_S 0x3 | |
161 | #define OP_SH_DSPSFT 20 | |
162 | #define OP_MASK_DSPSFT 0x3f | |
163 | #define OP_SH_DSPSFT_7 19 | |
164 | #define OP_MASK_DSPSFT_7 0x7f | |
165 | #define OP_SH_SA3 21 | |
166 | #define OP_MASK_SA3 0x7 | |
167 | #define OP_SH_SA4 21 | |
168 | #define OP_MASK_SA4 0xf | |
169 | #define OP_SH_IMM8 16 | |
170 | #define OP_MASK_IMM8 0xff | |
171 | #define OP_SH_IMM10 16 | |
172 | #define OP_MASK_IMM10 0x3ff | |
173 | #define OP_SH_WRDSP 11 | |
174 | #define OP_MASK_WRDSP 0x3f | |
175 | #define OP_SH_RDDSP 16 | |
176 | #define OP_MASK_RDDSP 0x3f | |
8b082fb1 TS |
177 | #define OP_SH_BP 11 |
178 | #define OP_MASK_BP 0x3 | |
93c34b9b | 179 | |
089b39de CF |
180 | /* MIPS MT ASE */ |
181 | #define OP_SH_MT_U 5 | |
182 | #define OP_MASK_MT_U 0x1 | |
183 | #define OP_SH_MT_H 4 | |
184 | #define OP_MASK_MT_H 0x1 | |
185 | #define OP_SH_MTACC_T 18 | |
186 | #define OP_MASK_MTACC_T 0x3 | |
187 | #define OP_SH_MTACC_D 13 | |
188 | #define OP_MASK_MTACC_D 0x3 | |
189 | ||
dec0624d MR |
190 | /* MIPS MCU ASE */ |
191 | #define OP_MASK_3BITPOS 0x7 | |
192 | #define OP_SH_3BITPOS 12 | |
193 | #define OP_MASK_OFFSET12 0xfff | |
194 | #define OP_SH_OFFSET12 0 | |
195 | ||
640c0ccd CD |
196 | #define OP_OP_COP0 0x10 |
197 | #define OP_OP_COP1 0x11 | |
198 | #define OP_OP_COP2 0x12 | |
199 | #define OP_OP_COP3 0x13 | |
200 | #define OP_OP_LWC1 0x31 | |
201 | #define OP_OP_LWC2 0x32 | |
202 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ | |
203 | #define OP_OP_LDC1 0x35 | |
204 | #define OP_OP_LDC2 0x36 | |
205 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ | |
206 | #define OP_OP_SWC1 0x39 | |
207 | #define OP_OP_SWC2 0x3a | |
208 | #define OP_OP_SWC3 0x3b | |
209 | #define OP_OP_SDC1 0x3d | |
210 | #define OP_OP_SDC2 0x3e | |
211 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ | |
212 | ||
b015e599 AP |
213 | /* MIPS VIRT ASE */ |
214 | #define OP_MASK_CODE10 0x3ff | |
215 | #define OP_SH_CODE10 11 | |
216 | ||
deec1734 CD |
217 | /* Values in the 'VSEL' field. */ |
218 | #define MDMX_FMTSEL_IMM_QH 0x1d | |
219 | #define MDMX_FMTSEL_IMM_OB 0x1e | |
220 | #define MDMX_FMTSEL_VEC_QH 0x15 | |
221 | #define MDMX_FMTSEL_VEC_OB 0x16 | |
4372b673 | 222 | |
9bcd4f99 TS |
223 | /* UDI */ |
224 | #define OP_SH_UDI1 6 | |
225 | #define OP_MASK_UDI1 0x1f | |
226 | #define OP_SH_UDI2 6 | |
227 | #define OP_MASK_UDI2 0x3ff | |
228 | #define OP_SH_UDI3 6 | |
229 | #define OP_MASK_UDI3 0x7fff | |
230 | #define OP_SH_UDI4 6 | |
231 | #define OP_MASK_UDI4 0xfffff | |
232 | ||
bb35fb24 NC |
233 | /* Octeon */ |
234 | #define OP_SH_BBITIND 16 | |
235 | #define OP_MASK_BBITIND 0x1f | |
236 | #define OP_SH_CINSPOS 6 | |
237 | #define OP_MASK_CINSPOS 0x1f | |
238 | #define OP_SH_CINSLM1 11 | |
239 | #define OP_MASK_CINSLM1 0x1f | |
dd3cbb7e NC |
240 | #define OP_SH_SEQI 6 |
241 | #define OP_MASK_SEQI 0x3ff | |
bb35fb24 | 242 | |
98675402 RS |
243 | /* Loongson */ |
244 | #define OP_SH_OFFSET_A 6 | |
245 | #define OP_MASK_OFFSET_A 0xff | |
246 | #define OP_SH_OFFSET_B 3 | |
247 | #define OP_MASK_OFFSET_B 0xff | |
248 | #define OP_SH_OFFSET_C 6 | |
249 | #define OP_MASK_OFFSET_C 0x1ff | |
250 | #define OP_SH_RZ 0 | |
251 | #define OP_MASK_RZ 0x1f | |
252 | #define OP_SH_FZ 0 | |
253 | #define OP_MASK_FZ 0x1f | |
254 | ||
df58fc94 RS |
255 | /* Every MICROMIPSOP_X definition requires a corresponding OP_X |
256 | definition, and vice versa. This simplifies various parts | |
257 | of the operand handling in GAS. The fields below only exist | |
258 | in the microMIPS encoding, so define each one to have an empty | |
259 | range. */ | |
df58fc94 RS |
260 | #define OP_MASK_TRAP 0 |
261 | #define OP_SH_TRAP 0 | |
df58fc94 RS |
262 | #define OP_MASK_OFFSET10 0 |
263 | #define OP_SH_OFFSET10 0 | |
264 | #define OP_MASK_RS3 0 | |
265 | #define OP_SH_RS3 0 | |
266 | #define OP_MASK_MB 0 | |
267 | #define OP_SH_MB 0 | |
268 | #define OP_MASK_MC 0 | |
269 | #define OP_SH_MC 0 | |
270 | #define OP_MASK_MD 0 | |
271 | #define OP_SH_MD 0 | |
272 | #define OP_MASK_ME 0 | |
273 | #define OP_SH_ME 0 | |
274 | #define OP_MASK_MF 0 | |
275 | #define OP_SH_MF 0 | |
276 | #define OP_MASK_MG 0 | |
277 | #define OP_SH_MG 0 | |
278 | #define OP_MASK_MH 0 | |
279 | #define OP_SH_MH 0 | |
df58fc94 RS |
280 | #define OP_MASK_MJ 0 |
281 | #define OP_SH_MJ 0 | |
282 | #define OP_MASK_ML 0 | |
283 | #define OP_SH_ML 0 | |
284 | #define OP_MASK_MM 0 | |
285 | #define OP_SH_MM 0 | |
286 | #define OP_MASK_MN 0 | |
287 | #define OP_SH_MN 0 | |
288 | #define OP_MASK_MP 0 | |
289 | #define OP_SH_MP 0 | |
290 | #define OP_MASK_MQ 0 | |
291 | #define OP_SH_MQ 0 | |
292 | #define OP_MASK_IMMA 0 | |
293 | #define OP_SH_IMMA 0 | |
294 | #define OP_MASK_IMMB 0 | |
295 | #define OP_SH_IMMB 0 | |
296 | #define OP_MASK_IMMC 0 | |
297 | #define OP_SH_IMMC 0 | |
298 | #define OP_MASK_IMMF 0 | |
299 | #define OP_SH_IMMF 0 | |
300 | #define OP_MASK_IMMG 0 | |
301 | #define OP_SH_IMMG 0 | |
302 | #define OP_MASK_IMMH 0 | |
303 | #define OP_SH_IMMH 0 | |
304 | #define OP_MASK_IMMI 0 | |
305 | #define OP_SH_IMMI 0 | |
306 | #define OP_MASK_IMMJ 0 | |
307 | #define OP_SH_IMMJ 0 | |
308 | #define OP_MASK_IMML 0 | |
309 | #define OP_SH_IMML 0 | |
310 | #define OP_MASK_IMMM 0 | |
311 | #define OP_SH_IMMM 0 | |
312 | #define OP_MASK_IMMN 0 | |
313 | #define OP_SH_IMMN 0 | |
314 | #define OP_MASK_IMMO 0 | |
315 | #define OP_SH_IMMO 0 | |
316 | #define OP_MASK_IMMP 0 | |
317 | #define OP_SH_IMMP 0 | |
318 | #define OP_MASK_IMMQ 0 | |
319 | #define OP_SH_IMMQ 0 | |
320 | #define OP_MASK_IMMU 0 | |
321 | #define OP_SH_IMMU 0 | |
322 | #define OP_MASK_IMMW 0 | |
323 | #define OP_SH_IMMW 0 | |
324 | #define OP_MASK_IMMX 0 | |
325 | #define OP_SH_IMMX 0 | |
326 | #define OP_MASK_IMMY 0 | |
327 | #define OP_SH_IMMY 0 | |
328 | ||
7f3c4072 CM |
329 | /* Enhanced VA Scheme */ |
330 | #define OP_SH_EVAOFFSET 7 | |
331 | #define OP_MASK_EVAOFFSET 0x1ff | |
332 | ||
ab902481 RS |
333 | /* Enumerates the various types of MIPS operand. */ |
334 | enum mips_operand_type { | |
335 | /* Described by mips_int_operand. */ | |
336 | OP_INT, | |
337 | ||
338 | /* Described by mips_mapped_int_operand. */ | |
339 | OP_MAPPED_INT, | |
340 | ||
341 | /* Described by mips_msb_operand. */ | |
342 | OP_MSB, | |
343 | ||
344 | /* Described by mips_reg_operand. */ | |
345 | OP_REG, | |
346 | ||
0f35dbc4 RS |
347 | /* Like OP_REG, but can be omitted if the register is the same as the |
348 | previous operand. */ | |
349 | OP_OPTIONAL_REG, | |
350 | ||
ab902481 RS |
351 | /* Described by mips_reg_pair_operand. */ |
352 | OP_REG_PAIR, | |
353 | ||
354 | /* Described by mips_pcrel_operand. */ | |
355 | OP_PCREL, | |
356 | ||
357 | /* A performance register. The field is 5 bits in size, but the supported | |
358 | values are much more restricted. */ | |
359 | OP_PERF_REG, | |
360 | ||
361 | /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts | |
362 | as a normal 9-bit signed offset that is multiplied by four, but there | |
363 | are four special cases: | |
364 | ||
365 | -2 * 4 => -258 * 4 | |
366 | -1 * 4 => -257 * 4 | |
367 | 0 * 4 => 256 * 4 | |
368 | 1 * 4 => 257 * 4. */ | |
369 | OP_ADDIUSP_INT, | |
370 | ||
371 | /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two | |
372 | 5-bit register fields, both of which must be set to the destination | |
373 | register. */ | |
374 | OP_CLO_CLZ_DEST, | |
375 | ||
376 | /* A register list for a microMIPS LWM or SWM instruction. The operand | |
377 | size determines whether the 16-bit or 32-bit encoding is required. */ | |
378 | OP_LWM_SWM_LIST, | |
379 | ||
c3c07478 RS |
380 | /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ |
381 | OP_ENTRY_EXIT_LIST, | |
382 | ||
383 | /* The register list and frame size for a MIPS16 SAVE or RESTORE | |
384 | instruction. */ | |
385 | OP_SAVE_RESTORE_LIST, | |
386 | ||
ab902481 RS |
387 | /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: |
388 | ||
389 | V Meaning | |
390 | ----- ------- | |
391 | 0EEE0 8 copies of $vN[E], OB format | |
392 | 0EE01 4 copies of $vN[E], QH format | |
393 | 10110 all 8 elements of $vN, OB format | |
394 | 10101 all 4 elements of $vN, QH format | |
395 | 11110 8 copies of immediate N, OB format | |
396 | 11101 4 copies of immediate N, QH format. */ | |
397 | OP_MDMX_IMM_REG, | |
398 | ||
399 | /* A register operand that must match the destination register. */ | |
400 | OP_REPEAT_DEST_REG, | |
401 | ||
402 | /* A register operand that must match the previous register. */ | |
403 | OP_REPEAT_PREV_REG, | |
404 | ||
405 | /* $pc, which has no encoding in the architectural instruction. */ | |
14daeee3 RS |
406 | OP_PC, |
407 | ||
408 | /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines | |
409 | which. */ | |
410 | OP_VU0_SUFFIX, | |
411 | ||
412 | /* Like OP_VU0_SUFFIX, but used when the operand's value has already | |
413 | been set. Any suffix used here must match the previous value. */ | |
387a82f1 CF |
414 | OP_VU0_MATCH_SUFFIX, |
415 | ||
416 | /* An index selected by an integer, e.g. [1]. */ | |
417 | OP_IMM_INDEX, | |
418 | ||
419 | /* An index selected by a register, e.g. [$2]. */ | |
7361da2c AB |
420 | OP_REG_INDEX, |
421 | ||
422 | /* The operand spans two 5-bit register fields, both of which must be set to | |
423 | the source register. */ | |
424 | OP_SAME_RS_RT, | |
425 | ||
426 | /* Described by mips_prev_operand. */ | |
427 | OP_CHECK_PREV, | |
428 | ||
429 | /* A register operand that must not be zero. */ | |
430 | OP_NON_ZERO_REG | |
ab902481 RS |
431 | }; |
432 | ||
433 | /* Enumerates the types of MIPS register. */ | |
434 | enum mips_reg_operand_type { | |
435 | /* General registers $0-$31. Software names like $at can also be used. */ | |
436 | OP_REG_GP, | |
437 | ||
438 | /* Floating-point registers $f0-$f31. */ | |
439 | OP_REG_FP, | |
440 | ||
441 | /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes | |
442 | can also be written $fcc0-$fcc7. */ | |
443 | OP_REG_CCC, | |
444 | ||
445 | /* FPRs used in a vector capacity. They can be written $f0-$f31 | |
446 | or $v0-$v31, although the latter form is not used for the VR5400 | |
447 | vector instructions. */ | |
448 | OP_REG_VEC, | |
449 | ||
450 | /* DSP accumulator registers $ac0-$ac3. */ | |
451 | OP_REG_ACC, | |
452 | ||
453 | /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can | |
454 | also be used in some contexts. */ | |
455 | OP_REG_COPRO, | |
456 | ||
457 | /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can | |
458 | also be used in some contexts. */ | |
14daeee3 RS |
459 | OP_REG_HW, |
460 | ||
461 | /* Floating-point registers $vf0-$vf31. */ | |
462 | OP_REG_VF, | |
463 | ||
464 | /* Integer registers $vi0-$vi31. */ | |
465 | OP_REG_VI, | |
466 | ||
467 | /* R5900 VU0 registers $I, $Q, $R and $ACC. */ | |
468 | OP_REG_R5900_I, | |
469 | OP_REG_R5900_Q, | |
470 | OP_REG_R5900_R, | |
387a82f1 CF |
471 | OP_REG_R5900_ACC, |
472 | ||
473 | /* MSA registers $w0-$w31. */ | |
474 | OP_REG_MSA, | |
475 | ||
476 | /* MSA control registers $0-$31. */ | |
477 | OP_REG_MSA_CTRL | |
ab902481 RS |
478 | }; |
479 | ||
480 | /* Base class for all operands. */ | |
481 | struct mips_operand | |
482 | { | |
483 | /* The type of the operand. */ | |
484 | enum mips_operand_type type; | |
485 | ||
486 | /* The operand occupies SIZE bits of the instruction, starting at LSB. */ | |
487 | unsigned short size; | |
488 | unsigned short lsb; | |
489 | }; | |
490 | ||
491 | /* Describes an integer operand with a regular encoding pattern. */ | |
492 | struct mips_int_operand | |
493 | { | |
494 | struct mips_operand root; | |
495 | ||
496 | /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. | |
497 | The cyclically previous field value encodes 1 << SHIFT less than that, | |
498 | and so on. E.g. | |
499 | ||
500 | - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, | |
501 | but 15 encodes -1. | |
502 | ||
503 | - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is | |
504 | shifted left two places. | |
505 | ||
506 | - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except | |
507 | that 0 encodes 8. | |
508 | ||
509 | - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ | |
510 | unsigned int max_val; | |
511 | int bias; | |
512 | unsigned int shift; | |
513 | ||
514 | /* True if the operand should be printed as hex rather than decimal. */ | |
515 | bfd_boolean print_hex; | |
516 | }; | |
517 | ||
518 | /* Uses a lookup table to describe a small integer operand. */ | |
519 | struct mips_mapped_int_operand | |
520 | { | |
521 | struct mips_operand root; | |
522 | ||
523 | /* Maps each encoding value to the integer that it represents. */ | |
524 | const int *int_map; | |
525 | ||
526 | /* True if the operand should be printed as hex rather than decimal. */ | |
527 | bfd_boolean print_hex; | |
528 | }; | |
529 | ||
530 | /* An operand that encodes the most significant bit position of a bitfield. | |
531 | Given a bitfield that spans bits [MSB, LSB], some operands of this type | |
532 | encode MSB directly while others encode MSB - LSB. Each operand of this | |
533 | type is preceded by an integer operand that specifies LSB. | |
534 | ||
535 | The assembly form varies between instructions. For some instructions, | |
536 | such as EXT, the operand is written as the bitfield size. For others, | |
537 | such as EXTS, it is written in raw MSB - LSB form. */ | |
538 | struct mips_msb_operand | |
539 | { | |
540 | struct mips_operand root; | |
541 | ||
542 | /* The assembly-level operand encoded by a field value of 0. */ | |
543 | int bias; | |
544 | ||
545 | /* True if the operand encodes MSB directly, false if it encodes | |
546 | MSB - LSB. */ | |
547 | bfd_boolean add_lsb; | |
548 | ||
549 | /* The maximum value of MSB + 1. */ | |
550 | unsigned int opsize; | |
551 | }; | |
552 | ||
553 | /* Describes a single register operand. */ | |
554 | struct mips_reg_operand | |
555 | { | |
556 | struct mips_operand root; | |
557 | ||
558 | /* The type of register. */ | |
559 | enum mips_reg_operand_type reg_type; | |
560 | ||
561 | /* If nonnull, REG_MAP[N] gives the register associated with encoding N, | |
562 | otherwise the encoding is the same as the register number. */ | |
563 | const unsigned char *reg_map; | |
564 | }; | |
565 | ||
7361da2c AB |
566 | /* Describes an operand that which must match a condition based on the |
567 | previous operand. */ | |
568 | struct mips_check_prev_operand | |
569 | { | |
570 | struct mips_operand root; | |
571 | ||
572 | bfd_boolean greater_than_ok; | |
573 | bfd_boolean less_than_ok; | |
574 | bfd_boolean equal_ok; | |
575 | bfd_boolean zero_ok; | |
576 | }; | |
577 | ||
ab902481 RS |
578 | /* Describes an operand that encodes a pair of registers. */ |
579 | struct mips_reg_pair_operand | |
580 | { | |
581 | struct mips_operand root; | |
582 | ||
583 | /* The type of register. */ | |
584 | enum mips_reg_operand_type reg_type; | |
585 | ||
586 | /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ | |
587 | unsigned char *reg1_map; | |
588 | unsigned char *reg2_map; | |
589 | }; | |
590 | ||
591 | /* Describes an operand that is calculated relative to a base PC. | |
592 | The base PC is usually the address of the following instruction, | |
593 | but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ | |
594 | struct mips_pcrel_operand | |
595 | { | |
3ccad066 RS |
596 | /* Encodes the offset. */ |
597 | struct mips_int_operand root; | |
ab902481 | 598 | |
3ccad066 RS |
599 | /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', |
600 | which is then added to the offset encoded by ROOT. */ | |
ab902481 RS |
601 | unsigned int align_log2 : 8; |
602 | ||
ab902481 RS |
603 | /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then |
604 | reinstated. This is true for jumps and branches and false for | |
605 | PC-relative data instructions. */ | |
606 | unsigned int include_isa_bit : 1; | |
607 | ||
608 | /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. | |
609 | This is true for JALX and false otherwise. */ | |
610 | unsigned int flip_isa_bit : 1; | |
611 | }; | |
612 | ||
0f35dbc4 RS |
613 | /* Return true if the assembly syntax allows OPERAND to be omitted. */ |
614 | ||
615 | static inline bfd_boolean | |
616 | mips_optional_operand_p (const struct mips_operand *operand) | |
617 | { | |
618 | return (operand->type == OP_OPTIONAL_REG | |
619 | || operand->type == OP_REPEAT_PREV_REG); | |
620 | } | |
621 | ||
ab902481 RS |
622 | /* Return a version of INSN in which the field specified by OPERAND |
623 | has value UVAL. */ | |
624 | ||
625 | static inline unsigned int | |
626 | mips_insert_operand (const struct mips_operand *operand, unsigned int insn, | |
627 | unsigned int uval) | |
628 | { | |
629 | unsigned int mask; | |
630 | ||
631 | mask = (1 << operand->size) - 1; | |
632 | insn &= ~(mask << operand->lsb); | |
633 | insn |= (uval & mask) << operand->lsb; | |
634 | return insn; | |
635 | } | |
636 | ||
637 | /* Extract OPERAND from instruction INSN. */ | |
638 | ||
639 | static inline unsigned int | |
640 | mips_extract_operand (const struct mips_operand *operand, unsigned int insn) | |
641 | { | |
642 | return (insn >> operand->lsb) & ((1 << operand->size) - 1); | |
643 | } | |
644 | ||
645 | /* UVAL is the value encoded by OPERAND. Return it in signed form. */ | |
646 | ||
647 | static inline int | |
648 | mips_signed_operand (const struct mips_operand *operand, unsigned int uval) | |
649 | { | |
650 | unsigned int sign_bit, mask; | |
651 | ||
652 | mask = (1 << operand->size) - 1; | |
653 | sign_bit = 1 << (operand->size - 1); | |
654 | return ((uval + sign_bit) & mask) - sign_bit; | |
655 | } | |
656 | ||
657 | /* Return the integer that OPERAND encodes as UVAL. */ | |
658 | ||
659 | static inline int | |
660 | mips_decode_int_operand (const struct mips_int_operand *operand, | |
661 | unsigned int uval) | |
662 | { | |
663 | uval |= (operand->max_val - uval) & -(1 << operand->root.size); | |
664 | uval += operand->bias; | |
665 | uval <<= operand->shift; | |
666 | return uval; | |
667 | } | |
668 | ||
3ccad066 RS |
669 | /* Return the maximum value that can be encoded by OPERAND. */ |
670 | ||
671 | static inline int | |
672 | mips_int_operand_max (const struct mips_int_operand *operand) | |
673 | { | |
674 | return (operand->max_val + operand->bias) << operand->shift; | |
675 | } | |
676 | ||
677 | /* Return the minimum value that can be encoded by OPERAND. */ | |
678 | ||
679 | static inline int | |
680 | mips_int_operand_min (const struct mips_int_operand *operand) | |
681 | { | |
682 | unsigned int mask; | |
683 | ||
684 | mask = (1 << operand->root.size) - 1; | |
685 | return mips_int_operand_max (operand) - (mask << operand->shift); | |
686 | } | |
687 | ||
fc76e730 RS |
688 | /* Return the register that OPERAND encodes as UVAL. */ |
689 | ||
690 | static inline int | |
691 | mips_decode_reg_operand (const struct mips_reg_operand *operand, | |
692 | unsigned int uval) | |
693 | { | |
694 | if (operand->reg_map) | |
695 | uval = operand->reg_map[uval]; | |
696 | return uval; | |
697 | } | |
698 | ||
ab902481 RS |
699 | /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. |
700 | Return the address that it encodes. */ | |
701 | ||
702 | static inline bfd_vma | |
703 | mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, | |
704 | bfd_vma base_pc, unsigned int uval) | |
705 | { | |
706 | bfd_vma addr; | |
707 | ||
708 | addr = base_pc & -(1 << operand->align_log2); | |
3ccad066 | 709 | addr += mips_decode_int_operand (&operand->root, uval); |
ab902481 RS |
710 | if (operand->include_isa_bit) |
711 | addr |= base_pc & 1; | |
712 | if (operand->flip_isa_bit) | |
713 | addr ^= 1; | |
714 | return addr; | |
715 | } | |
716 | ||
252b5132 RH |
717 | /* This structure holds information for a particular instruction. */ |
718 | ||
719 | struct mips_opcode | |
720 | { | |
721 | /* The name of the instruction. */ | |
722 | const char *name; | |
723 | /* A string describing the arguments for this instruction. */ | |
724 | const char *args; | |
725 | /* The basic opcode for the instruction. When assembling, this | |
726 | opcode is modified by the arguments to produce the actual opcode | |
727 | that is used. If pinfo is INSN_MACRO, then this is 0. */ | |
728 | unsigned long match; | |
729 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
730 | relevant portions of the opcode when disassembling. If the | |
731 | actual opcode anded with the match field equals the opcode field, | |
732 | then we have found the correct instruction. If pinfo is | |
733 | INSN_MACRO, then this field is the macro identifier. */ | |
734 | unsigned long mask; | |
735 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
736 | of bits describing the instruction, notably any relevant hazard | |
737 | information. */ | |
738 | unsigned long pinfo; | |
dc9a9f39 FF |
739 | /* A collection of additional bits describing the instruction. */ |
740 | unsigned long pinfo2; | |
252b5132 RH |
741 | /* A collection of bits describing the instruction sets of which this |
742 | instruction or macro is a member. */ | |
743 | unsigned long membership; | |
d301a56b RS |
744 | /* A collection of bits describing the ASE of which this instruction |
745 | or macro is a member. */ | |
746 | unsigned long ase; | |
35d0a169 MR |
747 | /* A collection of bits describing the instruction sets of which this |
748 | instruction or macro is not a member. */ | |
749 | unsigned long exclusions; | |
252b5132 RH |
750 | }; |
751 | ||
27abff54 | 752 | /* These are the characters which may appear in the args field of an |
252b5132 RH |
753 | instruction. They appear in the order in which the fields appear |
754 | when the instruction is used. Commas and parentheses in the args | |
755 | string are ignored when assembling, and written into the output | |
756 | when disassembling. | |
757 | ||
758 | Each of these characters corresponds to a mask field defined above. | |
759 | ||
18870af7 | 760 | "1" 5 bit sync type (OP_*_STYPE) |
252b5132 RH |
761 | "<" 5 bit shift amount (OP_*_SHAMT) |
762 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) | |
763 | "a" 26 bit target address (OP_*_TARGET) | |
27c5c572 | 764 | "+i" likewise, but flips bit 0 |
252b5132 RH |
765 | "b" 5 bit base register (OP_*_RS) |
766 | "c" 10 bit breakpoint code (OP_*_CODE) | |
767 | "d" 5 bit destination register specifier (OP_*_RD) | |
768 | "h" 5 bit prefx hint (OP_*_PREFX) | |
769 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) | |
770 | "j" 16 bit signed immediate (OP_*_DELTA) | |
771 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) | |
772 | "o" 16 bit signed offset (OP_*_DELTA) | |
773 | "p" 16 bit PC relative branch target address (OP_*_DELTA) | |
774 | "q" 10 bit extra breakpoint code (OP_*_CODE2) | |
775 | "r" 5 bit same register used as both source and target (OP_*_RS) | |
776 | "s" 5 bit source register specifier (OP_*_RS) | |
777 | "t" 5 bit target register (OP_*_RT) | |
778 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) | |
779 | "v" 5 bit same register used as both source and destination (OP_*_RS) | |
780 | "w" 5 bit same register used as both target and destination (OP_*_RT) | |
4372b673 NC |
781 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
782 | (used by clo and clz) | |
252b5132 | 783 | "C" 25 bit coprocessor function code (OP_*_COPZ) |
4372b673 NC |
784 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
785 | "J" 19 bit wait function code (OP_*_CODE19) | |
252b5132 RH |
786 | "x" accept and ignore register name |
787 | "z" must be zero register | |
af7ee8bf | 788 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
ef0ee844 | 789 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
df58fc94 RS |
790 | LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for |
791 | microMIPS compatibility). | |
071742cf | 792 | Enforces: 0 <= pos < 32. |
ef0ee844 | 793 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
5f74bc13 | 794 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 795 | Enforces: 0 < (pos+size) <= 32. |
ef0ee844 | 796 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
5f74bc13 | 797 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 798 | Enforces: 0 < (pos+size) <= 32. |
5f74bc13 CD |
799 | (Also used by "dext" w/ different limits, but limits for |
800 | that are checked by the M_DEXT macro.) | |
ef0ee844 | 801 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
5f74bc13 | 802 | Enforces: 32 <= pos < 64. |
ef0ee844 | 803 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
5f74bc13 CD |
804 | Requires that "+A" or "+E" occur first to set position. |
805 | Enforces: 32 < (pos+size) <= 64. | |
806 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). | |
807 | Requires that "+A" or "+E" occur first to set position. | |
808 | Enforces: 32 < (pos+size) <= 64. | |
809 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). | |
810 | Requires that "+A" or "+E" occur first to set position. | |
811 | Enforces: 32 < (pos+size) <= 64. | |
252b5132 RH |
812 | |
813 | Floating point instructions: | |
814 | "D" 5 bit destination register (OP_*_FD) | |
815 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) | |
816 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) | |
817 | "S" 5 bit fs source 1 register (OP_*_FS) | |
818 | "T" 5 bit ft source 2 register (OP_*_FT) | |
819 | "R" 5 bit fr source 3 register (OP_*_FR) | |
820 | "V" 5 bit same register used as floating source and destination (OP_*_FS) | |
821 | "W" 5 bit same register used as floating target and destination (OP_*_FT) | |
822 | ||
823 | Coprocessor instructions: | |
824 | "E" 5 bit target register (OP_*_RT) | |
825 | "G" 5 bit destination register (OP_*_RD) | |
8ff529d8 | 826 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
252b5132 | 827 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
9752cf1b RS |
828 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
829 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) | |
252b5132 RH |
830 | |
831 | Macro instructions: | |
832 | "A" General 32 bit expression | |
5f74bc13 | 833 | "I" 32 bit immediate (value placed in imm_expr). |
252b5132 RH |
834 | "F" 64 bit floating point constant in .rdata |
835 | "L" 64 bit floating point constant in .lit8 | |
836 | "f" 32 bit floating point constant | |
837 | "l" 32 bit floating point constant in .lit4 | |
838 | ||
5c324c16 RS |
839 | MDMX and VR5400 instruction operands (note that while these use the |
840 | FP register fields, the MDMX instructions accept both $fN and $vN names | |
841 | for the registers): | |
842 | "O" alignment offset (OP_*_ALN) | |
843 | "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) | |
844 | "X" destination register (OP_*_FD) | |
845 | "Y" source register (OP_*_FS) | |
846 | "Z" source register (OP_*_FT) | |
deec1734 | 847 | |
14daeee3 RS |
848 | R5900 VU0 Macromode instructions: |
849 | "+5" 5 bit floating point register (FD) | |
850 | "+6" 5 bit floating point register (FS) | |
851 | "+7" 5 bit floating point register (FT) | |
852 | "+8" 5 bit integer register (FD) | |
853 | "+9" 5 bit integer register (FS) | |
854 | "+0" 5 bit integer register (FT) | |
855 | "+K" match an existing 4-bit channel mask starting at bit 21 | |
856 | "+L" 2-bit channel index starting at bit 21 | |
857 | "+M" 2-bit channel index starting at bit 23 | |
858 | "+N" match an existing 2-bit channel index starting at bit 0 | |
859 | "+f" 15 bit immediate for VCALLMS | |
860 | "+g" 5 bit signed immediate for VIADDI | |
861 | "+m" $ACC register (syntax only) | |
862 | "+q" $Q register (syntax only) | |
863 | "+r" $R register (syntax only) | |
864 | "+y" $I register (syntax only) | |
865 | "#+" "++" decorator in ($reg++) sequence | |
866 | "#-" "--" decorator in (--$reg) sequence | |
867 | ||
93c34b9b | 868 | DSP ASE usage: |
8b082fb1 | 869 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) |
93c34b9b CF |
870 | "3" 3 bit unsigned immediate (OP_*_SA3) |
871 | "4" 4 bit unsigned immediate (OP_*_SA4) | |
872 | "5" 8 bit unsigned immediate (OP_*_IMM8) | |
873 | "6" 5 bit unsigned immediate (OP_*_RS) | |
874 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) | |
875 | "8" 6 bit unsigned immediate (OP_*_WRDSP) | |
876 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) | |
877 | "0" 6 bit signed immediate (OP_*_DSPSFT) | |
878 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) | |
879 | "'" 6 bit unsigned immediate (OP_*_RDDSP) | |
880 | "@" 10 bit signed immediate (OP_*_IMM10) | |
881 | ||
089b39de | 882 | MT ASE usage: |
a9e24354 TS |
883 | "!" 1 bit usermode flag (OP_*_MT_U) |
884 | "$" 1 bit load high flag (OP_*_MT_H) | |
089b39de CF |
885 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
886 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) | |
887 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) | |
888 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) | |
089b39de | 889 | |
dec0624d MR |
890 | MCU ASE usage: |
891 | "~" 12 bit offset (OP_*_OFFSET12) | |
892 | "\" 3 bit position for aset and aclr (OP_*_3BITPOS) | |
893 | ||
b015e599 AP |
894 | VIRT ASE usage: |
895 | "+J" 10-bit hypcall code (OP_*CODE10) | |
896 | ||
9bcd4f99 TS |
897 | UDI immediates: |
898 | "+1" UDI immediate bits 6-10 | |
899 | "+2" UDI immediate bits 6-15 | |
900 | "+3" UDI immediate bits 6-20 | |
901 | "+4" UDI immediate bits 6-25 | |
902 | ||
bb35fb24 NC |
903 | Octeon: |
904 | "+x" Bit index field of bbit. Enforces: 0 <= index < 32. | |
905 | "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, | |
906 | otherwise skips to next candidate. | |
907 | "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. | |
908 | "+P" Position field of cins/exts aliasing cins32/exts32. Matches if | |
909 | 32 <= pos < 64, otherwise skips to next candidate. | |
dd3cbb7e | 910 | "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. |
23e69e47 RS |
911 | "+s" Length-minus-one field of cins32/exts32. Requires msb position |
912 | of the field to be <= 31. | |
913 | "+S" Length-minus-one field of cins/exts. Requires msb position | |
914 | of the field to be <= 63. | |
bb35fb24 | 915 | |
1bec78e9 RS |
916 | Loongson-3A: |
917 | "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) | |
918 | "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) | |
919 | "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) | |
920 | "+z" 5-bit rz register (OP_*_RZ) | |
921 | "+Z" 5-bit fz register (OP_*_FZ) | |
922 | ||
7f3c4072 CM |
923 | Enhanced VA Scheme: |
924 | "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) | |
925 | ||
387a82f1 CF |
926 | MSA Extension: |
927 | "+d" 5-bit MSA register (FD) | |
928 | "+e" 5-bit MSA register (FS) | |
929 | "+h" 5-bit MSA register (FT) | |
930 | "+k" 5-bit GPR at bit 6 | |
931 | "+l" 5-bit MSA control register at bit 6 | |
932 | "+n" 5-bit MSA control register at bit 11 | |
e269fea7 AB |
933 | "+o" 4-bit vector element index at bit 16 |
934 | "+u" 3-bit vector element index at bit 16 | |
935 | "+v" 2-bit vector element index at bit 16 | |
936 | "+w" 1-bit vector element index at bit 16 | |
387a82f1 CF |
937 | "+T" (-512 .. 511) << 0 at bit 16 |
938 | "+U" (-512 .. 511) << 1 at bit 16 | |
939 | "+V" (-512 .. 511) << 2 at bit 16 | |
940 | "+W" (-512 .. 511) << 3 at bit 16 | |
941 | "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 | |
942 | "+!" 3 bit unsigned bit position at bit 16 | |
943 | "+@" 4 bit unsigned bit position at bit 16 | |
944 | "+#" 6 bit unsigned bit position at bit 16 | |
945 | "+$" 5 bit unsigned immediate at bit 16 | |
946 | "+%" 5 bit signed immediate at bit 16 | |
947 | "+^" 10 bit signed immediate at bit 11 | |
948 | "+&" 0 vector element index | |
949 | "+*" 5-bit register vector element index at bit 16 | |
950 | "+|" 8-bit mask at bit 16 | |
951 | ||
7361da2c AB |
952 | MIPS R6: |
953 | "+:" 11-bit mask at bit 0 | |
954 | "+'" 26 bit PC relative branch target address | |
955 | "+"" 21 bit PC relative branch target address | |
956 | "+;" 5 bit same register in both OP_*_RS and OP_*_RT | |
957 | "+I" 2bit unsigned bit position at bit 6 | |
958 | "+O" 3bit unsigned bit position at bit 6 | |
959 | "+R" must be program counter | |
960 | "-a" (-262144 .. 262143) << 2 at bit 0 | |
961 | "-b" (-131072 .. 131071) << 3 at bit 0 | |
962 | "-d" Same as destination register GP | |
963 | "-s" 5 bit source register specifier (OP_*_RS) not $0 | |
964 | "-t" 5 bit source register specifier (OP_*_RT) not $0 | |
965 | "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS | |
966 | "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS | |
967 | "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS | |
968 | "-x" 5 bit source register specifier (OP_*_RT) greater than or | |
969 | equal to OP_*_RS | |
970 | "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS | |
971 | "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 | |
972 | "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 | |
973 | ||
252b5132 RH |
974 | Other: |
975 | "()" parens surrounding optional value | |
976 | "," separates operands | |
af7ee8bf | 977 | "+" Start of extension sequence. |
252b5132 RH |
978 | |
979 | Characters used so far, for quick reference when adding more: | |
de9a3e51 | 980 | "1234567890" |
7361da2c | 981 | "%[]<>(),+-:'@!#$*&\~" |
af7ee8bf | 982 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
089b39de | 983 | "abcdefghijklopqrstuvwxz" |
af7ee8bf CD |
984 | |
985 | Extension character sequences used so far ("+" followed by the | |
986 | following), for quick reference when adding more: | |
14daeee3 | 987 | "1234567890" |
7361da2c AB |
988 | "~!@#$%^&*|:'";" |
989 | "ABCEFGHIJKLMNOPQRSTUVWXZ" | |
387a82f1 | 990 | "abcdefghijklmnopqrstuvwxyz" |
7361da2c AB |
991 | |
992 | Extension character sequences used so far ("-" followed by the | |
993 | following), for quick reference when adding more: | |
994 | "AB" | |
995 | "abdstuvwxy" | |
252b5132 RH |
996 | */ |
997 | ||
998 | /* These are the bits which may be set in the pinfo field of an | |
999 | instructions, if it is not equal to INSN_MACRO. */ | |
1000 | ||
fc76e730 RS |
1001 | /* Writes to operand number N. */ |
1002 | #define INSN_WRITE_SHIFT 0 | |
1003 | #define INSN_WRITE_1 0x00000001 | |
1004 | #define INSN_WRITE_2 0x00000002 | |
1005 | #define INSN_WRITE_ALL 0x00000003 | |
1006 | /* Reads from operand number N. */ | |
1007 | #define INSN_READ_SHIFT 2 | |
1008 | #define INSN_READ_1 0x00000004 | |
1009 | #define INSN_READ_2 0x00000008 | |
1010 | #define INSN_READ_3 0x00000010 | |
1011 | #define INSN_READ_4 0x00000020 | |
1012 | #define INSN_READ_ALL 0x0000003c | |
252b5132 | 1013 | /* Modifies general purpose register 31. */ |
fc76e730 | 1014 | #define INSN_WRITE_GPR_31 0x00000040 |
252b5132 | 1015 | /* Modifies coprocessor condition code. */ |
fc76e730 | 1016 | #define INSN_WRITE_COND_CODE 0x00000080 |
252b5132 | 1017 | /* Reads coprocessor condition code. */ |
fc76e730 | 1018 | #define INSN_READ_COND_CODE 0x00000100 |
252b5132 | 1019 | /* TLB operation. */ |
fc76e730 | 1020 | #define INSN_TLB 0x00000200 |
252b5132 | 1021 | /* Reads coprocessor register other than floating point register. */ |
fc76e730 | 1022 | #define INSN_COP 0x00000400 |
67dc82bc CM |
1023 | /* Instruction loads value from memory. */ |
1024 | #define INSN_LOAD_MEMORY 0x00000800 | |
43885403 MF |
1025 | /* Instruction loads value from coprocessor, (may require delay). */ |
1026 | #define INSN_LOAD_COPROC 0x00001000 | |
252b5132 | 1027 | /* Instruction has unconditional branch delay slot. */ |
fc76e730 | 1028 | #define INSN_UNCOND_BRANCH_DELAY 0x00002000 |
252b5132 | 1029 | /* Instruction has conditional branch delay slot. */ |
fc76e730 | 1030 | #define INSN_COND_BRANCH_DELAY 0x00004000 |
252b5132 | 1031 | /* Conditional branch likely: if branch not taken, insn nullified. */ |
fc76e730 | 1032 | #define INSN_COND_BRANCH_LIKELY 0x00008000 |
43885403 MF |
1033 | /* Moves to coprocessor register, (may require delay). */ |
1034 | #define INSN_COPROC_MOVE 0x00010000 | |
252b5132 | 1035 | /* Loads coprocessor register from memory, requiring delay. */ |
fc76e730 | 1036 | #define INSN_COPROC_MEMORY_DELAY 0x00020000 |
252b5132 | 1037 | /* Reads the HI register. */ |
fc76e730 | 1038 | #define INSN_READ_HI 0x00040000 |
252b5132 | 1039 | /* Reads the LO register. */ |
fc76e730 | 1040 | #define INSN_READ_LO 0x00080000 |
252b5132 | 1041 | /* Modifies the HI register. */ |
fc76e730 | 1042 | #define INSN_WRITE_HI 0x00100000 |
252b5132 | 1043 | /* Modifies the LO register. */ |
fc76e730 | 1044 | #define INSN_WRITE_LO 0x00200000 |
bcd530a7 RS |
1045 | /* Not to be placed in a branch delay slot, either architecturally |
1046 | or for ease of handling (such as with instructions that take a trap). */ | |
fc76e730 | 1047 | #define INSN_NO_DELAY_SLOT 0x00400000 |
252b5132 | 1048 | /* Instruction stores value into memory. */ |
fc76e730 | 1049 | #define INSN_STORE_MEMORY 0x00800000 |
252b5132 | 1050 | /* Instruction uses single precision floating point. */ |
fc76e730 | 1051 | #define FP_S 0x01000000 |
252b5132 | 1052 | /* Instruction uses double precision floating point. */ |
fc76e730 | 1053 | #define FP_D 0x02000000 |
252b5132 | 1054 | /* Instruction is part of the tx39's integer multiply family. */ |
fc76e730 RS |
1055 | #define INSN_MULT 0x04000000 |
1056 | /* Reads general purpose register 24. */ | |
1057 | #define INSN_READ_GPR_24 0x08000000 | |
1058 | /* Writes to general purpose register 24. */ | |
1059 | #define INSN_WRITE_GPR_24 0x10000000 | |
1060 | /* A user-defined instruction. */ | |
1061 | #define INSN_UDI 0x20000000 | |
d0799671 AN |
1062 | /* Instruction is actually a macro. It should be ignored by the |
1063 | disassembler, and requires special treatment by the assembler. */ | |
1064 | #define INSN_MACRO 0xffffffff | |
dc9a9f39 FF |
1065 | |
1066 | /* These are the bits which may be set in the pinfo2 field of an | |
1067 | instruction. */ | |
1068 | ||
1069 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ | |
239cb185 | 1070 | #define INSN2_ALIAS 0x00000001 |
dc9a9f39 | 1071 | /* Instruction reads MDMX accumulator. */ |
239cb185 | 1072 | #define INSN2_READ_MDMX_ACC 0x00000002 |
dc9a9f39 | 1073 | /* Instruction writes MDMX accumulator. */ |
239cb185 | 1074 | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
d0799671 AN |
1075 | /* Macro uses single-precision floating-point instructions. This should |
1076 | only be set for macros. For instructions, FP_S in pinfo carries the | |
1077 | same information. */ | |
1078 | #define INSN2_M_FP_S 0x00000008 | |
1079 | /* Macro uses double-precision floating-point instructions. This should | |
1080 | only be set for macros. For instructions, FP_D in pinfo carries the | |
1081 | same information. */ | |
1082 | #define INSN2_M_FP_D 0x00000010 | |
df58fc94 | 1083 | /* Instruction has a branch delay slot that requires a 16-bit instruction. */ |
fc76e730 | 1084 | #define INSN2_BRANCH_DELAY_16BIT 0x00000020 |
df58fc94 | 1085 | /* Instruction has a branch delay slot that requires a 32-bit instruction. */ |
fc76e730 RS |
1086 | #define INSN2_BRANCH_DELAY_32BIT 0x00000040 |
1087 | /* Writes to the stack pointer ($29). */ | |
1088 | #define INSN2_WRITE_SP 0x00000080 | |
1089 | /* Reads from the stack pointer ($29). */ | |
1090 | #define INSN2_READ_SP 0x00000100 | |
df58fc94 | 1091 | /* Reads the RA ($31) register. */ |
fc76e730 | 1092 | #define INSN2_READ_GPR_31 0x00000200 |
df58fc94 | 1093 | /* Reads the program counter ($pc). */ |
fc76e730 | 1094 | #define INSN2_READ_PC 0x00000400 |
df58fc94 | 1095 | /* Is an unconditional branch insn. */ |
fc76e730 | 1096 | #define INSN2_UNCOND_BRANCH 0x00000800 |
df58fc94 | 1097 | /* Is a conditional branch insn. */ |
fc76e730 RS |
1098 | #define INSN2_COND_BRANCH 0x00001000 |
1099 | /* Reads from $16. This is true of the MIPS16 0x6500 nop. */ | |
1100 | #define INSN2_READ_GPR_16 0x00002000 | |
14daeee3 RS |
1101 | /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ |
1102 | #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 | |
7361da2c AB |
1103 | /* Instruction has a forbidden slot. */ |
1104 | #define INSN2_FORBIDDEN_SLOT 0x00008000 | |
df58fc94 | 1105 | |
e7af610e | 1106 | /* Masks used to mark instructions to indicate which MIPS ISA level |
56950294 MS |
1107 | they were introduced in. INSN_ISA_MASK masks an enumeration that |
1108 | specifies the base ISA level(s). The remainder of a 32-bit | |
1109 | word constructed using these macros is a bitmask of the remaining | |
1110 | INSN_* values below. */ | |
1111 | ||
ae52f483 | 1112 | #define INSN_ISA_MASK 0x0000001ful |
56950294 MS |
1113 | |
1114 | /* We cannot start at zero due to ISA_UNKNOWN below. */ | |
1115 | #define INSN_ISA1 1 | |
1116 | #define INSN_ISA2 2 | |
1117 | #define INSN_ISA3 3 | |
1118 | #define INSN_ISA4 4 | |
1119 | #define INSN_ISA5 5 | |
1120 | #define INSN_ISA32 6 | |
1121 | #define INSN_ISA32R2 7 | |
ae52f483 AB |
1122 | #define INSN_ISA32R3 8 |
1123 | #define INSN_ISA32R5 9 | |
7361da2c | 1124 | #define INSN_ISA32R6 10 |
ae52f483 AB |
1125 | #define INSN_ISA64 11 |
1126 | #define INSN_ISA64R2 12 | |
1127 | #define INSN_ISA64R3 13 | |
1128 | #define INSN_ISA64R5 14 | |
7361da2c | 1129 | #define INSN_ISA64R6 15 |
56950294 MS |
1130 | /* Below this point the INSN_* values correspond to combinations of ISAs. |
1131 | They are only for use in the opcodes table to indicate membership of | |
1132 | a combination of ISAs that cannot be expressed using the usual inclusion | |
1133 | ordering on the above INSN_* values. */ | |
ae52f483 AB |
1134 | #define INSN_ISA3_32 16 |
1135 | #define INSN_ISA3_32R2 17 | |
1136 | #define INSN_ISA4_32 18 | |
1137 | #define INSN_ISA4_32R2 19 | |
1138 | #define INSN_ISA5_32R2 20 | |
56950294 | 1139 | |
7361da2c AB |
1140 | /* The R6 definitions shown below state that they support all previous ISAs. |
1141 | This is not actually true as some instructions are removed in R6. | |
1142 | The problem is that the removed instructions in R6 come from different | |
1143 | ISAs. One approach to solve this would be to describe in the membership | |
1144 | field of the opcode table the different ISAs an instruction belongs to. | |
1145 | This would require us to create a large amount of different ISA | |
1146 | combinations which is hard to manage. A cleaner approach (which is | |
1147 | implemented here) is to say that R6 is an extension of R5 and then to | |
1148 | deal with the removed instructions by adding instruction exclusions | |
1149 | for R6 in the opcode table. */ | |
1150 | ||
3efe9ec5 | 1151 | /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ |
7361da2c | 1152 | |
3efe9ec5 RS |
1153 | #define ISAF(X) (1 << (INSN_ISA##X - 1)) |
1154 | #define INSN_UPTO1 ISAF(1) | |
1155 | #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) | |
1156 | #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) | |
1157 | #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) | |
1158 | #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) | |
1159 | #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) | |
1160 | #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ | |
1161 | | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) | |
ae52f483 AB |
1162 | #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) |
1163 | #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) | |
7361da2c | 1164 | #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) |
3efe9ec5 RS |
1165 | #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) |
1166 | #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) | |
ae52f483 AB |
1167 | #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) |
1168 | #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) | |
7361da2c | 1169 | #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) |
3efe9ec5 RS |
1170 | |
1171 | /* The same information in table form: bit INSN_ISA<X> - 1 of index | |
1172 | INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ | |
1173 | static const unsigned int mips_isa_table[] = { | |
1174 | INSN_UPTO1, | |
1175 | INSN_UPTO2, | |
1176 | INSN_UPTO3, | |
1177 | INSN_UPTO4, | |
1178 | INSN_UPTO5, | |
1179 | INSN_UPTO32, | |
1180 | INSN_UPTO32R2, | |
ae52f483 AB |
1181 | INSN_UPTO32R3, |
1182 | INSN_UPTO32R5, | |
7361da2c | 1183 | INSN_UPTO32R6, |
3efe9ec5 | 1184 | INSN_UPTO64, |
ae52f483 AB |
1185 | INSN_UPTO64R2, |
1186 | INSN_UPTO64R3, | |
7361da2c AB |
1187 | INSN_UPTO64R5, |
1188 | INSN_UPTO64R6 | |
3efe9ec5 RS |
1189 | }; |
1190 | #undef ISAF | |
252b5132 | 1191 | |
e6429699 | 1192 | /* Masks used for Chip specific instructions. */ |
432233b3 | 1193 | #define INSN_CHIP_MASK 0xc3ff0f20 |
e6429699 AN |
1194 | |
1195 | /* Cavium Networks Octeon instructions. */ | |
1196 | #define INSN_OCTEON 0x00000800 | |
dd6a37e7 | 1197 | #define INSN_OCTEONP 0x00000200 |
432233b3 | 1198 | #define INSN_OCTEON2 0x00000100 |
2c629856 | 1199 | #define INSN_OCTEON3 0x00000040 |
e6429699 | 1200 | |
e407c74b NC |
1201 | /* MIPS R5900 instruction */ |
1202 | #define INSN_5900 0x00004000 | |
f79e2745 | 1203 | |
252b5132 | 1204 | /* MIPS R4650 instruction. */ |
e7af610e | 1205 | #define INSN_4650 0x00010000 |
252b5132 | 1206 | /* LSI R4010 instruction. */ |
e7af610e NC |
1207 | #define INSN_4010 0x00020000 |
1208 | /* NEC VR4100 instruction. */ | |
bf40d919 | 1209 | #define INSN_4100 0x00040000 |
252b5132 | 1210 | /* Toshiba R3900 instruction. */ |
bf40d919 | 1211 | #define INSN_3900 0x00080000 |
99c14723 TS |
1212 | /* MIPS R10000 instruction. */ |
1213 | #define INSN_10000 0x00100000 | |
2228315b CD |
1214 | /* Broadcom SB-1 instruction. */ |
1215 | #define INSN_SB1 0x00200000 | |
9752cf1b RS |
1216 | /* NEC VR4111/VR4181 instruction. */ |
1217 | #define INSN_4111 0x00400000 | |
1218 | /* NEC VR4120 instruction. */ | |
1219 | #define INSN_4120 0x00800000 | |
1220 | /* NEC VR5400 instruction. */ | |
1221 | #define INSN_5400 0x01000000 | |
1222 | /* NEC VR5500 instruction. */ | |
1223 | #define INSN_5500 0x02000000 | |
39a7806d | 1224 | |
350cc38d MS |
1225 | /* ST Microelectronics Loongson 2E. */ |
1226 | #define INSN_LOONGSON_2E 0x40000000 | |
1227 | /* ST Microelectronics Loongson 2F. */ | |
435b94a4 | 1228 | #define INSN_LOONGSON_2F 0x80000000 |
fd503541 | 1229 | /* Loongson 3A. */ |
435b94a4 | 1230 | #define INSN_LOONGSON_3A 0x00000400 |
52b6b6b9 | 1231 | /* RMI Xlr instruction */ |
d301a56b | 1232 | #define INSN_XLR 0x00000020 |
39a7806d | 1233 | |
d301a56b RS |
1234 | /* DSP ASE */ |
1235 | #define ASE_DSP 0x00000001 | |
1236 | #define ASE_DSP64 0x00000002 | |
1237 | /* DSP R2 ASE */ | |
1238 | #define ASE_DSPR2 0x00000004 | |
7f3c4072 CM |
1239 | /* Enhanced VA Scheme */ |
1240 | #define ASE_EVA 0x00000008 | |
dec0624d | 1241 | /* MCU (MicroController) ASE */ |
d301a56b RS |
1242 | #define ASE_MCU 0x00000010 |
1243 | /* MDMX ASE */ | |
1244 | #define ASE_MDMX 0x00000020 | |
1245 | /* MIPS-3D ASE */ | |
1246 | #define ASE_MIPS3D 0x00000040 | |
1247 | /* MT ASE */ | |
1248 | #define ASE_MT 0x00000080 | |
1249 | /* SmartMIPS ASE */ | |
1250 | #define ASE_SMARTMIPS 0x00000100 | |
1251 | /* Virtualization ASE */ | |
1252 | #define ASE_VIRT 0x00000200 | |
1253 | #define ASE_VIRT64 0x00000400 | |
387a82f1 CF |
1254 | /* MSA Extension */ |
1255 | #define ASE_MSA 0x00000800 | |
1256 | #define ASE_MSA64 0x00001000 | |
7d64c587 AB |
1257 | /* eXtended Physical Address (XPA) Extension. */ |
1258 | #define ASE_XPA 0x00002000 | |
dec0624d | 1259 | |
e7af610e NC |
1260 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
1261 | ||
1262 | #define ISA_UNKNOWN 0 /* Gas internal use. */ | |
56950294 MS |
1263 | #define ISA_MIPS1 INSN_ISA1 |
1264 | #define ISA_MIPS2 INSN_ISA2 | |
1265 | #define ISA_MIPS3 INSN_ISA3 | |
1266 | #define ISA_MIPS4 INSN_ISA4 | |
1267 | #define ISA_MIPS5 INSN_ISA5 | |
af7ee8bf | 1268 | |
56950294 MS |
1269 | #define ISA_MIPS32 INSN_ISA32 |
1270 | #define ISA_MIPS64 INSN_ISA64 | |
367c01af | 1271 | |
56950294 | 1272 | #define ISA_MIPS32R2 INSN_ISA32R2 |
ae52f483 AB |
1273 | #define ISA_MIPS32R3 INSN_ISA32R3 |
1274 | #define ISA_MIPS32R5 INSN_ISA32R5 | |
56950294 | 1275 | #define ISA_MIPS64R2 INSN_ISA64R2 |
ae52f483 AB |
1276 | #define ISA_MIPS64R3 INSN_ISA64R3 |
1277 | #define ISA_MIPS64R5 INSN_ISA64R5 | |
5f74bc13 | 1278 | |
7361da2c AB |
1279 | #define ISA_MIPS32R6 INSN_ISA32R6 |
1280 | #define ISA_MIPS64R6 INSN_ISA64R6 | |
af7ee8bf | 1281 | |
156c2f8b NC |
1282 | /* CPU defines, use instead of hardcoding processor number. Keep this |
1283 | in sync with bfd/archures.c in order for machine selection to work. */ | |
e7af610e | 1284 | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
156c2f8b NC |
1285 | #define CPU_R3000 3000 |
1286 | #define CPU_R3900 3900 | |
1287 | #define CPU_R4000 4000 | |
1288 | #define CPU_R4010 4010 | |
1289 | #define CPU_VR4100 4100 | |
1290 | #define CPU_R4111 4111 | |
9752cf1b | 1291 | #define CPU_VR4120 4120 |
156c2f8b NC |
1292 | #define CPU_R4300 4300 |
1293 | #define CPU_R4400 4400 | |
1294 | #define CPU_R4600 4600 | |
1295 | #define CPU_R4650 4650 | |
1296 | #define CPU_R5000 5000 | |
9752cf1b RS |
1297 | #define CPU_VR5400 5400 |
1298 | #define CPU_VR5500 5500 | |
e407c74b | 1299 | #define CPU_R5900 5900 |
156c2f8b | 1300 | #define CPU_R6000 6000 |
5a7ea749 | 1301 | #define CPU_RM7000 7000 |
156c2f8b | 1302 | #define CPU_R8000 8000 |
98e7aba8 | 1303 | #define CPU_RM9000 9000 |
156c2f8b | 1304 | #define CPU_R10000 10000 |
d1cf510e | 1305 | #define CPU_R12000 12000 |
3aa3176b TS |
1306 | #define CPU_R14000 14000 |
1307 | #define CPU_R16000 16000 | |
156c2f8b NC |
1308 | #define CPU_MIPS16 16 |
1309 | #define CPU_MIPS32 32 | |
af7ee8bf | 1310 | #define CPU_MIPS32R2 33 |
ae52f483 AB |
1311 | #define CPU_MIPS32R3 34 |
1312 | #define CPU_MIPS32R5 36 | |
7361da2c | 1313 | #define CPU_MIPS32R6 37 |
84ea6cf2 NC |
1314 | #define CPU_MIPS5 5 |
1315 | #define CPU_MIPS64 64 | |
5f74bc13 | 1316 | #define CPU_MIPS64R2 65 |
ae52f483 AB |
1317 | #define CPU_MIPS64R3 66 |
1318 | #define CPU_MIPS64R5 68 | |
7361da2c | 1319 | #define CPU_MIPS64R6 69 |
c6c98b38 | 1320 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
350cc38d MS |
1321 | #define CPU_LOONGSON_2E 3001 |
1322 | #define CPU_LOONGSON_2F 3002 | |
fd503541 | 1323 | #define CPU_LOONGSON_3A 3003 |
e6429699 | 1324 | #define CPU_OCTEON 6501 |
dd6a37e7 | 1325 | #define CPU_OCTEONP 6601 |
432233b3 | 1326 | #define CPU_OCTEON2 6502 |
2c629856 | 1327 | #define CPU_OCTEON3 6503 |
52b6b6b9 | 1328 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
156c2f8b | 1329 | |
35d0a169 MR |
1330 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
1331 | ||
1332 | static inline bfd_boolean | |
1333 | cpu_is_member (int cpu, unsigned int mask) | |
1334 | { | |
1335 | switch (cpu) | |
1336 | { | |
1337 | case CPU_R4650: | |
1338 | case CPU_RM7000: | |
1339 | case CPU_RM9000: | |
1340 | return (mask & INSN_4650) != 0; | |
1341 | ||
1342 | case CPU_R4010: | |
1343 | return (mask & INSN_4010) != 0; | |
1344 | ||
1345 | case CPU_VR4100: | |
1346 | return (mask & INSN_4100) != 0; | |
1347 | ||
1348 | case CPU_R3900: | |
1349 | return (mask & INSN_3900) != 0; | |
1350 | ||
1351 | case CPU_R10000: | |
1352 | case CPU_R12000: | |
1353 | case CPU_R14000: | |
1354 | case CPU_R16000: | |
1355 | return (mask & INSN_10000) != 0; | |
1356 | ||
1357 | case CPU_SB1: | |
1358 | return (mask & INSN_SB1) != 0; | |
1359 | ||
1360 | case CPU_R4111: | |
1361 | return (mask & INSN_4111) != 0; | |
1362 | ||
1363 | case CPU_VR4120: | |
1364 | return (mask & INSN_4120) != 0; | |
1365 | ||
1366 | case CPU_VR5400: | |
1367 | return (mask & INSN_5400) != 0; | |
1368 | ||
1369 | case CPU_VR5500: | |
1370 | return (mask & INSN_5500) != 0; | |
1371 | ||
e407c74b NC |
1372 | case CPU_R5900: |
1373 | return (mask & INSN_5900) != 0; | |
1374 | ||
35d0a169 MR |
1375 | case CPU_LOONGSON_2E: |
1376 | return (mask & INSN_LOONGSON_2E) != 0; | |
1377 | ||
1378 | case CPU_LOONGSON_2F: | |
1379 | return (mask & INSN_LOONGSON_2F) != 0; | |
1380 | ||
1381 | case CPU_LOONGSON_3A: | |
1382 | return (mask & INSN_LOONGSON_3A) != 0; | |
1383 | ||
1384 | case CPU_OCTEON: | |
1385 | return (mask & INSN_OCTEON) != 0; | |
1386 | ||
1387 | case CPU_OCTEONP: | |
1388 | return (mask & INSN_OCTEONP) != 0; | |
1389 | ||
1390 | case CPU_OCTEON2: | |
1391 | return (mask & INSN_OCTEON2) != 0; | |
1392 | ||
2c629856 N |
1393 | case CPU_OCTEON3: |
1394 | return (mask & INSN_OCTEON3) != 0; | |
1395 | ||
35d0a169 MR |
1396 | case CPU_XLR: |
1397 | return (mask & INSN_XLR) != 0; | |
1398 | ||
7361da2c AB |
1399 | case CPU_MIPS32R6: |
1400 | return (mask & INSN_ISA_MASK) == INSN_ISA32R6; | |
1401 | ||
1402 | case CPU_MIPS64R6: | |
1403 | return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) | |
1404 | || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); | |
1405 | ||
35d0a169 MR |
1406 | default: |
1407 | return FALSE; | |
1408 | } | |
1409 | } | |
1410 | ||
1f25f5d3 CD |
1411 | /* Test for membership in an ISA including chip specific ISAs. INSN |
1412 | is pointer to an element of the opcode table; ISA is the specified | |
1413 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to | |
35d0a169 MR |
1414 | test, or zero if no CPU specific ISA test is desired. Return true |
1415 | if instruction INSN is available to the given ISA and CPU. */ | |
1416 | ||
1417 | static inline bfd_boolean | |
d301a56b | 1418 | opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) |
35d0a169 MR |
1419 | { |
1420 | if (!cpu_is_member (cpu, insn->exclusions)) | |
1421 | { | |
1422 | /* Test for ISA level compatibility. */ | |
1423 | if ((isa & INSN_ISA_MASK) != 0 | |
1424 | && (insn->membership & INSN_ISA_MASK) != 0 | |
1425 | && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] | |
1426 | >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) | |
1427 | return TRUE; | |
1428 | ||
1429 | /* Test for ASE compatibility. */ | |
d301a56b | 1430 | if ((ase & insn->ase) != 0) |
35d0a169 MR |
1431 | return TRUE; |
1432 | ||
1433 | /* Test for processor-specific extensions. */ | |
1434 | if (cpu_is_member (cpu, insn->membership)) | |
1435 | return TRUE; | |
1436 | } | |
1437 | return FALSE; | |
1438 | } | |
252b5132 RH |
1439 | |
1440 | /* This is a list of macro expanded instructions. | |
8eaec934 | 1441 | |
e7af610e | 1442 | _I appended means immediate |
f2ae14a1 RS |
1443 | _A appended means target address of a jump |
1444 | _AB appended means address with (possibly zero) base register | |
e7af610e NC |
1445 | _D appended means 64 bit floating point constant |
1446 | _S appended means 32 bit floating point constant. */ | |
1447 | ||
1448 | enum | |
1449 | { | |
1450 | M_ABS, | |
dec0624d | 1451 | M_ACLR_AB, |
e7af610e NC |
1452 | M_ADD_I, |
1453 | M_ADDU_I, | |
1454 | M_AND_I, | |
dec0624d | 1455 | M_ASET_AB, |
8b082fb1 | 1456 | M_BALIGN, |
df58fc94 RS |
1457 | M_BC1FL, |
1458 | M_BC1TL, | |
1459 | M_BC2FL, | |
1460 | M_BC2TL, | |
e7af610e NC |
1461 | M_BEQ, |
1462 | M_BEQ_I, | |
df58fc94 | 1463 | M_BEQL, |
e7af610e NC |
1464 | M_BEQL_I, |
1465 | M_BGE, | |
1466 | M_BGEL, | |
1467 | M_BGE_I, | |
1468 | M_BGEL_I, | |
1469 | M_BGEU, | |
1470 | M_BGEUL, | |
1471 | M_BGEU_I, | |
1472 | M_BGEUL_I, | |
df58fc94 RS |
1473 | M_BGEZ, |
1474 | M_BGEZL, | |
1475 | M_BGEZALL, | |
e7af610e NC |
1476 | M_BGT, |
1477 | M_BGTL, | |
1478 | M_BGT_I, | |
1479 | M_BGTL_I, | |
1480 | M_BGTU, | |
1481 | M_BGTUL, | |
1482 | M_BGTU_I, | |
1483 | M_BGTUL_I, | |
df58fc94 RS |
1484 | M_BGTZ, |
1485 | M_BGTZL, | |
e7af610e NC |
1486 | M_BLE, |
1487 | M_BLEL, | |
1488 | M_BLE_I, | |
1489 | M_BLEL_I, | |
1490 | M_BLEU, | |
1491 | M_BLEUL, | |
1492 | M_BLEU_I, | |
1493 | M_BLEUL_I, | |
df58fc94 RS |
1494 | M_BLEZ, |
1495 | M_BLEZL, | |
e7af610e NC |
1496 | M_BLT, |
1497 | M_BLTL, | |
1498 | M_BLT_I, | |
1499 | M_BLTL_I, | |
1500 | M_BLTU, | |
1501 | M_BLTUL, | |
1502 | M_BLTU_I, | |
1503 | M_BLTUL_I, | |
df58fc94 RS |
1504 | M_BLTZ, |
1505 | M_BLTZL, | |
1506 | M_BLTZALL, | |
e7af610e | 1507 | M_BNE, |
df58fc94 | 1508 | M_BNEL, |
e7af610e NC |
1509 | M_BNE_I, |
1510 | M_BNEL_I, | |
d43b4baf | 1511 | M_CACHE_AB, |
7f3c4072 | 1512 | M_CACHEE_AB, |
e7af610e NC |
1513 | M_DABS, |
1514 | M_DADD_I, | |
1515 | M_DADDU_I, | |
1516 | M_DDIV_3, | |
1517 | M_DDIV_3I, | |
1518 | M_DDIVU_3, | |
1519 | M_DDIVU_3I, | |
1520 | M_DIV_3, | |
1521 | M_DIV_3I, | |
1522 | M_DIVU_3, | |
1523 | M_DIVU_3I, | |
1524 | M_DLA_AB, | |
1abe91b1 | 1525 | M_DLCA_AB, |
e7af610e NC |
1526 | M_DLI, |
1527 | M_DMUL, | |
8eaec934 | 1528 | M_DMUL_I, |
e7af610e | 1529 | M_DMULO, |
8eaec934 | 1530 | M_DMULO_I, |
e7af610e | 1531 | M_DMULOU, |
8eaec934 | 1532 | M_DMULOU_I, |
e7af610e NC |
1533 | M_DREM_3, |
1534 | M_DREM_3I, | |
1535 | M_DREMU_3, | |
1536 | M_DREMU_3I, | |
1537 | M_DSUB_I, | |
1538 | M_DSUBU_I, | |
1539 | M_DSUBU_I_2, | |
1540 | M_J_A, | |
1541 | M_JAL_1, | |
1542 | M_JAL_2, | |
1543 | M_JAL_A, | |
df58fc94 RS |
1544 | M_JALS_1, |
1545 | M_JALS_2, | |
1546 | M_JALS_A, | |
833794fc MR |
1547 | M_JRADDIUSP, |
1548 | M_JRC, | |
e7af610e NC |
1549 | M_L_DAB, |
1550 | M_LA_AB, | |
e7af610e | 1551 | M_LB_AB, |
7f3c4072 | 1552 | M_LBE_AB, |
e7af610e | 1553 | M_LBU_AB, |
7f3c4072 | 1554 | M_LBUE_AB, |
1abe91b1 | 1555 | M_LCA_AB, |
e7af610e NC |
1556 | M_LD_AB, |
1557 | M_LDC1_AB, | |
1558 | M_LDC2_AB, | |
c77c0862 | 1559 | M_LQC2_AB, |
e7af610e NC |
1560 | M_LDC3_AB, |
1561 | M_LDL_AB, | |
df58fc94 | 1562 | M_LDM_AB, |
df58fc94 | 1563 | M_LDP_AB, |
e7af610e | 1564 | M_LDR_AB, |
e7af610e | 1565 | M_LH_AB, |
7f3c4072 | 1566 | M_LHE_AB, |
e7af610e | 1567 | M_LHU_AB, |
7f3c4072 | 1568 | M_LHUE_AB, |
e7af610e NC |
1569 | M_LI, |
1570 | M_LI_D, | |
1571 | M_LI_DD, | |
1572 | M_LI_S, | |
1573 | M_LI_SS, | |
1574 | M_LL_AB, | |
1575 | M_LLD_AB, | |
7f3c4072 | 1576 | M_LLE_AB, |
e407c74b | 1577 | M_LQ_AB, |
e7af610e | 1578 | M_LW_AB, |
7f3c4072 | 1579 | M_LWE_AB, |
e7af610e | 1580 | M_LWC0_AB, |
e7af610e | 1581 | M_LWC1_AB, |
e7af610e | 1582 | M_LWC2_AB, |
e7af610e | 1583 | M_LWC3_AB, |
e7af610e | 1584 | M_LWL_AB, |
7f3c4072 | 1585 | M_LWLE_AB, |
df58fc94 | 1586 | M_LWM_AB, |
df58fc94 | 1587 | M_LWP_AB, |
e7af610e | 1588 | M_LWR_AB, |
7f3c4072 | 1589 | M_LWRE_AB, |
e7af610e | 1590 | M_LWU_AB, |
52b6b6b9 JM |
1591 | M_MSGSND, |
1592 | M_MSGLD, | |
1593 | M_MSGLD_T, | |
1594 | M_MSGWAIT, | |
1595 | M_MSGWAIT_T, | |
a58ec95a | 1596 | M_MOVE, |
833794fc | 1597 | M_MOVEP, |
e7af610e | 1598 | M_MUL, |
8eaec934 | 1599 | M_MUL_I, |
e7af610e | 1600 | M_MULO, |
8eaec934 | 1601 | M_MULO_I, |
e7af610e | 1602 | M_MULOU, |
8eaec934 | 1603 | M_MULOU_I, |
e7af610e NC |
1604 | M_NOR_I, |
1605 | M_OR_I, | |
3eebd5eb | 1606 | M_PREF_AB, |
7f3c4072 | 1607 | M_PREFE_AB, |
e7af610e NC |
1608 | M_REM_3, |
1609 | M_REM_3I, | |
1610 | M_REMU_3, | |
1611 | M_REMU_3I, | |
771c7ce4 | 1612 | M_DROL, |
e7af610e | 1613 | M_ROL, |
771c7ce4 | 1614 | M_DROL_I, |
e7af610e | 1615 | M_ROL_I, |
771c7ce4 | 1616 | M_DROR, |
e7af610e | 1617 | M_ROR, |
771c7ce4 | 1618 | M_DROR_I, |
e7af610e NC |
1619 | M_ROR_I, |
1620 | M_S_DA, | |
e7af610e NC |
1621 | M_S_DAB, |
1622 | M_S_S, | |
dd6a37e7 | 1623 | M_SAA_AB, |
dd6a37e7 | 1624 | M_SAAD_AB, |
e7af610e NC |
1625 | M_SC_AB, |
1626 | M_SCD_AB, | |
7f3c4072 | 1627 | M_SCE_AB, |
e7af610e NC |
1628 | M_SD_AB, |
1629 | M_SDC1_AB, | |
1630 | M_SDC2_AB, | |
c77c0862 | 1631 | M_SQC2_AB, |
e7af610e NC |
1632 | M_SDC3_AB, |
1633 | M_SDL_AB, | |
df58fc94 | 1634 | M_SDM_AB, |
df58fc94 | 1635 | M_SDP_AB, |
e7af610e NC |
1636 | M_SDR_AB, |
1637 | M_SEQ, | |
1638 | M_SEQ_I, | |
1639 | M_SGE, | |
1640 | M_SGE_I, | |
1641 | M_SGEU, | |
1642 | M_SGEU_I, | |
1643 | M_SGT, | |
1644 | M_SGT_I, | |
1645 | M_SGTU, | |
1646 | M_SGTU_I, | |
1647 | M_SLE, | |
1648 | M_SLE_I, | |
1649 | M_SLEU, | |
1650 | M_SLEU_I, | |
1651 | M_SLT_I, | |
1652 | M_SLTU_I, | |
1653 | M_SNE, | |
1654 | M_SNE_I, | |
e7af610e | 1655 | M_SB_AB, |
7f3c4072 | 1656 | M_SBE_AB, |
e7af610e | 1657 | M_SH_AB, |
7f3c4072 | 1658 | M_SHE_AB, |
e407c74b | 1659 | M_SQ_AB, |
e7af610e | 1660 | M_SW_AB, |
7f3c4072 | 1661 | M_SWE_AB, |
e7af610e | 1662 | M_SWC0_AB, |
e7af610e | 1663 | M_SWC1_AB, |
e7af610e | 1664 | M_SWC2_AB, |
e7af610e | 1665 | M_SWC3_AB, |
e7af610e | 1666 | M_SWL_AB, |
7f3c4072 | 1667 | M_SWLE_AB, |
df58fc94 | 1668 | M_SWM_AB, |
df58fc94 | 1669 | M_SWP_AB, |
e7af610e | 1670 | M_SWR_AB, |
7f3c4072 | 1671 | M_SWRE_AB, |
e7af610e NC |
1672 | M_SUB_I, |
1673 | M_SUBU_I, | |
1674 | M_SUBU_I_2, | |
1675 | M_TEQ_I, | |
1676 | M_TGE_I, | |
1677 | M_TGEU_I, | |
1678 | M_TLT_I, | |
1679 | M_TLTU_I, | |
1680 | M_TNE_I, | |
1681 | M_TRUNCWD, | |
1682 | M_TRUNCWS, | |
f2ae14a1 RS |
1683 | M_ULD_AB, |
1684 | M_ULH_AB, | |
1685 | M_ULHU_AB, | |
1686 | M_ULW_AB, | |
1687 | M_USH_AB, | |
1688 | M_USW_AB, | |
1689 | M_USD_AB, | |
e7af610e NC |
1690 | M_XOR_I, |
1691 | M_COP0, | |
1692 | M_COP1, | |
1693 | M_COP2, | |
1694 | M_COP3, | |
1695 | M_NUM_MACROS | |
252b5132 RH |
1696 | }; |
1697 | ||
1698 | ||
1699 | /* The order of overloaded instructions matters. Label arguments and | |
1700 | register arguments look the same. Instructions that can have either | |
1701 | for arguments must apear in the correct order in this table for the | |
1702 | assembler to pick the right one. In other words, entries with | |
1703 | immediate operands must apear after the same instruction with | |
1704 | registers. | |
1705 | ||
1706 | Many instructions are short hand for other instructions (i.e., The | |
1707 | jal <register> instruction is short for jalr <register>). */ | |
1708 | ||
14daeee3 | 1709 | extern const struct mips_operand mips_vu0_channel_mask; |
ab902481 | 1710 | extern const struct mips_operand *decode_mips_operand (const char *); |
252b5132 RH |
1711 | extern const struct mips_opcode mips_builtin_opcodes[]; |
1712 | extern const int bfd_mips_num_builtin_opcodes; | |
1713 | extern struct mips_opcode *mips_opcodes; | |
1714 | extern int bfd_mips_num_opcodes; | |
1715 | #define NUMOPCODES bfd_mips_num_opcodes | |
1716 | ||
1717 | \f | |
1718 | /* The rest of this file adds definitions for the mips16 TinyRISC | |
1719 | processor. */ | |
1720 | ||
1721 | /* These are the bitmasks and shift counts used for the different | |
1722 | fields in the instruction formats. Other than OP, no masks are | |
1723 | provided for the fixed portions of an instruction, since they are | |
1724 | not needed. | |
1725 | ||
1726 | The I format uses IMM11. | |
1727 | ||
1728 | The RI format uses RX and IMM8. | |
1729 | ||
1730 | The RR format uses RX, and RY. | |
1731 | ||
1732 | The RRI format uses RX, RY, and IMM5. | |
1733 | ||
1734 | The RRR format uses RX, RY, and RZ. | |
1735 | ||
1736 | The RRI_A format uses RX, RY, and IMM4. | |
1737 | ||
1738 | The SHIFT format uses RX, RY, and SHAMT. | |
1739 | ||
1740 | The I8 format uses IMM8. | |
1741 | ||
1742 | The I8_MOVR32 format uses RY and REGR32. | |
1743 | ||
1744 | The IR_MOV32R format uses REG32R and MOV32Z. | |
1745 | ||
1746 | The I64 format uses IMM8. | |
1747 | ||
1748 | The RI64 format uses RY and IMM5. | |
1749 | */ | |
1750 | ||
1751 | #define MIPS16OP_MASK_OP 0x1f | |
1752 | #define MIPS16OP_SH_OP 11 | |
1753 | #define MIPS16OP_MASK_IMM11 0x7ff | |
1754 | #define MIPS16OP_SH_IMM11 0 | |
1755 | #define MIPS16OP_MASK_RX 0x7 | |
1756 | #define MIPS16OP_SH_RX 8 | |
1757 | #define MIPS16OP_MASK_IMM8 0xff | |
1758 | #define MIPS16OP_SH_IMM8 0 | |
1759 | #define MIPS16OP_MASK_RY 0x7 | |
1760 | #define MIPS16OP_SH_RY 5 | |
1761 | #define MIPS16OP_MASK_IMM5 0x1f | |
1762 | #define MIPS16OP_SH_IMM5 0 | |
1763 | #define MIPS16OP_MASK_RZ 0x7 | |
1764 | #define MIPS16OP_SH_RZ 2 | |
1765 | #define MIPS16OP_MASK_IMM4 0xf | |
1766 | #define MIPS16OP_SH_IMM4 0 | |
1767 | #define MIPS16OP_MASK_REGR32 0x1f | |
1768 | #define MIPS16OP_SH_REGR32 0 | |
1769 | #define MIPS16OP_MASK_REG32R 0x1f | |
1770 | #define MIPS16OP_SH_REG32R 3 | |
1771 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) | |
1772 | #define MIPS16OP_MASK_MOVE32Z 0x7 | |
1773 | #define MIPS16OP_SH_MOVE32Z 0 | |
1774 | #define MIPS16OP_MASK_IMM6 0x3f | |
1775 | #define MIPS16OP_SH_IMM6 5 | |
1776 | ||
bb35fb24 NC |
1777 | /* These are the characters which may appears in the args field of a MIPS16 |
1778 | instruction. They appear in the order in which the fields appear when the | |
1779 | instruction is used. Commas and parentheses in the args string are ignored | |
1780 | when assembling, and written into the output when disassembling. | |
252b5132 RH |
1781 | |
1782 | "y" 3 bit register (MIPS16OP_*_RY) | |
1783 | "x" 3 bit register (MIPS16OP_*_RX) | |
1784 | "z" 3 bit register (MIPS16OP_*_RZ) | |
1785 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) | |
1786 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) | |
1787 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) | |
1788 | "0" zero register ($0) | |
1789 | "S" stack pointer ($sp or $29) | |
1790 | "P" program counter | |
1791 | "R" return address register ($ra or $31) | |
1792 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) | |
1793 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) | |
1794 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) | |
1795 | "a" 26 bit jump address | |
27c5c572 | 1796 | "i" likewise, but flips bit 0 |
252b5132 RH |
1797 | "e" 11 bit extension value |
1798 | "l" register list for entry instruction | |
1799 | "L" register list for exit instruction | |
1800 | ||
cc537e56 RS |
1801 | "I" an immediate value used for macros |
1802 | ||
252b5132 RH |
1803 | The remaining codes may be extended. Except as otherwise noted, |
1804 | the full extended operand is a 16 bit signed value. | |
1805 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) | |
1806 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) | |
1807 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) | |
1808 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) | |
1809 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) | |
1810 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) | |
1811 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) | |
1812 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) | |
1813 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) | |
1814 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) | |
1815 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) | |
1816 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) | |
1817 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) | |
1818 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) | |
1819 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) | |
1820 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) | |
1821 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) | |
1822 | "q" 11 bit branch address (MIPS16OP_*_IMM11) | |
1823 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) | |
1824 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) | |
1825 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) | |
0499d65b TS |
1826 | "m" 7 bit register list for save instruction (18 bit extended) |
1827 | "M" 7 bit register list for restore instruction (18 bit extended) | |
1828 | */ | |
1829 | ||
1830 | /* Save/restore encoding for the args field when all 4 registers are | |
1831 | either saved as arguments or saved/restored as statics. */ | |
1832 | #define MIPS16_ALL_ARGS 0xe | |
1833 | #define MIPS16_ALL_STATICS 0xb | |
252b5132 | 1834 | |
252b5132 RH |
1835 | /* The following flags have the same value for the mips16 opcode |
1836 | table: | |
7c176fa8 MR |
1837 | |
1838 | INSN_ISA3 | |
1839 | ||
252b5132 RH |
1840 | INSN_UNCOND_BRANCH_DELAY |
1841 | INSN_COND_BRANCH_DELAY | |
1842 | INSN_COND_BRANCH_LIKELY (never used) | |
1843 | INSN_READ_HI | |
1844 | INSN_READ_LO | |
1845 | INSN_WRITE_HI | |
1846 | INSN_WRITE_LO | |
1847 | INSN_TRAP | |
7c176fa8 | 1848 | FP_D (never used) |
252b5132 RH |
1849 | */ |
1850 | ||
c3c07478 | 1851 | extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); |
252b5132 RH |
1852 | extern const struct mips_opcode mips16_opcodes[]; |
1853 | extern const int bfd_mips16_num_opcodes; | |
1854 | ||
2309ddf2 MR |
1855 | /* These are the bit masks and shift counts used for the different fields |
1856 | in the microMIPS instruction formats. No masks are provided for the | |
1857 | fixed portions of an instruction, since they are not needed. */ | |
df58fc94 | 1858 | |
df58fc94 RS |
1859 | #define MICROMIPSOP_MASK_IMMEDIATE 0xffff |
1860 | #define MICROMIPSOP_SH_IMMEDIATE 0 | |
1861 | #define MICROMIPSOP_MASK_DELTA 0xffff | |
1862 | #define MICROMIPSOP_SH_DELTA 0 | |
1863 | #define MICROMIPSOP_MASK_CODE10 0x3ff | |
1864 | #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ | |
1865 | #define MICROMIPSOP_MASK_TRAP 0xf | |
1866 | #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ | |
1867 | #define MICROMIPSOP_MASK_SHAMT 0x1f | |
1868 | #define MICROMIPSOP_SH_SHAMT 11 | |
1869 | #define MICROMIPSOP_MASK_TARGET 0x3ffffff | |
1870 | #define MICROMIPSOP_SH_TARGET 0 | |
1871 | #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ | |
1872 | #define MICROMIPSOP_SH_EXTLSB 6 | |
1873 | #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
1874 | #define MICROMIPSOP_SH_EXTMSBD 11 | |
1875 | #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ | |
1876 | #define MICROMIPSOP_SH_INSMSB 11 | |
1877 | #define MICROMIPSOP_MASK_CODE 0x3ff | |
1878 | #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ | |
1879 | #define MICROMIPSOP_MASK_CODE2 0x3ff | |
1880 | #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ | |
1881 | #define MICROMIPSOP_MASK_CACHE 0x1f | |
1882 | #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ | |
1883 | #define MICROMIPSOP_MASK_SEL 0x7 | |
1884 | #define MICROMIPSOP_SH_SEL 11 | |
1885 | #define MICROMIPSOP_MASK_OFFSET12 0xfff | |
1886 | #define MICROMIPSOP_SH_OFFSET12 0 | |
dec0624d MR |
1887 | #define MICROMIPSOP_MASK_3BITPOS 0x7 |
1888 | #define MICROMIPSOP_SH_3BITPOS 21 | |
df58fc94 RS |
1889 | #define MICROMIPSOP_MASK_STYPE 0x1f |
1890 | #define MICROMIPSOP_SH_STYPE 16 | |
1891 | #define MICROMIPSOP_MASK_OFFSET10 0x3ff | |
1892 | #define MICROMIPSOP_SH_OFFSET10 6 | |
1893 | #define MICROMIPSOP_MASK_RS 0x1f | |
1894 | #define MICROMIPSOP_SH_RS 16 | |
1895 | #define MICROMIPSOP_MASK_RT 0x1f | |
1896 | #define MICROMIPSOP_SH_RT 21 | |
1897 | #define MICROMIPSOP_MASK_RD 0x1f | |
1898 | #define MICROMIPSOP_SH_RD 11 | |
1899 | #define MICROMIPSOP_MASK_FS 0x1f | |
1900 | #define MICROMIPSOP_SH_FS 16 | |
1901 | #define MICROMIPSOP_MASK_FT 0x1f | |
1902 | #define MICROMIPSOP_SH_FT 21 | |
1903 | #define MICROMIPSOP_MASK_FD 0x1f | |
1904 | #define MICROMIPSOP_SH_FD 11 | |
1905 | #define MICROMIPSOP_MASK_FR 0x1f | |
1906 | #define MICROMIPSOP_SH_FR 6 | |
1907 | #define MICROMIPSOP_MASK_RS3 0x1f | |
1908 | #define MICROMIPSOP_SH_RS3 6 | |
1909 | #define MICROMIPSOP_MASK_PREFX 0x1f | |
1910 | #define MICROMIPSOP_SH_PREFX 11 | |
1911 | #define MICROMIPSOP_MASK_BCC 0x7 | |
1912 | #define MICROMIPSOP_SH_BCC 18 | |
1913 | #define MICROMIPSOP_MASK_CCC 0x7 | |
1914 | #define MICROMIPSOP_SH_CCC 13 | |
1915 | #define MICROMIPSOP_MASK_COPZ 0x7fffff | |
1916 | #define MICROMIPSOP_SH_COPZ 3 | |
1917 | ||
1918 | #define MICROMIPSOP_MASK_MB 0x7 | |
1919 | #define MICROMIPSOP_SH_MB 23 | |
1920 | #define MICROMIPSOP_MASK_MC 0x7 | |
1921 | #define MICROMIPSOP_SH_MC 4 | |
1922 | #define MICROMIPSOP_MASK_MD 0x7 | |
1923 | #define MICROMIPSOP_SH_MD 7 | |
1924 | #define MICROMIPSOP_MASK_ME 0x7 | |
1925 | #define MICROMIPSOP_SH_ME 1 | |
1926 | #define MICROMIPSOP_MASK_MF 0x7 | |
1927 | #define MICROMIPSOP_SH_MF 3 | |
1928 | #define MICROMIPSOP_MASK_MG 0x7 | |
1929 | #define MICROMIPSOP_SH_MG 0 | |
1930 | #define MICROMIPSOP_MASK_MH 0x7 | |
1931 | #define MICROMIPSOP_SH_MH 7 | |
df58fc94 RS |
1932 | #define MICROMIPSOP_MASK_MJ 0x1f |
1933 | #define MICROMIPSOP_SH_MJ 0 | |
1934 | #define MICROMIPSOP_MASK_ML 0x7 | |
1935 | #define MICROMIPSOP_SH_ML 4 | |
1936 | #define MICROMIPSOP_MASK_MM 0x7 | |
1937 | #define MICROMIPSOP_SH_MM 1 | |
1938 | #define MICROMIPSOP_MASK_MN 0x7 | |
1939 | #define MICROMIPSOP_SH_MN 4 | |
1940 | #define MICROMIPSOP_MASK_MP 0x1f | |
1941 | #define MICROMIPSOP_SH_MP 5 | |
1942 | #define MICROMIPSOP_MASK_MQ 0x7 | |
1943 | #define MICROMIPSOP_SH_MQ 7 | |
1944 | ||
1945 | #define MICROMIPSOP_MASK_IMMA 0x7f | |
1946 | #define MICROMIPSOP_SH_IMMA 0 | |
1947 | #define MICROMIPSOP_MASK_IMMB 0x7 | |
1948 | #define MICROMIPSOP_SH_IMMB 1 | |
1949 | #define MICROMIPSOP_MASK_IMMC 0xf | |
1950 | #define MICROMIPSOP_SH_IMMC 0 | |
1951 | #define MICROMIPSOP_MASK_IMMD 0x3ff | |
1952 | #define MICROMIPSOP_SH_IMMD 0 | |
1953 | #define MICROMIPSOP_MASK_IMME 0x7f | |
1954 | #define MICROMIPSOP_SH_IMME 0 | |
1955 | #define MICROMIPSOP_MASK_IMMF 0xf | |
1956 | #define MICROMIPSOP_SH_IMMF 0 | |
1957 | #define MICROMIPSOP_MASK_IMMG 0xf | |
1958 | #define MICROMIPSOP_SH_IMMG 0 | |
1959 | #define MICROMIPSOP_MASK_IMMH 0xf | |
1960 | #define MICROMIPSOP_SH_IMMH 0 | |
1961 | #define MICROMIPSOP_MASK_IMMI 0x7f | |
1962 | #define MICROMIPSOP_SH_IMMI 0 | |
1963 | #define MICROMIPSOP_MASK_IMMJ 0xf | |
1964 | #define MICROMIPSOP_SH_IMMJ 0 | |
1965 | #define MICROMIPSOP_MASK_IMML 0xf | |
1966 | #define MICROMIPSOP_SH_IMML 0 | |
1967 | #define MICROMIPSOP_MASK_IMMM 0x7 | |
1968 | #define MICROMIPSOP_SH_IMMM 1 | |
1969 | #define MICROMIPSOP_MASK_IMMN 0x3 | |
1970 | #define MICROMIPSOP_SH_IMMN 4 | |
1971 | #define MICROMIPSOP_MASK_IMMO 0xf | |
1972 | #define MICROMIPSOP_SH_IMMO 0 | |
1973 | #define MICROMIPSOP_MASK_IMMP 0x1f | |
1974 | #define MICROMIPSOP_SH_IMMP 0 | |
1975 | #define MICROMIPSOP_MASK_IMMQ 0x7fffff | |
1976 | #define MICROMIPSOP_SH_IMMQ 0 | |
1977 | #define MICROMIPSOP_MASK_IMMU 0x1f | |
1978 | #define MICROMIPSOP_SH_IMMU 0 | |
1979 | #define MICROMIPSOP_MASK_IMMW 0x3f | |
1980 | #define MICROMIPSOP_SH_IMMW 1 | |
1981 | #define MICROMIPSOP_MASK_IMMX 0xf | |
1982 | #define MICROMIPSOP_SH_IMMX 1 | |
1983 | #define MICROMIPSOP_MASK_IMMY 0x1ff | |
1984 | #define MICROMIPSOP_SH_IMMY 1 | |
1985 | ||
03f66e8a MR |
1986 | /* MIPS DSP ASE */ |
1987 | #define MICROMIPSOP_MASK_DSPACC 0x3 | |
1988 | #define MICROMIPSOP_SH_DSPACC 14 | |
1989 | #define MICROMIPSOP_MASK_DSPSFT 0x3f | |
1990 | #define MICROMIPSOP_SH_DSPSFT 16 | |
1991 | #define MICROMIPSOP_MASK_SA3 0x7 | |
1992 | #define MICROMIPSOP_SH_SA3 13 | |
1993 | #define MICROMIPSOP_MASK_SA4 0xf | |
1994 | #define MICROMIPSOP_SH_SA4 12 | |
1995 | #define MICROMIPSOP_MASK_IMM8 0xff | |
1996 | #define MICROMIPSOP_SH_IMM8 13 | |
1997 | #define MICROMIPSOP_MASK_IMM10 0x3ff | |
1998 | #define MICROMIPSOP_SH_IMM10 16 | |
1999 | #define MICROMIPSOP_MASK_WRDSP 0x3f | |
2000 | #define MICROMIPSOP_SH_WRDSP 14 | |
2001 | #define MICROMIPSOP_MASK_BP 0x3 | |
2002 | #define MICROMIPSOP_SH_BP 14 | |
2003 | ||
df58fc94 RS |
2004 | /* Placeholders for fields that only exist in the traditional 32-bit |
2005 | instruction encoding; see the comment above for details. */ | |
2006 | #define MICROMIPSOP_MASK_CODE20 0 | |
2007 | #define MICROMIPSOP_SH_CODE20 0 | |
2008 | #define MICROMIPSOP_MASK_PERFREG 0 | |
2009 | #define MICROMIPSOP_SH_PERFREG 0 | |
2010 | #define MICROMIPSOP_MASK_CODE19 0 | |
2011 | #define MICROMIPSOP_SH_CODE19 0 | |
2012 | #define MICROMIPSOP_MASK_ALN 0 | |
2013 | #define MICROMIPSOP_SH_ALN 0 | |
2014 | #define MICROMIPSOP_MASK_VECBYTE 0 | |
2015 | #define MICROMIPSOP_SH_VECBYTE 0 | |
2016 | #define MICROMIPSOP_MASK_VECALIGN 0 | |
2017 | #define MICROMIPSOP_SH_VECALIGN 0 | |
df58fc94 RS |
2018 | #define MICROMIPSOP_MASK_DSPACC_S 0 |
2019 | #define MICROMIPSOP_SH_DSPACC_S 0 | |
df58fc94 RS |
2020 | #define MICROMIPSOP_MASK_DSPSFT_7 0 |
2021 | #define MICROMIPSOP_SH_DSPSFT_7 0 | |
df58fc94 RS |
2022 | #define MICROMIPSOP_MASK_RDDSP 0 |
2023 | #define MICROMIPSOP_SH_RDDSP 0 | |
df58fc94 RS |
2024 | #define MICROMIPSOP_MASK_MT_U 0 |
2025 | #define MICROMIPSOP_SH_MT_U 0 | |
2026 | #define MICROMIPSOP_MASK_MT_H 0 | |
2027 | #define MICROMIPSOP_SH_MT_H 0 | |
2028 | #define MICROMIPSOP_MASK_MTACC_T 0 | |
2029 | #define MICROMIPSOP_SH_MTACC_T 0 | |
2030 | #define MICROMIPSOP_MASK_MTACC_D 0 | |
2031 | #define MICROMIPSOP_SH_MTACC_D 0 | |
2032 | #define MICROMIPSOP_MASK_BBITIND 0 | |
2033 | #define MICROMIPSOP_SH_BBITIND 0 | |
2034 | #define MICROMIPSOP_MASK_CINSPOS 0 | |
2035 | #define MICROMIPSOP_SH_CINSPOS 0 | |
2036 | #define MICROMIPSOP_MASK_CINSLM1 0 | |
2037 | #define MICROMIPSOP_SH_CINSLM1 0 | |
2038 | #define MICROMIPSOP_MASK_SEQI 0 | |
2039 | #define MICROMIPSOP_SH_SEQI 0 | |
2040 | #define MICROMIPSOP_SH_OFFSET_A 0 | |
2041 | #define MICROMIPSOP_MASK_OFFSET_A 0 | |
2042 | #define MICROMIPSOP_SH_OFFSET_B 0 | |
2043 | #define MICROMIPSOP_MASK_OFFSET_B 0 | |
2044 | #define MICROMIPSOP_SH_OFFSET_C 0 | |
2045 | #define MICROMIPSOP_MASK_OFFSET_C 0 | |
2046 | #define MICROMIPSOP_SH_RZ 0 | |
2047 | #define MICROMIPSOP_MASK_RZ 0 | |
2048 | #define MICROMIPSOP_SH_FZ 0 | |
2049 | #define MICROMIPSOP_MASK_FZ 0 | |
2050 | ||
7f3c4072 CM |
2051 | /* microMIPS Enhanced VA Scheme */ |
2052 | #define MICROMIPSOP_SH_EVAOFFSET 0 | |
2053 | #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff | |
2054 | ||
df58fc94 RS |
2055 | /* These are the characters which may appears in the args field of a microMIPS |
2056 | instruction. They appear in the order in which the fields appear | |
2057 | when the instruction is used. Commas and parentheses in the args | |
2058 | string are ignored when assembling, and written into the output | |
2059 | when disassembling. | |
2060 | ||
2061 | The followings are for 16-bit microMIPS instructions. | |
2062 | ||
2063 | "ma" must be $28 | |
2064 | "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 | |
2065 | The same register used as both source and target. | |
2066 | "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 | |
2067 | "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 | |
2068 | The same register used as both source and target. | |
2069 | "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 | |
2070 | "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 | |
e76ff5ab | 2071 | "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 |
df58fc94 RS |
2072 | "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 |
2073 | "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 | |
2074 | "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 | |
2075 | "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 | |
2076 | "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 | |
2077 | "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 | |
2078 | "mr" must be program counter | |
2079 | "ms" must be $29 | |
2080 | "mt" must be the same as the previous register | |
2081 | "mx" must be the same as the destination register | |
2082 | "my" must be $31 | |
2083 | "mz" must be $0 | |
2084 | ||
2085 | "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) | |
2086 | "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) | |
2087 | "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, | |
2088 | 32768, 65535) (MICROMIPSOP_*_IMMC) | |
2089 | "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) | |
2090 | "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) | |
2091 | "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) | |
2092 | "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) | |
2093 | "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) | |
2094 | "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) | |
2095 | "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) | |
2096 | "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) | |
2097 | "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) | |
2098 | "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) | |
2099 | "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) | |
2100 | "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) | |
2101 | "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) | |
2102 | "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) | |
2103 | "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) | |
2104 | "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) | |
2105 | "mZ" must be zero | |
2106 | ||
2107 | In most cases 32-bit microMIPS instructions use the same characters | |
2108 | as MIPS (with ADDIUPC being a notable exception, but there are some | |
2109 | others too). | |
2110 | ||
2111 | "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) | |
18870af7 | 2112 | "1" 5-bit sync type (MICROMIPSOP_*_STYPE) |
df58fc94 RS |
2113 | "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) |
2114 | ">" shift amount between 32 and 63, stored after subtracting 32 | |
2115 | (MICROMIPSOP_*_SHAMT) | |
dec0624d | 2116 | "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) |
df58fc94 RS |
2117 | "|" 4-bit trap code (MICROMIPSOP_*_TRAP) |
2118 | "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) | |
2119 | "a" 26-bit target address (MICROMIPSOP_*_TARGET) | |
27c5c572 | 2120 | "+i" likewise, but flips bit 0 |
df58fc94 RS |
2121 | "b" 5-bit base register (MICROMIPSOP_*_RS) |
2122 | "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) | |
2123 | "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) | |
2124 | "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) | |
26f85d7a | 2125 | "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) |
df58fc94 RS |
2126 | "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) |
2127 | "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) | |
2128 | "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) | |
2129 | "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) | |
2130 | "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) | |
2131 | "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) | |
2132 | "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) | |
2133 | "s" 5-bit source register specifier (MICROMIPSOP_*_RS) | |
2134 | "t" 5-bit target register (MICROMIPSOP_*_RT) | |
2135 | "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) | |
2136 | "v" 5-bit same register used as both source and destination | |
2137 | (MICROMIPSOP_*_RS) | |
2138 | "w" 5-bit same register used as both target and destination | |
2139 | (MICROMIPSOP_*_RT) | |
2140 | "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) | |
2141 | "z" must be zero register | |
2142 | "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) | |
df58fc94 RS |
2143 | "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) |
2144 | ||
2145 | "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes | |
2146 | LSB (MICROMIPSOP_*_EXTLSB). | |
2147 | Enforces: 0 <= pos < 32. | |
2148 | "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). | |
2149 | Requires that "+A" or "+E" occur first to set position. | |
2150 | Enforces: 0 < (pos+size) <= 32. | |
2151 | "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). | |
2152 | Requires that "+A" or "+E" occur first to set position. | |
2153 | Enforces: 0 < (pos+size) <= 32. | |
2154 | (Also used by DEXT w/ different limits, but limits for | |
2155 | that are checked by the M_DEXT macro.) | |
2156 | "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). | |
2157 | Enforces: 32 <= pos < 64. | |
2158 | "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). | |
2159 | Requires that "+A" or "+E" occur first to set position. | |
2160 | Enforces: 32 < (pos+size) <= 64. | |
2161 | "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). | |
2162 | Requires that "+A" or "+E" occur first to set position. | |
2163 | Enforces: 32 < (pos+size) <= 64. | |
2164 | "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). | |
2165 | Requires that "+A" or "+E" occur first to set position. | |
2166 | Enforces: 32 < (pos+size) <= 64. | |
5575639b MR |
2167 | "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code |
2168 | (MICROMIPSOP_*_CODE10) | |
df58fc94 RS |
2169 | |
2170 | PC-relative addition (ADDIUPC) instruction: | |
2171 | "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) | |
2172 | "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 | |
2173 | ||
2174 | Floating point instructions: | |
2175 | "D" 5-bit destination register (MICROMIPSOP_*_FD) | |
2176 | "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) | |
2177 | "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) | |
2178 | "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) | |
2179 | "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) | |
2180 | "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) | |
2181 | "V" 5-bit same register used as floating source and destination or target | |
2182 | (MICROMIPSOP_*_FS) | |
2183 | ||
2184 | Coprocessor instructions: | |
2185 | "E" 5-bit target register (MICROMIPSOP_*_RT) | |
18870af7 | 2186 | "G" 5-bit source register (MICROMIPSOP_*_RS) |
df58fc94 | 2187 | "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) |
df58fc94 RS |
2188 | |
2189 | Macro instructions: | |
2190 | "A" general 32 bit expression | |
2191 | "I" 32-bit immediate (value placed in imm_expr). | |
df58fc94 RS |
2192 | "F" 64-bit floating point constant in .rdata |
2193 | "L" 64-bit floating point constant in .lit8 | |
2194 | "f" 32-bit floating point constant | |
2195 | "l" 32-bit floating point constant in .lit4 | |
2196 | ||
03f66e8a MR |
2197 | DSP ASE usage: |
2198 | "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) | |
2199 | "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) | |
2200 | "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) | |
2201 | "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) | |
2202 | "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) | |
2203 | "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) | |
2204 | "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) | |
2205 | "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) | |
2206 | "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) | |
2207 | "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) | |
2208 | ||
7f3c4072 CM |
2209 | microMIPS Enhanced VA Scheme: |
2210 | "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) | |
2211 | ||
387a82f1 CF |
2212 | MSA Extension: |
2213 | "+d" 5-bit MSA register (FD) | |
2214 | "+e" 5-bit MSA register (FS) | |
2215 | "+h" 5-bit MSA register (FT) | |
2216 | "+k" 5-bit GPR at bit 6 | |
2217 | "+l" 5-bit MSA control register at bit 6 | |
2218 | "+n" 5-bit MSA control register at bit 11 | |
e269fea7 AB |
2219 | "+o" 4-bit vector element index at bit 16 |
2220 | "+u" 3-bit vector element index at bit 16 | |
2221 | "+v" 2-bit vector element index at bit 16 | |
2222 | "+w" 1-bit vector element index at bit 16 | |
387a82f1 CF |
2223 | "+x" 5-bit shift amount at bit 16 |
2224 | "+T" (-512 .. 511) << 0 at bit 16 | |
2225 | "+U" (-512 .. 511) << 1 at bit 16 | |
2226 | "+V" (-512 .. 511) << 2 at bit 16 | |
2227 | "+W" (-512 .. 511) << 3 at bit 16 | |
2228 | "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 | |
2229 | "+!" 3 bit unsigned bit position at bit 16 | |
2230 | "+@" 4 bit unsigned bit position at bit 16 | |
2231 | "+#" 6 bit unsigned bit position at bit 16 | |
2232 | "+$" 5 bit unsigned immediate at bit 16 | |
2233 | "+%" 5 bit signed immediate at bit 16 | |
2234 | "+^" 10 bit signed immediate at bit 11 | |
2235 | "+&" 0 vector element index | |
2236 | "+*" 5-bit register vector element index at bit 16 | |
2237 | "+|" 8-bit mask at bit 16 | |
2238 | ||
df58fc94 RS |
2239 | Other: |
2240 | "()" parens surrounding optional value | |
2241 | "," separates operands | |
2242 | "+" start of extension sequence | |
2243 | "m" start of microMIPS extension sequence | |
2244 | ||
2245 | Characters used so far, for quick reference when adding more: | |
03f66e8a | 2246 | "12345678 0" |
7361da2c AB |
2247 | "<>(),+-.@\^|~" |
2248 | "ABCDEFGHI KLMN RST V " | |
df58fc94 RS |
2249 | "abcd f hijklmnopqrstuvw yz" |
2250 | ||
2251 | Extension character sequences used so far ("+" followed by the | |
2252 | following), for quick reference when adding more: | |
df58fc94 | 2253 | "" |
387a82f1 | 2254 | "~!@#$%^&*|" |
5575639b | 2255 | "ABCEFGHJTUVW" |
387a82f1 | 2256 | "dehijklnouvwx" |
df58fc94 RS |
2257 | |
2258 | Extension character sequences used so far ("m" followed by the | |
2259 | following), for quick reference when adding more: | |
2260 | "" | |
2261 | "" | |
2262 | " BCDEFGHIJ LMNOPQ U WXYZ" | |
2263 | " bcdefghij lmn pq st xyz" | |
7361da2c AB |
2264 | |
2265 | Extension character sequences used so far ("-" followed by the | |
2266 | following), for quick reference when adding more: | |
2267 | "" | |
2268 | "" | |
2269 | <none so far> | |
df58fc94 RS |
2270 | */ |
2271 | ||
ab902481 | 2272 | extern const struct mips_operand *decode_micromips_operand (const char *); |
df58fc94 RS |
2273 | extern const struct mips_opcode micromips_opcodes[]; |
2274 | extern const int bfd_micromips_num_opcodes; | |
2275 | ||
c67a084a NC |
2276 | /* A NOP insn impemented as "or at,at,zero". |
2277 | Used to implement -mfix-loongson2f. */ | |
2278 | #define LOONGSON2F_NOP_INSN 0x00200825 | |
2279 | ||
252b5132 | 2280 | #endif /* _MIPS_H_ */ |