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[deliverable/binutils-gdb.git] / include / opcode / mips.h
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252b5132 1/* mips.h. Mips opcode list for GDB, the GNU debugger.
c3aa17e9
AM		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005
4f1d9bd8 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
7
8This file is part of GDB, GAS, and the GNU binutils.
9
10GDB, GAS, and the GNU binutils are free software; you can redistribute
11them and/or modify them under the terms of the GNU General Public
12License as published by the Free Software Foundation; either version
131, or (at your option) any later version.
14
15GDB, GAS, and the GNU binutils are distributed in the hope that they
16will be useful, but WITHOUT ANY WARRANTY; without even the implied
17warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18the GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this file; see the file COPYING. If not, write to the Free
e172dbf8 22Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 23
24#ifndef _MIPS_H_
25#define _MIPS_H_
26
27/* These are bit masks and shift counts to use to access the various
28 fields of an instruction. To retrieve the X field of an
29 instruction, use the expression
30 (i >> OP_SH_X) & OP_MASK_X
31 To set the same field (to j), use
32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
33
34 Make sure you use fields that are appropriate for the instruction,
8eaec934 35 of course.
252b5132 36
8eaec934 37 The 'i' format uses OP, RS, RT and IMMEDIATE.
252b5132
RH		 38
39 The 'j' format uses OP and TARGET.
40
41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
42
43 The 'b' format uses OP, RS, RT and DELTA.
44
45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
46
47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
48
49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
50 breakpoint instruction are not defined; Kane says the breakpoint
51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
52 only use ten bits). An optional two-operand form of break/sdbbp
4372b673
NC		 53 allows the lower ten bits to be set too, and MIPS32 and later
54 architectures allow 20 bits to be set with a signal operand
55 (using CODE20).
252b5132 56
4372b673 57 The syscall instruction uses CODE20.
252b5132
RH		 58
59 The general coprocessor instructions use COPZ. */
60
61#define OP_MASK_OP 0x3f
62#define OP_SH_OP 26
63#define OP_MASK_RS 0x1f
64#define OP_SH_RS 21
65#define OP_MASK_FR 0x1f
66#define OP_SH_FR 21
67#define OP_MASK_FMT 0x1f
68#define OP_SH_FMT 21
69#define OP_MASK_BCC 0x7
70#define OP_SH_BCC 18
71#define OP_MASK_CODE 0x3ff
72#define OP_SH_CODE 16
73#define OP_MASK_CODE2 0x3ff
74#define OP_SH_CODE2 6
75#define OP_MASK_RT 0x1f
76#define OP_SH_RT 16
77#define OP_MASK_FT 0x1f
78#define OP_SH_FT 16
79#define OP_MASK_CACHE 0x1f
80#define OP_SH_CACHE 16
81#define OP_MASK_RD 0x1f
82#define OP_SH_RD 11
83#define OP_MASK_FS 0x1f
84#define OP_SH_FS 11
85#define OP_MASK_PREFX 0x1f
86#define OP_SH_PREFX 11
87#define OP_MASK_CCC 0x7
88#define OP_SH_CCC 8
4372b673
NC		 89#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
90#define OP_SH_CODE20 6
252b5132
RH		 91#define OP_MASK_SHAMT 0x1f
92#define OP_SH_SHAMT 6
93#define OP_MASK_FD 0x1f
94#define OP_SH_FD 6
95#define OP_MASK_TARGET 0x3ffffff
96#define OP_SH_TARGET 0
97#define OP_MASK_COPZ 0x1ffffff
98#define OP_SH_COPZ 0
99#define OP_MASK_IMMEDIATE 0xffff
100#define OP_SH_IMMEDIATE 0
101#define OP_MASK_DELTA 0xffff
102#define OP_SH_DELTA 0
103#define OP_MASK_FUNCT 0x3f
104#define OP_SH_FUNCT 0
105#define OP_MASK_SPEC 0x3f
106#define OP_SH_SPEC 0
4372b673
NC		 107#define OP_SH_LOCC 8 /* FP condition code. */
108#define OP_SH_HICC 18 /* FP condition code. */
252b5132 109#define OP_MASK_CC 0x7
4372b673
NC		 110#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
111#define OP_MASK_COP1NORM 0x1 /* a single bit. */
112#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
252b5132
RH		 113#define OP_MASK_COP1SPEC 0xf
114#define OP_MASK_COP1SCLR 0x4
115#define OP_MASK_COP1CMP 0x3
116#define OP_SH_COP1CMP 4
4372b673 117#define OP_SH_FORMAT 21 /* FP short format field. */
252b5132
RH		 118#define OP_MASK_FORMAT 0x7
119#define OP_SH_TRUE 16
120#define OP_MASK_TRUE 0x1
121#define OP_SH_GE 17
122#define OP_MASK_GE 0x01
123#define OP_SH_UNSIGNED 16
124#define OP_MASK_UNSIGNED 0x1
125#define OP_SH_HINT 16
126#define OP_MASK_HINT 0x1f
4372b673 127#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
8eaec934 128#define OP_MASK_MMI 0x3f
252b5132
RH		 129#define OP_SH_MMISUB 6
130#define OP_MASK_MMISUB 0x1f
4372b673 131#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
252b5132 132#define OP_SH_PERFREG 1
4372b673
NC		 133#define OP_SH_SEL 0 /* Coprocessor select field. */
134#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
135#define OP_SH_CODE19 6 /* 19 bit wait code. */
136#define OP_MASK_CODE19 0x7ffff
deec1734
CD		 137#define OP_SH_ALN 21
138#define OP_MASK_ALN 0x7
139#define OP_SH_VSEL 21
140#define OP_MASK_VSEL 0x1f
9752cf1b
RS		 141#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
142 but 0x8-0xf don't select bytes. */
143#define OP_SH_VECBYTE 22
144#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
145#define OP_SH_VECALIGN 21
af7ee8bf
CD		 146#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
147#define OP_SH_INSMSB 11
148#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
149#define OP_SH_EXTMSBD 11
deec1734 150
93c34b9b
CF		 151/* MIPS DSP ASE */
152#define OP_SH_DSPACC 11
153#define OP_MASK_DSPACC 0x3
154#define OP_SH_DSPACC_S 21
155#define OP_MASK_DSPACC_S 0x3
156#define OP_SH_DSPSFT 20
157#define OP_MASK_DSPSFT 0x3f
158#define OP_SH_DSPSFT_7 19
159#define OP_MASK_DSPSFT_7 0x7f
160#define OP_SH_SA3 21
161#define OP_MASK_SA3 0x7
162#define OP_SH_SA4 21
163#define OP_MASK_SA4 0xf
164#define OP_SH_IMM8 16
165#define OP_MASK_IMM8 0xff
166#define OP_SH_IMM10 16
167#define OP_MASK_IMM10 0x3ff
168#define OP_SH_WRDSP 11
169#define OP_MASK_WRDSP 0x3f
170#define OP_SH_RDDSP 16
171#define OP_MASK_RDDSP 0x3f
8b082fb1
TS		 172#define OP_SH_BP 11
173#define OP_MASK_BP 0x3
93c34b9b 174
089b39de
CF		 175/* MIPS MT ASE */
176#define OP_SH_MT_U 5
177#define OP_MASK_MT_U 0x1
178#define OP_SH_MT_H 4
179#define OP_MASK_MT_H 0x1
180#define OP_SH_MTACC_T 18
181#define OP_MASK_MTACC_T 0x3
182#define OP_SH_MTACC_D 13
183#define OP_MASK_MTACC_D 0x3
184
640c0ccd
CD		 185#define OP_OP_COP0 0x10
186#define OP_OP_COP1 0x11
187#define OP_OP_COP2 0x12
188#define OP_OP_COP3 0x13
189#define OP_OP_LWC1 0x31
190#define OP_OP_LWC2 0x32
191#define OP_OP_LWC3 0x33 /* a.k.a. pref */
192#define OP_OP_LDC1 0x35
193#define OP_OP_LDC2 0x36
194#define OP_OP_LDC3 0x37 /* a.k.a. ld */
195#define OP_OP_SWC1 0x39
196#define OP_OP_SWC2 0x3a
197#define OP_OP_SWC3 0x3b
198#define OP_OP_SDC1 0x3d
199#define OP_OP_SDC2 0x3e
200#define OP_OP_SDC3 0x3f /* a.k.a. sd */
201
deec1734
CD		 202/* Values in the 'VSEL' field. */
203#define MDMX_FMTSEL_IMM_QH 0x1d
204#define MDMX_FMTSEL_IMM_OB 0x1e
205#define MDMX_FMTSEL_VEC_QH 0x15
206#define MDMX_FMTSEL_VEC_OB 0x16
4372b673 207
9bcd4f99
TS		 208/* UDI */
209#define OP_SH_UDI1 6
210#define OP_MASK_UDI1 0x1f
211#define OP_SH_UDI2 6
212#define OP_MASK_UDI2 0x3ff
213#define OP_SH_UDI3 6
214#define OP_MASK_UDI3 0x7fff
215#define OP_SH_UDI4 6
216#define OP_MASK_UDI4 0xfffff
217
252b5132
RH		 218/* This structure holds information for a particular instruction. */
219
220struct mips_opcode
221{
222 /* The name of the instruction. */
223 const char *name;
224 /* A string describing the arguments for this instruction. */
225 const char *args;
226 /* The basic opcode for the instruction. When assembling, this
227 opcode is modified by the arguments to produce the actual opcode
228 that is used. If pinfo is INSN_MACRO, then this is 0. */
229 unsigned long match;
230 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
231 relevant portions of the opcode when disassembling. If the
232 actual opcode anded with the match field equals the opcode field,
233 then we have found the correct instruction. If pinfo is
234 INSN_MACRO, then this field is the macro identifier. */
235 unsigned long mask;
236 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
237 of bits describing the instruction, notably any relevant hazard
238 information. */
239 unsigned long pinfo;
dc9a9f39
FF		 240 /* A collection of additional bits describing the instruction. */
241 unsigned long pinfo2;
252b5132
RH		 242 /* A collection of bits describing the instruction sets of which this
243 instruction or macro is a member. */
244 unsigned long membership;
245};
246
27abff54 247/* These are the characters which may appear in the args field of an
252b5132
RH		 248 instruction. They appear in the order in which the fields appear
249 when the instruction is used. Commas and parentheses in the args
250 string are ignored when assembling, and written into the output
251 when disassembling.
252
253 Each of these characters corresponds to a mask field defined above.
254
255 "<" 5 bit shift amount (OP_*_SHAMT)
256 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
257 "a" 26 bit target address (OP_*_TARGET)
258 "b" 5 bit base register (OP_*_RS)
259 "c" 10 bit breakpoint code (OP_*_CODE)
260 "d" 5 bit destination register specifier (OP_*_RD)
261 "h" 5 bit prefx hint (OP_*_PREFX)
262 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
263 "j" 16 bit signed immediate (OP_*_DELTA)
264 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
9752cf1b 265 Also used for immediate operands in vr5400 vector insns.
252b5132
RH		 266 "o" 16 bit signed offset (OP_*_DELTA)
267 "p" 16 bit PC relative branch target address (OP_*_DELTA)
268 "q" 10 bit extra breakpoint code (OP_*_CODE2)
269 "r" 5 bit same register used as both source and target (OP_*_RS)
270 "s" 5 bit source register specifier (OP_*_RS)
271 "t" 5 bit target register (OP_*_RT)
272 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
273 "v" 5 bit same register used as both source and destination (OP_*_RS)
274 "w" 5 bit same register used as both target and destination (OP_*_RT)
4372b673
NC		 275 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
276 (used by clo and clz)
252b5132 277 "C" 25 bit coprocessor function code (OP_*_COPZ)
4372b673
NC		 278 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
279 "J" 19 bit wait function code (OP_*_CODE19)
252b5132
RH		 280 "x" accept and ignore register name
281 "z" must be zero register
af7ee8bf 282 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
ef0ee844
TS		 283 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
284 LSB (OP_*_SHAMT).
071742cf 285 Enforces: 0 <= pos < 32.
ef0ee844 286 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
5f74bc13 287 Requires that "+A" or "+E" occur first to set position.
071742cf 288 Enforces: 0 < (pos+size) <= 32.
ef0ee844 289 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
5f74bc13 290 Requires that "+A" or "+E" occur first to set position.
071742cf 291 Enforces: 0 < (pos+size) <= 32.
5f74bc13
CD		 292 (Also used by "dext" w/ different limits, but limits for
293 that are checked by the M_DEXT macro.)
ef0ee844 294 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
5f74bc13 295 Enforces: 32 <= pos < 64.
ef0ee844 296 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
5f74bc13
CD		 297 Requires that "+A" or "+E" occur first to set position.
298 Enforces: 32 < (pos+size) <= 64.
299 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
300 Requires that "+A" or "+E" occur first to set position.
301 Enforces: 32 < (pos+size) <= 64.
302 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
303 Requires that "+A" or "+E" occur first to set position.
304 Enforces: 32 < (pos+size) <= 64.
252b5132
RH		 305
306 Floating point instructions:
307 "D" 5 bit destination register (OP_*_FD)
308 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
309 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
310 "S" 5 bit fs source 1 register (OP_*_FS)
311 "T" 5 bit ft source 2 register (OP_*_FT)
312 "R" 5 bit fr source 3 register (OP_*_FR)
313 "V" 5 bit same register used as floating source and destination (OP_*_FS)
314 "W" 5 bit same register used as floating target and destination (OP_*_FT)
315
316 Coprocessor instructions:
317 "E" 5 bit target register (OP_*_RT)
318 "G" 5 bit destination register (OP_*_RD)
8ff529d8 319 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
252b5132 320 "P" 5 bit performance-monitor register (OP_*_PERFREG)
9752cf1b
RS		 321 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
322 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
323 see also "k" above
bbcc0807
CD		 324 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
325 for pretty-printing in disassembly only.
252b5132
RH		 326
327 Macro instructions:
328 "A" General 32 bit expression
5f74bc13
CD		 329 "I" 32 bit immediate (value placed in imm_expr).
330 "+I" 32 bit immediate (value placed in imm2_expr).
252b5132
RH		 331 "F" 64 bit floating point constant in .rdata
332 "L" 64 bit floating point constant in .lit8
333 "f" 32 bit floating point constant
334 "l" 32 bit floating point constant in .lit4
335
deec1734
CD		 336 MDMX instruction operands (note that while these use the FP register
337 fields, they accept both $fN and $vN names for the registers):
338 "O" MDMX alignment offset (OP_*_ALN)
339 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
340 "X" MDMX destination register (OP_*_FD)
341 "Y" MDMX source register (OP_*_FS)
342 "Z" MDMX source register (OP_*_FT)
343
93c34b9b 344 DSP ASE usage:
8b082fb1 345 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
93c34b9b
CF		 346 "3" 3 bit unsigned immediate (OP_*_SA3)
347 "4" 4 bit unsigned immediate (OP_*_SA4)
348 "5" 8 bit unsigned immediate (OP_*_IMM8)
349 "6" 5 bit unsigned immediate (OP_*_RS)
350 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
351 "8" 6 bit unsigned immediate (OP_*_WRDSP)
352 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
353 "0" 6 bit signed immediate (OP_*_DSPSFT)
354 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
355 "'" 6 bit unsigned immediate (OP_*_RDDSP)
356 "@" 10 bit signed immediate (OP_*_IMM10)
357
089b39de 358 MT ASE usage:
a9e24354
TS		 359 "!" 1 bit usermode flag (OP_*_MT_U)
360 "$" 1 bit load high flag (OP_*_MT_H)
089b39de
CF		 361 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
362 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
363 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
364 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
365 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
366
9bcd4f99
TS		 367 UDI immediates:
368 "+1" UDI immediate bits 6-10
369 "+2" UDI immediate bits 6-15
370 "+3" UDI immediate bits 6-20
371 "+4" UDI immediate bits 6-25
372
252b5132
RH		 373 Other:
374 "()" parens surrounding optional value
375 "," separates operands
9752cf1b 376 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
af7ee8bf 377 "+" Start of extension sequence.
252b5132
RH		 378
379 Characters used so far, for quick reference when adding more:
8b082fb1 380 "234567890"
089b39de 381 "%[]<>(),+:'@!$*&"
af7ee8bf 382 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
089b39de 383 "abcdefghijklopqrstuvwxz"
af7ee8bf
CD		 384
385 Extension character sequences used so far ("+" followed by the
386 following), for quick reference when adding more:
9bcd4f99 387 "1234"
089b39de
CF		 388 "ABCDEFGHIT"
389 "t"
252b5132
RH		 390*/
391
392/* These are the bits which may be set in the pinfo field of an
393 instructions, if it is not equal to INSN_MACRO. */
394
395/* Modifies the general purpose register in OP_*_RD. */
396#define INSN_WRITE_GPR_D 0x00000001
397/* Modifies the general purpose register in OP_*_RT. */
398#define INSN_WRITE_GPR_T 0x00000002
399/* Modifies general purpose register 31. */
400#define INSN_WRITE_GPR_31 0x00000004
401/* Modifies the floating point register in OP_*_FD. */
402#define INSN_WRITE_FPR_D 0x00000008
403/* Modifies the floating point register in OP_*_FS. */
404#define INSN_WRITE_FPR_S 0x00000010
405/* Modifies the floating point register in OP_*_FT. */
406#define INSN_WRITE_FPR_T 0x00000020
407/* Reads the general purpose register in OP_*_RS. */
408#define INSN_READ_GPR_S 0x00000040
409/* Reads the general purpose register in OP_*_RT. */
410#define INSN_READ_GPR_T 0x00000080
411/* Reads the floating point register in OP_*_FS. */
412#define INSN_READ_FPR_S 0x00000100
413/* Reads the floating point register in OP_*_FT. */
414#define INSN_READ_FPR_T 0x00000200
415/* Reads the floating point register in OP_*_FR. */
416#define INSN_READ_FPR_R 0x00000400
417/* Modifies coprocessor condition code. */
418#define INSN_WRITE_COND_CODE 0x00000800
419/* Reads coprocessor condition code. */
420#define INSN_READ_COND_CODE 0x00001000
421/* TLB operation. */
422#define INSN_TLB 0x00002000
423/* Reads coprocessor register other than floating point register. */
424#define INSN_COP 0x00004000
425/* Instruction loads value from memory, requiring delay. */
426#define INSN_LOAD_MEMORY_DELAY 0x00008000
427/* Instruction loads value from coprocessor, requiring delay. */
428#define INSN_LOAD_COPROC_DELAY 0x00010000
429/* Instruction has unconditional branch delay slot. */
430#define INSN_UNCOND_BRANCH_DELAY 0x00020000
431/* Instruction has conditional branch delay slot. */
432#define INSN_COND_BRANCH_DELAY 0x00040000
433/* Conditional branch likely: if branch not taken, insn nullified. */
434#define INSN_COND_BRANCH_LIKELY 0x00080000
435/* Moves to coprocessor register, requiring delay. */
436#define INSN_COPROC_MOVE_DELAY 0x00100000
437/* Loads coprocessor register from memory, requiring delay. */
438#define INSN_COPROC_MEMORY_DELAY 0x00200000
439/* Reads the HI register. */
440#define INSN_READ_HI 0x00400000
441/* Reads the LO register. */
442#define INSN_READ_LO 0x00800000
443/* Modifies the HI register. */
444#define INSN_WRITE_HI 0x01000000
445/* Modifies the LO register. */
446#define INSN_WRITE_LO 0x02000000
447/* Takes a trap (easier to keep out of delay slot). */
448#define INSN_TRAP 0x04000000
449/* Instruction stores value into memory. */
450#define INSN_STORE_MEMORY 0x08000000
451/* Instruction uses single precision floating point. */
452#define FP_S 0x10000000
453/* Instruction uses double precision floating point. */
454#define FP_D 0x20000000
455/* Instruction is part of the tx39's integer multiply family. */
456#define INSN_MULT 0x40000000
457/* Instruction synchronize shared memory. */
458#define INSN_SYNC 0x80000000
dc9a9f39
FF		 459
460/* These are the bits which may be set in the pinfo2 field of an
461 instruction. */
462
463/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
239cb185 464#define INSN2_ALIAS 0x00000001
dc9a9f39 465/* Instruction reads MDMX accumulator. */
239cb185 466#define INSN2_READ_MDMX_ACC 0x00000002
dc9a9f39 467/* Instruction writes MDMX accumulator. */
239cb185 468#define INSN2_WRITE_MDMX_ACC 0x00000004
252b5132
RH		 469
470/* Instruction is actually a macro. It should be ignored by the
471 disassembler, and requires special treatment by the assembler. */
472#define INSN_MACRO 0xffffffff
473
e7af610e 474/* Masks used to mark instructions to indicate which MIPS ISA level
56950294
MS		 475 they were introduced in. INSN_ISA_MASK masks an enumeration that
476 specifies the base ISA level(s). The remainder of a 32-bit
477 word constructed using these macros is a bitmask of the remaining
478 INSN_* values below. */
479
480#define INSN_ISA_MASK 0x0000000ful
481
482/* We cannot start at zero due to ISA_UNKNOWN below. */
483#define INSN_ISA1 1
484#define INSN_ISA2 2
485#define INSN_ISA3 3
486#define INSN_ISA4 4
487#define INSN_ISA5 5
488#define INSN_ISA32 6
489#define INSN_ISA32R2 7
490#define INSN_ISA64 8
491#define INSN_ISA64R2 9
492/* Below this point the INSN_* values correspond to combinations of ISAs.
493 They are only for use in the opcodes table to indicate membership of
494 a combination of ISAs that cannot be expressed using the usual inclusion
495 ordering on the above INSN_* values. */
496#define INSN_ISA3_32 10
497#define INSN_ISA3_32R2 11
498#define INSN_ISA4_32 12
499#define INSN_ISA4_32R2 13
500#define INSN_ISA5_32R2 14
501
502/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
503 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
504 this table describes whether at least one of the ISAs described by X
505 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
506 a particular core and X as the ISA level(s) at which a certain instruction
507 is defined.) The ISA(s) described by X is/are implemented by Y iff
508 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
509 is non-zero. */
510static const unsigned int mips_isa_table[] =
511 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
252b5132 512
1f25f5d3 513/* Masks used for MIPS-defined ASEs. */
8b082fb1 514#define INSN_ASE_MASK 0x3c00f000
1f25f5d3 515
93c34b9b
CF		 516/* DSP ASE */
517#define INSN_DSP 0x00001000
65263ce3 518#define INSN_DSP64 0x00002000
aec421e0 519/* MIPS 16 ASE */
65263ce3 520#define INSN_MIPS16 0x00004000
1f25f5d3 521/* MIPS-3D ASE */
65263ce3 522#define INSN_MIPS3D 0x00008000
1f25f5d3 523
252b5132 524/* Chip specific instructions. These are bitmasks. */
e7af610e 525
252b5132 526/* MIPS R4650 instruction. */
e7af610e 527#define INSN_4650 0x00010000
252b5132 528/* LSI R4010 instruction. */
e7af610e
NC		 529#define INSN_4010 0x00020000
530/* NEC VR4100 instruction. */
bf40d919 531#define INSN_4100 0x00040000
252b5132 532/* Toshiba R3900 instruction. */
bf40d919 533#define INSN_3900 0x00080000
99c14723
TS		 534/* MIPS R10000 instruction. */
535#define INSN_10000 0x00100000
2228315b
CD		 536/* Broadcom SB-1 instruction. */
537#define INSN_SB1 0x00200000
9752cf1b
RS		 538/* NEC VR4111/VR4181 instruction. */
539#define INSN_4111 0x00400000
540/* NEC VR4120 instruction. */
541#define INSN_4120 0x00800000
542/* NEC VR5400 instruction. */
543#define INSN_5400 0x01000000
544/* NEC VR5500 instruction. */
545#define INSN_5500 0x02000000
39a7806d 546
65263ce3
TS		 547/* MDMX ASE */
548#define INSN_MDMX 0x04000000
089b39de 549/* MT ASE */
65263ce3 550#define INSN_MT 0x08000000
8b082fb1 551/* SmartMIPS ASE */
65263ce3 552#define INSN_SMARTMIPS 0x10000000
8b082fb1
TS		 553/* DSP R2 ASE */
554#define INSN_DSPR2 0x20000000
350cc38d
MS		 555/* ST Microelectronics Loongson 2E. */
556#define INSN_LOONGSON_2E 0x40000000
557/* ST Microelectronics Loongson 2F. */
558#define INSN_LOONGSON_2F 0x80000000
39a7806d 559
e7af610e
NC		 560/* MIPS ISA defines, use instead of hardcoding ISA level. */
561
562#define ISA_UNKNOWN 0 /* Gas internal use. */
56950294
MS		 563#define ISA_MIPS1 INSN_ISA1
564#define ISA_MIPS2 INSN_ISA2
565#define ISA_MIPS3 INSN_ISA3
566#define ISA_MIPS4 INSN_ISA4
567#define ISA_MIPS5 INSN_ISA5
af7ee8bf 568
56950294
MS		 569#define ISA_MIPS32 INSN_ISA32
570#define ISA_MIPS64 INSN_ISA64
367c01af 571
56950294
MS		 572#define ISA_MIPS32R2 INSN_ISA32R2
573#define ISA_MIPS64R2 INSN_ISA64R2
5f74bc13 574
af7ee8bf 575
156c2f8b
NC		 576/* CPU defines, use instead of hardcoding processor number. Keep this
577 in sync with bfd/archures.c in order for machine selection to work. */
e7af610e 578#define CPU_UNKNOWN 0 /* Gas internal use. */
156c2f8b
NC		 579#define CPU_R3000 3000
580#define CPU_R3900 3900
581#define CPU_R4000 4000
582#define CPU_R4010 4010
583#define CPU_VR4100 4100
584#define CPU_R4111 4111
9752cf1b 585#define CPU_VR4120 4120
156c2f8b
NC		 586#define CPU_R4300 4300
587#define CPU_R4400 4400
588#define CPU_R4600 4600
589#define CPU_R4650 4650
590#define CPU_R5000 5000
9752cf1b
RS		 591#define CPU_VR5400 5400
592#define CPU_VR5500 5500
156c2f8b 593#define CPU_R6000 6000
5a7ea749 594#define CPU_RM7000 7000
156c2f8b 595#define CPU_R8000 8000
98e7aba8 596#define CPU_RM9000 9000
156c2f8b 597#define CPU_R10000 10000
d1cf510e 598#define CPU_R12000 12000
156c2f8b
NC		 599#define CPU_MIPS16 16
600#define CPU_MIPS32 32
af7ee8bf 601#define CPU_MIPS32R2 33
84ea6cf2
NC		 602#define CPU_MIPS5 5
603#define CPU_MIPS64 64
5f74bc13 604#define CPU_MIPS64R2 65
c6c98b38 605#define CPU_SB1 12310201 /* octal 'SB', 01. */
350cc38d
MS		 606#define CPU_LOONGSON_2E 3001
607#define CPU_LOONGSON_2F 3002
156c2f8b 608
1f25f5d3
CD		 609/* Test for membership in an ISA including chip specific ISAs. INSN
610 is pointer to an element of the opcode table; ISA is the specified
611 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
612 test, or zero if no CPU specific ISA test is desired. */
a58ec95a
RS		 613
614#define OPCODE_IS_MEMBER(insn, isa, cpu) \
56950294
MS		 615 (((isa & INSN_ISA_MASK) != 0 \
616 && ((insn)->membership & INSN_ISA_MASK) != 0 \
617 && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
618 (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
619 || ((isa & ~INSN_ISA_MASK) \
620 & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
156c2f8b 621 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
5a7ea749 622 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
98e7aba8 623 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
156c2f8b 624 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
9752cf1b 625 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
99c14723
TS		 626 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
627 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
2228315b 628 && ((insn)->membership & INSN_10000) != 0) \
5d84d93f 629 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
9752cf1b
RS		 630 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
631 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
632 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
633 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
350cc38d
MS		 634 || (cpu == CPU_LOONGSON_2E \
635 && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
636 || (cpu == CPU_LOONGSON_2F \
637 && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
e4432525 638 || 0) /* Please keep this term for easier source merging. */
252b5132
RH		 639
640/* This is a list of macro expanded instructions.
8eaec934 641
e7af610e
NC		 642 _I appended means immediate
643 _A appended means address
644 _AB appended means address with base register
645 _D appended means 64 bit floating point constant
646 _S appended means 32 bit floating point constant. */
647
648enum
649{
650 M_ABS,
651 M_ADD_I,
652 M_ADDU_I,
653 M_AND_I,
8b082fb1 654 M_BALIGN,
e7af610e
NC		 655 M_BEQ,
656 M_BEQ_I,
657 M_BEQL_I,
658 M_BGE,
659 M_BGEL,
660 M_BGE_I,
661 M_BGEL_I,
662 M_BGEU,
663 M_BGEUL,
664 M_BGEU_I,
665 M_BGEUL_I,
666 M_BGT,
667 M_BGTL,
668 M_BGT_I,
669 M_BGTL_I,
670 M_BGTU,
671 M_BGTUL,
672 M_BGTU_I,
673 M_BGTUL_I,
674 M_BLE,
675 M_BLEL,
676 M_BLE_I,
677 M_BLEL_I,
678 M_BLEU,
679 M_BLEUL,
680 M_BLEU_I,
681 M_BLEUL_I,
682 M_BLT,
683 M_BLTL,
684 M_BLT_I,
685 M_BLTL_I,
686 M_BLTU,
687 M_BLTUL,
688 M_BLTU_I,
689 M_BLTUL_I,
690 M_BNE,
691 M_BNE_I,
692 M_BNEL_I,
d43b4baf 693 M_CACHE_AB,
e7af610e
NC		 694 M_DABS,
695 M_DADD_I,
696 M_DADDU_I,
697 M_DDIV_3,
698 M_DDIV_3I,
699 M_DDIVU_3,
700 M_DDIVU_3I,
5f74bc13
CD		 701 M_DEXT,
702 M_DINS,
e7af610e
NC		 703 M_DIV_3,
704 M_DIV_3I,
705 M_DIVU_3,
706 M_DIVU_3I,
707 M_DLA_AB,
1abe91b1 708 M_DLCA_AB,
e7af610e
NC		 709 M_DLI,
710 M_DMUL,
8eaec934 711 M_DMUL_I,
e7af610e 712 M_DMULO,
8eaec934 713 M_DMULO_I,
e7af610e 714 M_DMULOU,
8eaec934 715 M_DMULOU_I,
e7af610e
NC		 716 M_DREM_3,
717 M_DREM_3I,
718 M_DREMU_3,
719 M_DREMU_3I,
720 M_DSUB_I,
721 M_DSUBU_I,
722 M_DSUBU_I_2,
723 M_J_A,
724 M_JAL_1,
725 M_JAL_2,
726 M_JAL_A,
727 M_L_DOB,
728 M_L_DAB,
729 M_LA_AB,
730 M_LB_A,
731 M_LB_AB,
732 M_LBU_A,
733 M_LBU_AB,
1abe91b1 734 M_LCA_AB,
e7af610e
NC		 735 M_LD_A,
736 M_LD_OB,
737 M_LD_AB,
738 M_LDC1_AB,
739 M_LDC2_AB,
740 M_LDC3_AB,
741 M_LDL_AB,
742 M_LDR_AB,
743 M_LH_A,
744 M_LH_AB,
745 M_LHU_A,
746 M_LHU_AB,
747 M_LI,
748 M_LI_D,
749 M_LI_DD,
750 M_LI_S,
751 M_LI_SS,
752 M_LL_AB,
753 M_LLD_AB,
754 M_LS_A,
755 M_LW_A,
756 M_LW_AB,
757 M_LWC0_A,
758 M_LWC0_AB,
759 M_LWC1_A,
760 M_LWC1_AB,
761 M_LWC2_A,
762 M_LWC2_AB,
763 M_LWC3_A,
764 M_LWC3_AB,
765 M_LWL_A,
766 M_LWL_AB,
767 M_LWR_A,
768 M_LWR_AB,
769 M_LWU_AB,
a58ec95a 770 M_MOVE,
e7af610e 771 M_MUL,
8eaec934 772 M_MUL_I,
e7af610e 773 M_MULO,
8eaec934 774 M_MULO_I,
e7af610e 775 M_MULOU,
8eaec934 776 M_MULOU_I,
e7af610e
NC		 777 M_NOR_I,
778 M_OR_I,
779 M_REM_3,
780 M_REM_3I,
781 M_REMU_3,
782 M_REMU_3I,
771c7ce4 783 M_DROL,
e7af610e 784 M_ROL,
771c7ce4 785 M_DROL_I,
e7af610e 786 M_ROL_I,
771c7ce4 787 M_DROR,
e7af610e 788 M_ROR,
771c7ce4 789 M_DROR_I,
e7af610e
NC		 790 M_ROR_I,
791 M_S_DA,
792 M_S_DOB,
793 M_S_DAB,
794 M_S_S,
795 M_SC_AB,
796 M_SCD_AB,
797 M_SD_A,
798 M_SD_OB,
799 M_SD_AB,
800 M_SDC1_AB,
801 M_SDC2_AB,
802 M_SDC3_AB,
803 M_SDL_AB,
804 M_SDR_AB,
805 M_SEQ,
806 M_SEQ_I,
807 M_SGE,
808 M_SGE_I,
809 M_SGEU,
810 M_SGEU_I,
811 M_SGT,
812 M_SGT_I,
813 M_SGTU,
814 M_SGTU_I,
815 M_SLE,
816 M_SLE_I,
817 M_SLEU,
818 M_SLEU_I,
819 M_SLT_I,
820 M_SLTU_I,
821 M_SNE,
822 M_SNE_I,
823 M_SB_A,
824 M_SB_AB,
825 M_SH_A,
826 M_SH_AB,
827 M_SW_A,
828 M_SW_AB,
829 M_SWC0_A,
830 M_SWC0_AB,
831 M_SWC1_A,
832 M_SWC1_AB,
833 M_SWC2_A,
834 M_SWC2_AB,
835 M_SWC3_A,
836 M_SWC3_AB,
837 M_SWL_A,
838 M_SWL_AB,
839 M_SWR_A,
840 M_SWR_AB,
841 M_SUB_I,
842 M_SUBU_I,
843 M_SUBU_I_2,
844 M_TEQ_I,
845 M_TGE_I,
846 M_TGEU_I,
847 M_TLT_I,
848 M_TLTU_I,
849 M_TNE_I,
850 M_TRUNCWD,
851 M_TRUNCWS,
852 M_ULD,
853 M_ULD_A,
854 M_ULH,
855 M_ULH_A,
856 M_ULHU,
857 M_ULHU_A,
858 M_ULW,
859 M_ULW_A,
860 M_USH,
861 M_USH_A,
862 M_USW,
863 M_USW_A,
864 M_USD,
865 M_USD_A,
866 M_XOR_I,
867 M_COP0,
868 M_COP1,
869 M_COP2,
870 M_COP3,
871 M_NUM_MACROS
252b5132
RH		 872};
873
874
875/* The order of overloaded instructions matters. Label arguments and
876 register arguments look the same. Instructions that can have either
877 for arguments must apear in the correct order in this table for the
878 assembler to pick the right one. In other words, entries with
879 immediate operands must apear after the same instruction with
880 registers.
881
882 Many instructions are short hand for other instructions (i.e., The
883 jal <register> instruction is short for jalr <register>). */
884
885extern const struct mips_opcode mips_builtin_opcodes[];
886extern const int bfd_mips_num_builtin_opcodes;
887extern struct mips_opcode *mips_opcodes;
888extern int bfd_mips_num_opcodes;
889#define NUMOPCODES bfd_mips_num_opcodes
890
891\f
892/* The rest of this file adds definitions for the mips16 TinyRISC
893 processor. */
894
895/* These are the bitmasks and shift counts used for the different
896 fields in the instruction formats. Other than OP, no masks are
897 provided for the fixed portions of an instruction, since they are
898 not needed.
899
900 The I format uses IMM11.
901
902 The RI format uses RX and IMM8.
903
904 The RR format uses RX, and RY.
905
906 The RRI format uses RX, RY, and IMM5.
907
908 The RRR format uses RX, RY, and RZ.
909
910 The RRI_A format uses RX, RY, and IMM4.
911
912 The SHIFT format uses RX, RY, and SHAMT.
913
914 The I8 format uses IMM8.
915
916 The I8_MOVR32 format uses RY and REGR32.
917
918 The IR_MOV32R format uses REG32R and MOV32Z.
919
920 The I64 format uses IMM8.
921
922 The RI64 format uses RY and IMM5.
923 */
924
925#define MIPS16OP_MASK_OP 0x1f
926#define MIPS16OP_SH_OP 11
927#define MIPS16OP_MASK_IMM11 0x7ff
928#define MIPS16OP_SH_IMM11 0
929#define MIPS16OP_MASK_RX 0x7
930#define MIPS16OP_SH_RX 8
931#define MIPS16OP_MASK_IMM8 0xff
932#define MIPS16OP_SH_IMM8 0
933#define MIPS16OP_MASK_RY 0x7
934#define MIPS16OP_SH_RY 5
935#define MIPS16OP_MASK_IMM5 0x1f
936#define MIPS16OP_SH_IMM5 0
937#define MIPS16OP_MASK_RZ 0x7
938#define MIPS16OP_SH_RZ 2
939#define MIPS16OP_MASK_IMM4 0xf
940#define MIPS16OP_SH_IMM4 0
941#define MIPS16OP_MASK_REGR32 0x1f
942#define MIPS16OP_SH_REGR32 0
943#define MIPS16OP_MASK_REG32R 0x1f
944#define MIPS16OP_SH_REG32R 3
945#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
946#define MIPS16OP_MASK_MOVE32Z 0x7
947#define MIPS16OP_SH_MOVE32Z 0
948#define MIPS16OP_MASK_IMM6 0x3f
949#define MIPS16OP_SH_IMM6 5
950
951/* These are the characters which may appears in the args field of an
952 instruction. They appear in the order in which the fields appear
953 when the instruction is used. Commas and parentheses in the args
954 string are ignored when assembling, and written into the output
955 when disassembling.
956
957 "y" 3 bit register (MIPS16OP_*_RY)
958 "x" 3 bit register (MIPS16OP_*_RX)
959 "z" 3 bit register (MIPS16OP_*_RZ)
960 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
961 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
962 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
963 "0" zero register ($0)
964 "S" stack pointer ($sp or $29)
965 "P" program counter
966 "R" return address register ($ra or $31)
967 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
968 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
969 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
970 "a" 26 bit jump address
971 "e" 11 bit extension value
972 "l" register list for entry instruction
973 "L" register list for exit instruction
974
975 The remaining codes may be extended. Except as otherwise noted,
976 the full extended operand is a 16 bit signed value.
977 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
978 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
979 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
980 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
981 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
982 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
983 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
984 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
985 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
986 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
987 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
988 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
989 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
990 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
991 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
992 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
993 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
994 "q" 11 bit branch address (MIPS16OP_*_IMM11)
995 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
996 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
997 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
0499d65b
TS		 998 "m" 7 bit register list for save instruction (18 bit extended)
999 "M" 7 bit register list for restore instruction (18 bit extended)
1000 */
1001
1002/* Save/restore encoding for the args field when all 4 registers are
1003 either saved as arguments or saved/restored as statics. */
1004#define MIPS16_ALL_ARGS 0xe
1005#define MIPS16_ALL_STATICS 0xb
252b5132
RH		 1006
1007/* For the mips16, we use the same opcode table format and a few of
1008 the same flags. However, most of the flags are different. */
1009
1010/* Modifies the register in MIPS16OP_*_RX. */
1011#define MIPS16_INSN_WRITE_X 0x00000001
1012/* Modifies the register in MIPS16OP_*_RY. */
1013#define MIPS16_INSN_WRITE_Y 0x00000002
1014/* Modifies the register in MIPS16OP_*_RZ. */
1015#define MIPS16_INSN_WRITE_Z 0x00000004
1016/* Modifies the T ($24) register. */
1017#define MIPS16_INSN_WRITE_T 0x00000008
1018/* Modifies the SP ($29) register. */
1019#define MIPS16_INSN_WRITE_SP 0x00000010
1020/* Modifies the RA ($31) register. */
1021#define MIPS16_INSN_WRITE_31 0x00000020
1022/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1023#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1024/* Reads the register in MIPS16OP_*_RX. */
1025#define MIPS16_INSN_READ_X 0x00000080
1026/* Reads the register in MIPS16OP_*_RY. */
1027#define MIPS16_INSN_READ_Y 0x00000100
1028/* Reads the register in MIPS16OP_*_MOVE32Z. */
1029#define MIPS16_INSN_READ_Z 0x00000200
1030/* Reads the T ($24) register. */
1031#define MIPS16_INSN_READ_T 0x00000400
1032/* Reads the SP ($29) register. */
1033#define MIPS16_INSN_READ_SP 0x00000800
1034/* Reads the RA ($31) register. */
1035#define MIPS16_INSN_READ_31 0x00001000
1036/* Reads the program counter. */
1037#define MIPS16_INSN_READ_PC 0x00002000
1038/* Reads the general purpose register in MIPS16OP_*_REGR32. */
1039#define MIPS16_INSN_READ_GPR_X 0x00004000
1040/* Is a branch insn. */
1041#define MIPS16_INSN_BRANCH 0x00010000
1042
1043/* The following flags have the same value for the mips16 opcode
1044 table:
1045 INSN_UNCOND_BRANCH_DELAY
1046 INSN_COND_BRANCH_DELAY
1047 INSN_COND_BRANCH_LIKELY (never used)
1048 INSN_READ_HI
1049 INSN_READ_LO
1050 INSN_WRITE_HI
1051 INSN_WRITE_LO
1052 INSN_TRAP
1053 INSN_ISA3
1054 */
1055
1056extern const struct mips_opcode mips16_opcodes[];
1057extern const int bfd_mips16_num_opcodes;
1058
1059#endif /* _MIPS_H_ */
GDB Binutils - Deliverables
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