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252b5132 | 1 | /* ppc.h -- Header file for PowerPC opcode table |
b84bf58a AM |
2 | Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
3 | 2007 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | ||
6 | This file is part of GDB, GAS, and the GNU binutils. | |
7 | ||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version | |
11 | 1, or (at your option) any later version. | |
12 | ||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the Free | |
e172dbf8 | 20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 RH |
21 | |
22 | #ifndef PPC_H | |
23 | #define PPC_H | |
24 | ||
fa452fa6 PB |
25 | typedef unsigned long ppc_cpu_t; |
26 | ||
252b5132 RH |
27 | /* The opcode table is an array of struct powerpc_opcode. */ |
28 | ||
29 | struct powerpc_opcode | |
30 | { | |
31 | /* The opcode name. */ | |
32 | const char *name; | |
33 | ||
34 | /* The opcode itself. Those bits which will be filled in with | |
35 | operands are zeroes. */ | |
36 | unsigned long opcode; | |
37 | ||
38 | /* The opcode mask. This is used by the disassembler. This is a | |
39 | mask containing ones indicating those bits which must match the | |
40 | opcode field, and zeroes indicating those bits which need not | |
41 | match (and are presumably filled in by operands). */ | |
42 | unsigned long mask; | |
43 | ||
44 | /* One bit flags for the opcode. These are used to indicate which | |
45 | specific processors support the instructions. The defined values | |
46 | are listed below. */ | |
fa452fa6 | 47 | ppc_cpu_t flags; |
252b5132 RH |
48 | |
49 | /* An array of operand codes. Each code is an index into the | |
50 | operand table. They appear in the order which the operands must | |
51 | appear in assembly code, and are terminated by a zero. */ | |
52 | unsigned char operands[8]; | |
53 | }; | |
54 | ||
55 | /* The table itself is sorted by major opcode number, and is otherwise | |
56 | in the order in which the disassembler should consider | |
57 | instructions. */ | |
58 | extern const struct powerpc_opcode powerpc_opcodes[]; | |
59 | extern const int powerpc_num_opcodes; | |
60 | ||
61 | /* Values defined for the flags field of a struct powerpc_opcode. */ | |
62 | ||
63 | /* Opcode is defined for the PowerPC architecture. */ | |
68d23d21 | 64 | #define PPC_OPCODE_PPC 1 |
252b5132 RH |
65 | |
66 | /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
68d23d21 | 67 | #define PPC_OPCODE_POWER 2 |
252b5132 RH |
68 | |
69 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
68d23d21 | 70 | #define PPC_OPCODE_POWER2 4 |
252b5132 RH |
71 | |
72 | /* Opcode is only defined on 32 bit architectures. */ | |
68d23d21 | 73 | #define PPC_OPCODE_32 8 |
252b5132 RH |
74 | |
75 | /* Opcode is only defined on 64 bit architectures. */ | |
68d23d21 | 76 | #define PPC_OPCODE_64 0x10 |
252b5132 RH |
77 | |
78 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 | |
79 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
80 | but it also supports many additional POWER instructions. */ | |
68d23d21 | 81 | #define PPC_OPCODE_601 0x20 |
252b5132 RH |
82 | |
83 | /* Opcode is supported in both the Power and PowerPC architectures | |
84 | (ie, compiler's -mcpu=common or assembler's -mcom). */ | |
68d23d21 | 85 | #define PPC_OPCODE_COMMON 0x40 |
252b5132 RH |
86 | |
87 | /* Opcode is supported for any Power or PowerPC platform (this is | |
88 | for the assembler's -many option, and it eliminates duplicates). */ | |
68d23d21 | 89 | #define PPC_OPCODE_ANY 0x80 |
252b5132 | 90 | |
45c18104 | 91 | /* Opcode is supported as part of the 64-bit bridge. */ |
68d23d21 | 92 | #define PPC_OPCODE_64_BRIDGE 0x100 |
45c18104 | 93 | |
966f959b | 94 | /* Opcode is supported by Altivec Vector Unit */ |
68d23d21 | 95 | #define PPC_OPCODE_ALTIVEC 0x200 |
418c1742 MG |
96 | |
97 | /* Opcode is supported by PowerPC 403 processor. */ | |
68d23d21 | 98 | #define PPC_OPCODE_403 0x400 |
418c1742 | 99 | |
a09cf9bd | 100 | /* Opcode is supported by PowerPC BookE processor. */ |
68d23d21 | 101 | #define PPC_OPCODE_BOOKE 0x800 |
418c1742 | 102 | |
a09cf9bd | 103 | /* Opcode is only supported by 64-bit PowerPC BookE processor. */ |
68d23d21 AM |
104 | #define PPC_OPCODE_BOOKE64 0x1000 |
105 | ||
106 | /* Opcode is supported by PowerPC 440 processor. */ | |
107 | #define PPC_OPCODE_440 0x2000 | |
966f959b | 108 | |
fc1e7121 | 109 | /* Opcode is only supported by Power4 architecture. */ |
68d23d21 | 110 | #define PPC_OPCODE_POWER4 0x4000 |
fc1e7121 AM |
111 | |
112 | /* Opcode isn't supported by Power4 architecture. */ | |
68d23d21 | 113 | #define PPC_OPCODE_NOPOWER4 0x8000 |
fc1e7121 | 114 | |
0449635d | 115 | /* Opcode is only supported by POWERPC Classic architecture. */ |
68d23d21 | 116 | #define PPC_OPCODE_CLASSIC 0x10000 |
0449635d EZ |
117 | |
118 | /* Opcode is only supported by e500x2 Core. */ | |
68d23d21 | 119 | #define PPC_OPCODE_SPE 0x20000 |
0449635d EZ |
120 | |
121 | /* Opcode is supported by e500x2 Integer select APU. */ | |
68d23d21 | 122 | #define PPC_OPCODE_ISEL 0x40000 |
0449635d EZ |
123 | |
124 | /* Opcode is an e500 SPE floating point instruction. */ | |
68d23d21 | 125 | #define PPC_OPCODE_EFS 0x80000 |
0449635d EZ |
126 | |
127 | /* Opcode is supported by branch locking APU. */ | |
68d23d21 | 128 | #define PPC_OPCODE_BRLOCK 0x100000 |
0449635d EZ |
129 | |
130 | /* Opcode is supported by performance monitor APU. */ | |
68d23d21 | 131 | #define PPC_OPCODE_PMR 0x200000 |
0449635d EZ |
132 | |
133 | /* Opcode is supported by cache locking APU. */ | |
68d23d21 | 134 | #define PPC_OPCODE_CACHELCK 0x400000 |
0449635d EZ |
135 | |
136 | /* Opcode is supported by machine check APU. */ | |
68d23d21 | 137 | #define PPC_OPCODE_RFMCI 0x800000 |
0449635d | 138 | |
f4411256 | 139 | /* Opcode is only supported by Power5 architecture. */ |
9622b051 | 140 | #define PPC_OPCODE_POWER5 0x1000000 |
f4411256 | 141 | |
36ae0db3 | 142 | /* Opcode is supported by PowerPC e300 family. */ |
9622b051 AM |
143 | #define PPC_OPCODE_E300 0x2000000 |
144 | ||
145 | /* Opcode is only supported by Power6 architecture. */ | |
146 | #define PPC_OPCODE_POWER6 0x4000000 | |
147 | ||
ede602d7 AM |
148 | /* Opcode is only supported by PowerPC Cell family. */ |
149 | #define PPC_OPCODE_CELL 0x8000000 | |
36ae0db3 | 150 | |
c3d65c1c BE |
151 | /* Opcode is supported by CPUs with paired singles support. */ |
152 | #define PPC_OPCODE_PPCPS 0x10000000 | |
153 | ||
19a6653c AM |
154 | /* Opcode is supported by Power E500MC */ |
155 | #define PPC_OPCODE_E500MC 0x20000000 | |
156 | ||
252b5132 RH |
157 | /* A macro to extract the major opcode from an instruction. */ |
158 | #define PPC_OP(i) (((i) >> 26) & 0x3f) | |
159 | \f | |
160 | /* The operands table is an array of struct powerpc_operand. */ | |
161 | ||
162 | struct powerpc_operand | |
163 | { | |
b84bf58a AM |
164 | /* A bitmask of bits in the operand. */ |
165 | unsigned int bitm; | |
252b5132 | 166 | |
b84bf58a AM |
167 | /* How far the operand is left shifted in the instruction. |
168 | -1 to indicate that BITM and SHIFT cannot be used to determine | |
169 | where the operand goes in the insn. */ | |
252b5132 RH |
170 | int shift; |
171 | ||
172 | /* Insertion function. This is used by the assembler. To insert an | |
173 | operand value into an instruction, check this field. | |
174 | ||
175 | If it is NULL, execute | |
b84bf58a | 176 | i |= (op & o->bitm) << o->shift; |
252b5132 | 177 | (i is the instruction which we are filling in, o is a pointer to |
b84bf58a | 178 | this structure, and op is the operand value). |
252b5132 RH |
179 | |
180 | If this field is not NULL, then simply call it with the | |
181 | instruction and the operand value. It will return the new value | |
182 | of the instruction. If the ERRMSG argument is not NULL, then if | |
183 | the operand value is illegal, *ERRMSG will be set to a warning | |
184 | string (the operand will be inserted in any case). If the | |
185 | operand value is legal, *ERRMSG will be unchanged (most operands | |
186 | can accept any value). */ | |
8cf3f354 | 187 | unsigned long (*insert) |
fa452fa6 | 188 | (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); |
252b5132 RH |
189 | |
190 | /* Extraction function. This is used by the disassembler. To | |
191 | extract this operand type from an instruction, check this field. | |
192 | ||
193 | If it is NULL, compute | |
b84bf58a AM |
194 | op = (i >> o->shift) & o->bitm; |
195 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) | |
196 | sign_extend (op); | |
252b5132 | 197 | (i is the instruction, o is a pointer to this structure, and op |
b84bf58a | 198 | is the result). |
252b5132 RH |
199 | |
200 | If this field is not NULL, then simply call it with the | |
201 | instruction value. It will return the value of the operand. If | |
202 | the INVALID argument is not NULL, *INVALID will be set to | |
203 | non-zero if this operand type can not actually be extracted from | |
204 | this operand (i.e., the instruction does not match). If the | |
205 | operand is valid, *INVALID will not be changed. */ | |
fa452fa6 | 206 | long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); |
252b5132 RH |
207 | |
208 | /* One bit syntax flags. */ | |
209 | unsigned long flags; | |
210 | }; | |
211 | ||
212 | /* Elements in the table are retrieved by indexing with values from | |
213 | the operands field of the powerpc_opcodes table. */ | |
214 | ||
215 | extern const struct powerpc_operand powerpc_operands[]; | |
b84bf58a | 216 | extern const unsigned int num_powerpc_operands; |
252b5132 RH |
217 | |
218 | /* Values defined for the flags field of a struct powerpc_operand. */ | |
219 | ||
220 | /* This operand takes signed values. */ | |
b84bf58a | 221 | #define PPC_OPERAND_SIGNED (0x1) |
252b5132 RH |
222 | |
223 | /* This operand takes signed values, but also accepts a full positive | |
224 | range of values when running in 32 bit mode. That is, if bits is | |
225 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
226 | this flag is ignored. */ | |
b84bf58a | 227 | #define PPC_OPERAND_SIGNOPT (0x2) |
252b5132 RH |
228 | |
229 | /* This operand does not actually exist in the assembler input. This | |
230 | is used to support extended mnemonics such as mr, for which two | |
231 | operands fields are identical. The assembler should call the | |
232 | insert function with any op value. The disassembler should call | |
233 | the extract function, ignore the return value, and check the value | |
234 | placed in the valid argument. */ | |
b84bf58a | 235 | #define PPC_OPERAND_FAKE (0x4) |
252b5132 RH |
236 | |
237 | /* The next operand should be wrapped in parentheses rather than | |
238 | separated from this one by a comma. This is used for the load and | |
239 | store instructions which want their operands to look like | |
240 | reg,displacement(reg) | |
241 | */ | |
b84bf58a | 242 | #define PPC_OPERAND_PARENS (0x8) |
252b5132 RH |
243 | |
244 | /* This operand may use the symbolic names for the CR fields, which | |
245 | are | |
246 | lt 0 gt 1 eq 2 so 3 un 3 | |
247 | cr0 0 cr1 1 cr2 2 cr3 3 | |
248 | cr4 4 cr5 5 cr6 6 cr7 7 | |
249 | These may be combined arithmetically, as in cr2*4+gt. These are | |
250 | only supported on the PowerPC, not the POWER. */ | |
b84bf58a | 251 | #define PPC_OPERAND_CR (0x10) |
252b5132 RH |
252 | |
253 | /* This operand names a register. The disassembler uses this to print | |
254 | register names with a leading 'r'. */ | |
b84bf58a | 255 | #define PPC_OPERAND_GPR (0x20) |
252b5132 | 256 | |
fdd12ef3 | 257 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
b84bf58a | 258 | #define PPC_OPERAND_GPR_0 (0x40) |
fdd12ef3 | 259 | |
252b5132 RH |
260 | /* This operand names a floating point register. The disassembler |
261 | prints these with a leading 'f'. */ | |
b84bf58a | 262 | #define PPC_OPERAND_FPR (0x80) |
252b5132 RH |
263 | |
264 | /* This operand is a relative branch displacement. The disassembler | |
265 | prints these symbolically if possible. */ | |
b84bf58a | 266 | #define PPC_OPERAND_RELATIVE (0x100) |
252b5132 RH |
267 | |
268 | /* This operand is an absolute branch address. The disassembler | |
269 | prints these symbolically if possible. */ | |
b84bf58a | 270 | #define PPC_OPERAND_ABSOLUTE (0x200) |
252b5132 RH |
271 | |
272 | /* This operand is optional, and is zero if omitted. This is used for | |
2a309db0 | 273 | example, in the optional BF field in the comparison instructions. The |
252b5132 RH |
274 | assembler must count the number of operands remaining on the line, |
275 | and the number of operands remaining for the opcode, and decide | |
276 | whether this operand is present or not. The disassembler should | |
277 | print this operand out only if it is not zero. */ | |
b84bf58a | 278 | #define PPC_OPERAND_OPTIONAL (0x400) |
252b5132 RH |
279 | |
280 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand | |
281 | is omitted, then for the next operand use this operand value plus | |
282 | 1, ignoring the next operand field for the opcode. This wretched | |
283 | hack is needed because the Power rotate instructions can take | |
284 | either 4 or 5 operands. The disassembler should print this operand | |
285 | out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
b84bf58a | 286 | #define PPC_OPERAND_NEXT (0x800) |
252b5132 RH |
287 | |
288 | /* This operand should be regarded as a negative number for the | |
289 | purposes of overflow checking (i.e., the normal most negative | |
290 | number is disallowed and one more than the normal most positive | |
291 | number is allowed). This flag will only be set for a signed | |
292 | operand. */ | |
b84bf58a | 293 | #define PPC_OPERAND_NEGATIVE (0x1000) |
966f959b C |
294 | |
295 | /* This operand names a vector unit register. The disassembler | |
296 | prints these with a leading 'v'. */ | |
b84bf58a | 297 | #define PPC_OPERAND_VR (0x2000) |
966f959b | 298 | |
a6959011 | 299 | /* This operand is for the DS field in a DS form instruction. */ |
b84bf58a | 300 | #define PPC_OPERAND_DS (0x4000) |
adadcc0c AM |
301 | |
302 | /* This operand is for the DQ field in a DQ form instruction. */ | |
b84bf58a AM |
303 | #define PPC_OPERAND_DQ (0x8000) |
304 | ||
3896c469 | 305 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
b84bf58a | 306 | #define PPC_OPERAND_PLUS1 (0x10000) |
252b5132 RH |
307 | \f |
308 | /* The POWER and PowerPC assemblers use a few macros. We keep them | |
309 | with the operands table for simplicity. The macro table is an | |
310 | array of struct powerpc_macro. */ | |
311 | ||
312 | struct powerpc_macro | |
313 | { | |
314 | /* The macro name. */ | |
315 | const char *name; | |
316 | ||
317 | /* The number of operands the macro takes. */ | |
318 | unsigned int operands; | |
319 | ||
320 | /* One bit flags for the opcode. These are used to indicate which | |
321 | specific processors support the instructions. The values are the | |
322 | same as those for the struct powerpc_opcode flags field. */ | |
fa452fa6 | 323 | ppc_cpu_t flags; |
252b5132 RH |
324 | |
325 | /* A format string to turn the macro into a normal instruction. | |
326 | Each %N in the string is replaced with operand number N (zero | |
327 | based). */ | |
328 | const char *format; | |
329 | }; | |
330 | ||
331 | extern const struct powerpc_macro powerpc_macros[]; | |
332 | extern const int powerpc_num_macros; | |
333 | ||
334 | #endif /* PPC_H */ |