[deliverable/binutils-gdb.git] / include / opcode / ppc.h

/* ppc.h -- Header file for PowerPC opcode table
   Copyright (C) 1994-2016 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version 3,
   or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING3.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef PPC_H
#define PPC_H

#include "bfd_stdint.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef uint64_t ppc_cpu_t;

/* The opcode table is an array of struct powerpc_opcode.  */

struct powerpc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned long opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned long mask;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The defined values
     are listed below.  */
  ppc_cpu_t flags;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors no longer support the instructions.  The defined
     values are listed below.  */
  ppc_cpu_t deprecated;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[8];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const int vle_num_opcodes;

/* Values defined for the flags field of a struct powerpc_opcode.  */

/* Opcode is defined for the PowerPC architecture.  */
#define PPC_OPCODE_PPC			 1

/* Opcode is defined for the POWER (RS/6000) architecture.  */
#define PPC_OPCODE_POWER		 2

/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
#define PPC_OPCODE_POWER2		 4

/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
   but it also supports many additional POWER instructions.  */
#define PPC_OPCODE_601			 8

/* Opcode is supported in both the Power and PowerPC architectures
   (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
   the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
   and PPC_OPCODE_POWER2 because many instructions changed mnemonics
   between POWER and POWERPC.  */
#define PPC_OPCODE_COMMON	      0x10

/* Opcode is supported for any Power or PowerPC platform (this is
   for the assembler's -many option, and it eliminates duplicates).  */
#define PPC_OPCODE_ANY		      0x20

/* Opcode is only defined on 64 bit architectures.  */
#define PPC_OPCODE_64		      0x40

/* Opcode is supported as part of the 64-bit bridge.  */
#define PPC_OPCODE_64_BRIDGE	      0x80

/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC	     0x100

/* Opcode is supported by PowerPC 403 processor.  */
#define PPC_OPCODE_403		     0x200

/* Opcode is supported by PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE	     0x400

/* Opcode is supported by PowerPC 440 processor.  */
#define PPC_OPCODE_440		     0x800

/* Opcode is only supported by Power4 architecture.  */
#define PPC_OPCODE_POWER4	    0x1000

/* Opcode is only supported by Power7 architecture.  */
#define PPC_OPCODE_POWER7	    0x2000

/* Opcode is only supported by e500x2 Core.  */
#define PPC_OPCODE_SPE		    0x4000

/* Opcode is supported by e500x2 Integer select APU.  */
#define PPC_OPCODE_ISEL		    0x8000

/* Opcode is an e500 SPE floating point instruction.  */
#define PPC_OPCODE_EFS		   0x10000

/* Opcode is supported by branch locking APU.  */
#define PPC_OPCODE_BRLOCK	   0x20000

/* Opcode is supported by performance monitor APU.  */
#define PPC_OPCODE_PMR		   0x40000

/* Opcode is supported by cache locking APU.  */
#define PPC_OPCODE_CACHELCK	   0x80000

/* Opcode is supported by machine check APU.  */
#define PPC_OPCODE_RFMCI	  0x100000

/* Opcode is only supported by Power5 architecture.  */
#define PPC_OPCODE_POWER5	  0x200000

/* Opcode is supported by PowerPC e300 family.  */
#define PPC_OPCODE_E300           0x400000

/* Opcode is only supported by Power6 architecture.  */
#define PPC_OPCODE_POWER6	  0x800000

/* Opcode is only supported by PowerPC Cell family.  */
#define PPC_OPCODE_CELL		 0x1000000

/* Opcode is supported by CPUs with paired singles support.  */
#define PPC_OPCODE_PPCPS	 0x2000000

/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC        0x4000000

/* Opcode is supported by PowerPC 405 processor.  */
#define PPC_OPCODE_405		 0x8000000

/* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX		0x10000000

/* Opcode is supported by A2.  */
#define PPC_OPCODE_A2	 	0x20000000

/* Opcode is supported by PowerPC 476 processor.  */
#define PPC_OPCODE_476		0x40000000

/* Opcode is supported by AppliedMicro Titan core */
#define PPC_OPCODE_TITAN        0x80000000

/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500	       0x100000000ull

/* Opcode is supported by Extended Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC2    0x200000000ull

/* Opcode is supported by Power E6500 */
#define PPC_OPCODE_E6500       0x400000000ull

/* Opcode is supported by Thread management APU */
#define PPC_OPCODE_TMR         0x800000000ull

/* Opcode which is supported by the VLE extension.  */
#define PPC_OPCODE_VLE	      0x1000000000ull

/* Opcode is only supported by Power8 architecture.  */
#define PPC_OPCODE_POWER8     0x2000000000ull

/* Opcode which is supported by the Hardware Transactional Memory extension.  */
/* Currently, this is the same as the POWER8 mask.  If another cpu comes out
   that isn't a superset of POWER8, we can define this to its own mask.  */
#define PPC_OPCODE_HTM        PPC_OPCODE_POWER8

/* Opcode is supported by ppc750cl.  */
#define PPC_OPCODE_750	      0x4000000000ull

/* Opcode is supported by ppc7450.  */
#define PPC_OPCODE_7450	      0x8000000000ull

/* Opcode is supported by ppc821/850/860.  */
#define PPC_OPCODE_860	      0x10000000000ull

/* Opcode is only supported by Power9 architecture.  */
#define PPC_OPCODE_POWER9     0x20000000000ull

/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
#define PPC_OPCODE_VSX3       0x40000000000ull

/* A macro to extract the major opcode from an instruction.  */
#define PPC_OP(i) (((i) >> 26) & 0x3f)

/* A macro to determine if the instruction is a 2-byte VLE insn.  */
#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)

/* A macro to extract the major opcode from a VLE instruction.  */
#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)

/* A macro to convert a VLE opcode to a VLE opcode segment.  */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
\f
/* The operands table is an array of struct powerpc_operand.  */

struct powerpc_operand
{
  /* A bitmask of bits in the operand.  */
  unsigned int bitm;

  /* The shift operation to be applied to the operand.  No shift
     is made if this is zero.  For positive values, the operand
     is shifted left by SHIFT.  For negative values, the operand
     is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
     that BITM and SHIFT cannot be used to determine where the
     operand goes in the insn.  */
  int shift;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 if (o->shift >= 0)
	   i |= (op & o->bitm) << o->shift;
	 else
	   i |= (op & o->bitm) >> -o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the operand value).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.  It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).  If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned long (*insert)
    (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 if (o->shift >= 0)
	   op = (i >> o->shift) & o->bitm;
	 else
	   op = (i << -o->shift) & o->bitm;
	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
	   sign_extend (op);
     (i is the instruction, o is a pointer to this structure, and op
     is the result).

     If this field is not NULL, then simply call it with the
     instruction value.  It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     non-zero if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);

  /* One bit syntax flags.  */
  unsigned long flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the powerpc_opcodes table.  */

extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;

/* Use with the shift field of a struct powerpc_operand to indicate
     that BITM and SHIFT cannot be used to determine where the operand
     goes in the insn.  */
#define PPC_OPSHIFT_INV (-1U << 31)

/* Values defined for the flags field of a struct powerpc_operand.  */

/* This operand takes signed values.  */
#define PPC_OPERAND_SIGNED (0x1)

/* This operand takes signed values, but also accepts a full positive
   range of values when running in 32 bit mode.  That is, if bits is
   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
   this flag is ignored.  */
#define PPC_OPERAND_SIGNOPT (0x2)

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics such as mr, for which two
   operands fields are identical.  The assembler should call the
   insert function with any op value.  The disassembler should call
   the extract function, ignore the return value, and check the value
   placed in the valid argument.  */
#define PPC_OPERAND_FAKE (0x4)

/* The next operand should be wrapped in parentheses rather than
   separated from this one by a comma.  This is used for the load and
   store instructions which want their operands to look like
       reg,displacement(reg)
   */
#define PPC_OPERAND_PARENS (0x8)

/* This operand may use the symbolic names for the CR fields, which
   are
       lt  0	gt  1	eq  2	so  3	un  3
       cr0 0	cr1 1	cr2 2	cr3 3
       cr4 4	cr5 5	cr6 6	cr7 7
   These may be combined arithmetically, as in cr2*4+gt.  These are
   only supported on the PowerPC, not the POWER.  */
#define PPC_OPERAND_CR_BIT (0x10)

/* This operand names a register.  The disassembler uses this to print
   register names with a leading 'r'.  */
#define PPC_OPERAND_GPR (0x20)

/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
#define PPC_OPERAND_GPR_0 (0x40)

/* This operand names a floating point register.  The disassembler
   prints these with a leading 'f'.  */
#define PPC_OPERAND_FPR (0x80)

/* This operand is a relative branch displacement.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_RELATIVE (0x100)

/* This operand is an absolute branch address.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_ABSOLUTE (0x200)

/* This operand is optional, and is zero if omitted.  This is used for
   example, in the optional BF field in the comparison instructions.  The
   assembler must count the number of operands remaining on the line,
   and the number of operands remaining for the opcode, and decide
   whether this operand is present or not.  The disassembler should
   print this operand out only if it is not zero.  */
#define PPC_OPERAND_OPTIONAL (0x400)

/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
   is omitted, then for the next operand use this operand value plus
   1, ignoring the next operand field for the opcode.  This wretched
   hack is needed because the Power rotate instructions can take
   either 4 or 5 operands.  The disassembler should print this operand
   out regardless of the PPC_OPERAND_OPTIONAL field.  */
#define PPC_OPERAND_NEXT (0x800)

/* This operand should be regarded as a negative number for the
   purposes of overflow checking (i.e., the normal most negative
   number is disallowed and one more than the normal most positive
   number is allowed).  This flag will only be set for a signed
   operand.  */
#define PPC_OPERAND_NEGATIVE (0x1000)

/* This operand names a vector unit register.  The disassembler
   prints these with a leading 'v'.  */
#define PPC_OPERAND_VR (0x2000)

/* This operand is for the DS field in a DS form instruction.  */
#define PPC_OPERAND_DS (0x4000)

/* This operand is for the DQ field in a DQ form instruction.  */
#define PPC_OPERAND_DQ (0x8000)

/* Valid range of operand is 0..n rather than 0..n-1.  */
#define PPC_OPERAND_PLUS1 (0x10000)

/* Xilinx APU and FSL related operands */
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)

/* This operand names a vector-scalar unit register.  The disassembler
   prints these with a leading 'vs'.  */
#define PPC_OPERAND_VSR (0x100000)

/* This is a CR FIELD that does not use symbolic names.  */
#define PPC_OPERAND_CR_REG (0x200000)

/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
   is omitted, then the value it should use for the operand is stored
   in the SHIFT field of the immediatly following operand field.  */
#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
\f
/* The POWER and PowerPC assemblers use a few macros.  We keep them
   with the operands table for simplicity.  The macro table is an
   array of struct powerpc_macro.  */

struct powerpc_macro
{
  /* The macro name.  */
  const char *name;

  /* The number of operands the macro takes.  */
  unsigned int operands;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The values are the
     same as those for the struct powerpc_opcode flags field.  */
  ppc_cpu_t flags;

  /* A format string to turn the macro into a normal instruction.
     Each %N in the string is replaced with operand number N (zero
     based).  */
  const char *format;
};

extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;

extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);

static inline long
ppc_optional_operand_value (const struct powerpc_operand *operand)
{
  if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
    return (operand+1)->shift;
  return 0;
}

#ifdef __cplusplus
}
#endif

#endif /* PPC_H */
Commit	Line	Data
252b5132	1	/* ppc.h -- Header file for PowerPC opcode table
6f2750fe	2	Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132 RH	3	Written by Ian Lance Taylor, Cygnus Support
252b5132 RH	4
e4e42b45 NC	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version 3,
	10	or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING3. If not, write to the Free
	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
252b5132 RH	21
	22	#ifndef PPC_H
	23	#define PPC_H
	24
b961e85b AM	25	#include "bfd_stdint.h"
b961e85b AM	26
1fe0971e TS	27	#ifdef __cplusplus
	28	extern "C" {
	29	#endif
	30
b961e85b	31	typedef uint64_t ppc_cpu_t;
fa452fa6	32
252b5132 RH	33	/* The opcode table is an array of struct powerpc_opcode. */
	34
	35	struct powerpc_opcode
	36	{
	37	/* The opcode name. */
	38	const char *name;
	39
	40	/* The opcode itself. Those bits which will be filled in with
	41	operands are zeroes. */
	42	unsigned long opcode;
	43
	44	/* The opcode mask. This is used by the disassembler. This is a
	45	mask containing ones indicating those bits which must match the
	46	opcode field, and zeroes indicating those bits which need not
	47	match (and are presumably filled in by operands). */
	48	unsigned long mask;
	49
	50	/* One bit flags for the opcode. These are used to indicate which
	51	specific processors support the instructions. The defined values
	52	are listed below. */
fa452fa6	53	ppc_cpu_t flags;
252b5132	54
1cb0a767 PB	55	/* One bit flags for the opcode. These are used to indicate which
	56	specific processors no longer support the instructions. The defined
	57	values are listed below. */
	58	ppc_cpu_t deprecated;
	59
252b5132 RH	60	/* An array of operand codes. Each code is an index into the
	61	operand table. They appear in the order which the operands must
	62	appear in assembly code, and are terminated by a zero. */
	63	unsigned char operands[8];
	64	};
	65
	66	/* The table itself is sorted by major opcode number, and is otherwise
	67	in the order in which the disassembler should consider
	68	instructions. */
	69	extern const struct powerpc_opcode powerpc_opcodes[];
	70	extern const int powerpc_num_opcodes;
b9c361e0 JL	71	extern const struct powerpc_opcode vle_opcodes[];
b9c361e0 JL	72	extern const int vle_num_opcodes;
252b5132 RH	73
	74	/* Values defined for the flags field of a struct powerpc_opcode. */
	75
	76	/* Opcode is defined for the PowerPC architecture. */
68d23d21	77	#define PPC_OPCODE_PPC 1
252b5132 RH	78
252b5132 RH	79	/* Opcode is defined for the POWER (RS/6000) architecture. */
68d23d21	80	#define PPC_OPCODE_POWER 2
252b5132 RH	81
252b5132 RH	82	/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68d23d21	83	#define PPC_OPCODE_POWER2 4
252b5132	84
252b5132 RH	85	/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
	86	is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
	87	but it also supports many additional POWER instructions. */
bdc70b4a	88	#define PPC_OPCODE_601 8
252b5132 RH	89
252b5132 RH	90	/* Opcode is supported in both the Power and PowerPC architectures
f2bae120 AM	91	(ie, compiler's -mcpu=common or assembler's -mcom). More than just
	92	the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
	93	and PPC_OPCODE_POWER2 because many instructions changed mnemonics
	94	between POWER and POWERPC. */
bdc70b4a	95	#define PPC_OPCODE_COMMON 0x10
252b5132 RH	96
	97	/* Opcode is supported for any Power or PowerPC platform (this is
	98	for the assembler's -many option, and it eliminates duplicates). */
bdc70b4a AM	99	#define PPC_OPCODE_ANY 0x20
	100
	101	/* Opcode is only defined on 64 bit architectures. */
	102	#define PPC_OPCODE_64 0x40
252b5132	103
45c18104	104	/* Opcode is supported as part of the 64-bit bridge. */
bdc70b4a	105	#define PPC_OPCODE_64_BRIDGE 0x80
45c18104	106
966f959b	107	/* Opcode is supported by Altivec Vector Unit */
bdc70b4a	108	#define PPC_OPCODE_ALTIVEC 0x100
418c1742 MG	109
418c1742 MG	110	/* Opcode is supported by PowerPC 403 processor. */
bdc70b4a	111	#define PPC_OPCODE_403 0x200
418c1742	112
a09cf9bd	113	/* Opcode is supported by PowerPC BookE processor. */
bdc70b4a	114	#define PPC_OPCODE_BOOKE 0x400
68d23d21 AM	115
68d23d21 AM	116	/* Opcode is supported by PowerPC 440 processor. */
bdc70b4a	117	#define PPC_OPCODE_440 0x800
966f959b	118
fc1e7121	119	/* Opcode is only supported by Power4 architecture. */
bdc70b4a	120	#define PPC_OPCODE_POWER4 0x1000
fc1e7121	121
066be9f7	122	/* Opcode is only supported by Power7 architecture. */
bdc70b4a	123	#define PPC_OPCODE_POWER7 0x2000
0449635d EZ	124
0449635d EZ	125	/* Opcode is only supported by e500x2 Core. */
bdc70b4a	126	#define PPC_OPCODE_SPE 0x4000
0449635d EZ	127
0449635d EZ	128	/* Opcode is supported by e500x2 Integer select APU. */
bdc70b4a	129	#define PPC_OPCODE_ISEL 0x8000
0449635d EZ	130
0449635d EZ	131	/* Opcode is an e500 SPE floating point instruction. */
bdc70b4a	132	#define PPC_OPCODE_EFS 0x10000
0449635d EZ	133
0449635d EZ	134	/* Opcode is supported by branch locking APU. */
bdc70b4a	135	#define PPC_OPCODE_BRLOCK 0x20000
0449635d EZ	136
0449635d EZ	137	/* Opcode is supported by performance monitor APU. */
bdc70b4a	138	#define PPC_OPCODE_PMR 0x40000
0449635d EZ	139
0449635d EZ	140	/* Opcode is supported by cache locking APU. */
bdc70b4a	141	#define PPC_OPCODE_CACHELCK 0x80000
0449635d EZ	142
0449635d EZ	143	/* Opcode is supported by machine check APU. */
bdc70b4a	144	#define PPC_OPCODE_RFMCI 0x100000
0449635d	145
f4411256	146	/* Opcode is only supported by Power5 architecture. */
bdc70b4a	147	#define PPC_OPCODE_POWER5 0x200000
f4411256	148
36ae0db3	149	/* Opcode is supported by PowerPC e300 family. */
bdc70b4a	150	#define PPC_OPCODE_E300 0x400000
9622b051 AM	151
9622b051 AM	152	/* Opcode is only supported by Power6 architecture. */
bdc70b4a	153	#define PPC_OPCODE_POWER6 0x800000
9622b051	154
ede602d7	155	/* Opcode is only supported by PowerPC Cell family. */
bdc70b4a	156	#define PPC_OPCODE_CELL 0x1000000
36ae0db3	157
c3d65c1c	158	/* Opcode is supported by CPUs with paired singles support. */
bdc70b4a	159	#define PPC_OPCODE_PPCPS 0x2000000
c3d65c1c	160
19a6653c	161	/* Opcode is supported by Power E500MC */
bdc70b4a	162	#define PPC_OPCODE_E500MC 0x4000000
19a6653c	163
081ba1b3	164	/* Opcode is supported by PowerPC 405 processor. */
bdc70b4a	165	#define PPC_OPCODE_405 0x8000000
081ba1b3	166
9b4e5766	167	/* Opcode is supported by Vector-Scalar (VSX) Unit */
bdc70b4a	168	#define PPC_OPCODE_VSX 0x10000000
9b4e5766	169
e0d602ec	170	/* Opcode is supported by A2. */
bdc70b4a	171	#define PPC_OPCODE_A2 0x20000000
e0d602ec	172
9fe54b1c	173	/* Opcode is supported by PowerPC 476 processor. */
bdc70b4a	174	#define PPC_OPCODE_476 0x40000000
9fe54b1c	175
ce3d2015	176	/* Opcode is supported by AppliedMicro Titan core */
bdc70b4a	177	#define PPC_OPCODE_TITAN 0x80000000
ce3d2015	178
e01d869a	179	/* Opcode which is supported by the e500 family */
bdc70b4a	180	#define PPC_OPCODE_E500 0x100000000ull
e01d869a	181
aea77599 AM	182	/* Opcode is supported by Extended Altivec Vector Unit */
	183	#define PPC_OPCODE_ALTIVEC2 0x200000000ull
	184
	185	/* Opcode is supported by Power E6500 */
	186	#define PPC_OPCODE_E6500 0x400000000ull
	187
	188	/* Opcode is supported by Thread management APU */
	189	#define PPC_OPCODE_TMR 0x800000000ull
	190
b9c361e0 JL	191	/* Opcode which is supported by the VLE extension. */
	192	#define PPC_OPCODE_VLE 0x1000000000ull
	193
5817ffd1 PB	194	/* Opcode is only supported by Power8 architecture. */
	195	#define PPC_OPCODE_POWER8 0x2000000000ull
	196
	197	/* Opcode which is supported by the Hardware Transactional Memory extension. */
	198	/* Currently, this is the same as the POWER8 mask. If another cpu comes out
	199	that isn't a superset of POWER8, we can define this to its own mask. */
	200	#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
	201
ef5a96d5 AM	202	/* Opcode is supported by ppc750cl. */
	203	#define PPC_OPCODE_750 0x4000000000ull
	204
	205	/* Opcode is supported by ppc7450. */
	206	#define PPC_OPCODE_7450 0x8000000000ull
	207
	208	/* Opcode is supported by ppc821/850/860. */
	209	#define PPC_OPCODE_860 0x10000000000ull
	210
a680de9a PB	211	/* Opcode is only supported by Power9 architecture. */
	212	#define PPC_OPCODE_POWER9 0x20000000000ull
	213
	214	/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
	215	#define PPC_OPCODE_VSX3 0x40000000000ull
	216
252b5132 RH	217	/* A macro to extract the major opcode from an instruction. */
252b5132 RH	218	#define PPC_OP(i) (((i) >> 26) & 0x3f)
b9c361e0 JL	219
	220	/* A macro to determine if the instruction is a 2-byte VLE insn. */
	221	#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
	222
	223	/* A macro to extract the major opcode from a VLE instruction. */
	224	#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
	225
	226	/* A macro to convert a VLE opcode to a VLE opcode segment. */
	227	#define VLE_OP_TO_SEG(i) ((i) >> 1)
252b5132 RH	228	\f
	229	/* The operands table is an array of struct powerpc_operand. */
	230
	231	struct powerpc_operand
	232	{
b84bf58a AM	233	/* A bitmask of bits in the operand. */
b84bf58a AM	234	unsigned int bitm;
252b5132	235
b9c361e0 JL	236	/* The shift operation to be applied to the operand. No shift
	237	is made if this is zero. For positive values, the operand
	238	is shifted left by SHIFT. For negative values, the operand
	239	is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
	240	that BITM and SHIFT cannot be used to determine where the
	241	operand goes in the insn. */
252b5132 RH	242	int shift;
	243
	244	/* Insertion function. This is used by the assembler. To insert an
	245	operand value into an instruction, check this field.
	246
	247	If it is NULL, execute
b9c361e0 JL	248	if (o->shift >= 0)
	249	i \|= (op & o->bitm) << o->shift;
	250	else
	251	i \|= (op & o->bitm) >> -o->shift;
252b5132	252	(i is the instruction which we are filling in, o is a pointer to
b84bf58a	253	this structure, and op is the operand value).
252b5132 RH	254
	255	If this field is not NULL, then simply call it with the
	256	instruction and the operand value. It will return the new value
	257	of the instruction. If the ERRMSG argument is not NULL, then if
	258	the operand value is illegal, *ERRMSG will be set to a warning
	259	string (the operand will be inserted in any case). If the
	260	operand value is legal, *ERRMSG will be unchanged (most operands
	261	can accept any value). */
8cf3f354	262	unsigned long (*insert)
fa452fa6	263	(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
252b5132 RH	264
	265	/* Extraction function. This is used by the disassembler. To
	266	extract this operand type from an instruction, check this field.
	267
	268	If it is NULL, compute
b9c361e0 JL	269	if (o->shift >= 0)
	270	op = (i >> o->shift) & o->bitm;
	271	else
	272	op = (i << -o->shift) & o->bitm;
b84bf58a AM	273	if ((o->flags & PPC_OPERAND_SIGNED) != 0)
b84bf58a AM	274	sign_extend (op);
252b5132	275	(i is the instruction, o is a pointer to this structure, and op
b84bf58a	276	is the result).
252b5132 RH	277
	278	If this field is not NULL, then simply call it with the
	279	instruction value. It will return the value of the operand. If
	280	the INVALID argument is not NULL, *INVALID will be set to
	281	non-zero if this operand type can not actually be extracted from
	282	this operand (i.e., the instruction does not match). If the
	283	operand is valid, INVALID will not be changed. /
fa452fa6	284	long (extract) (unsigned long instruction, ppc_cpu_t dialect, int invalid);
252b5132 RH	285
	286	/* One bit syntax flags. */
	287	unsigned long flags;
	288	};
	289
	290	/* Elements in the table are retrieved by indexing with values from
	291	the operands field of the powerpc_opcodes table. */
	292
	293	extern const struct powerpc_operand powerpc_operands[];
b84bf58a	294	extern const unsigned int num_powerpc_operands;
252b5132	295
b9c361e0 JL	296	/* Use with the shift field of a struct powerpc_operand to indicate
	297	that BITM and SHIFT cannot be used to determine where the operand
	298	goes in the insn. */
b6518b38	299	#define PPC_OPSHIFT_INV (-1U << 31)
b9c361e0	300
252b5132 RH	301	/* Values defined for the flags field of a struct powerpc_operand. */
	302
	303	/* This operand takes signed values. */
b84bf58a	304	#define PPC_OPERAND_SIGNED (0x1)
252b5132 RH	305
	306	/* This operand takes signed values, but also accepts a full positive
	307	range of values when running in 32 bit mode. That is, if bits is
	308	16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
	309	this flag is ignored. */
b84bf58a	310	#define PPC_OPERAND_SIGNOPT (0x2)
252b5132 RH	311
	312	/* This operand does not actually exist in the assembler input. This
	313	is used to support extended mnemonics such as mr, for which two
	314	operands fields are identical. The assembler should call the
	315	insert function with any op value. The disassembler should call
	316	the extract function, ignore the return value, and check the value
	317	placed in the valid argument. */
b84bf58a	318	#define PPC_OPERAND_FAKE (0x4)
252b5132 RH	319
	320	/* The next operand should be wrapped in parentheses rather than
	321	separated from this one by a comma. This is used for the load and
	322	store instructions which want their operands to look like
	323	reg,displacement(reg)
	324	*/
b84bf58a	325	#define PPC_OPERAND_PARENS (0x8)
252b5132 RH	326
	327	/* This operand may use the symbolic names for the CR fields, which
	328	are
	329	lt 0 gt 1 eq 2 so 3 un 3
	330	cr0 0 cr1 1 cr2 2 cr3 3
	331	cr4 4 cr5 5 cr6 6 cr7 7
	332	These may be combined arithmetically, as in cr2*4+gt. These are
	333	only supported on the PowerPC, not the POWER. */
b9c361e0	334	#define PPC_OPERAND_CR_BIT (0x10)
252b5132 RH	335
	336	/* This operand names a register. The disassembler uses this to print
	337	register names with a leading 'r'. */
b84bf58a	338	#define PPC_OPERAND_GPR (0x20)
252b5132	339
fdd12ef3	340	/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
b84bf58a	341	#define PPC_OPERAND_GPR_0 (0x40)
fdd12ef3	342
252b5132 RH	343	/* This operand names a floating point register. The disassembler
252b5132 RH	344	prints these with a leading 'f'. */
b84bf58a	345	#define PPC_OPERAND_FPR (0x80)
252b5132 RH	346
	347	/* This operand is a relative branch displacement. The disassembler
	348	prints these symbolically if possible. */
b84bf58a	349	#define PPC_OPERAND_RELATIVE (0x100)
252b5132 RH	350
	351	/* This operand is an absolute branch address. The disassembler
	352	prints these symbolically if possible. */
b84bf58a	353	#define PPC_OPERAND_ABSOLUTE (0x200)
252b5132 RH	354
252b5132 RH	355	/* This operand is optional, and is zero if omitted. This is used for
2a309db0	356	example, in the optional BF field in the comparison instructions. The
252b5132 RH	357	assembler must count the number of operands remaining on the line,
	358	and the number of operands remaining for the opcode, and decide
	359	whether this operand is present or not. The disassembler should
	360	print this operand out only if it is not zero. */
b84bf58a	361	#define PPC_OPERAND_OPTIONAL (0x400)
252b5132 RH	362
	363	/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
	364	is omitted, then for the next operand use this operand value plus
	365	1, ignoring the next operand field for the opcode. This wretched
	366	hack is needed because the Power rotate instructions can take
	367	either 4 or 5 operands. The disassembler should print this operand
	368	out regardless of the PPC_OPERAND_OPTIONAL field. */
b84bf58a	369	#define PPC_OPERAND_NEXT (0x800)
252b5132 RH	370
	371	/* This operand should be regarded as a negative number for the
	372	purposes of overflow checking (i.e., the normal most negative
	373	number is disallowed and one more than the normal most positive
	374	number is allowed). This flag will only be set for a signed
	375	operand. */
b84bf58a	376	#define PPC_OPERAND_NEGATIVE (0x1000)
966f959b C	377
	378	/* This operand names a vector unit register. The disassembler
	379	prints these with a leading 'v'. */
b84bf58a	380	#define PPC_OPERAND_VR (0x2000)
966f959b	381
a6959011	382	/* This operand is for the DS field in a DS form instruction. */
b84bf58a	383	#define PPC_OPERAND_DS (0x4000)
adadcc0c AM	384
adadcc0c AM	385	/* This operand is for the DQ field in a DQ form instruction. */
b84bf58a AM	386	#define PPC_OPERAND_DQ (0x8000)
b84bf58a AM	387
3896c469	388	/* Valid range of operand is 0..n rather than 0..n-1. */
b84bf58a	389	#define PPC_OPERAND_PLUS1 (0x10000)
081ba1b3 AM	390
	391	/* Xilinx APU and FSL related operands */
	392	#define PPC_OPERAND_FSL (0x20000)
	393	#define PPC_OPERAND_FCR (0x40000)
	394	#define PPC_OPERAND_UDI (0x80000)
9b4e5766 PB	395
	396	/* This operand names a vector-scalar unit register. The disassembler
	397	prints these with a leading 'vs'. */
	398	#define PPC_OPERAND_VSR (0x100000)
b9c361e0 JL	399
	400	/* This is a CR FIELD that does not use symbolic names. */
	401	#define PPC_OPERAND_CR_REG (0x200000)
11a0cf2e PB	402
	403	/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
	404	is omitted, then the value it should use for the operand is stored
	405	in the SHIFT field of the immediatly following operand field. */
	406	#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
252b5132 RH	407	\f
	408	/* The POWER and PowerPC assemblers use a few macros. We keep them
	409	with the operands table for simplicity. The macro table is an
	410	array of struct powerpc_macro. */
	411
	412	struct powerpc_macro
	413	{
	414	/* The macro name. */
	415	const char *name;
	416
	417	/* The number of operands the macro takes. */
	418	unsigned int operands;
	419
	420	/* One bit flags for the opcode. These are used to indicate which
	421	specific processors support the instructions. The values are the
	422	same as those for the struct powerpc_opcode flags field. */
fa452fa6	423	ppc_cpu_t flags;
252b5132 RH	424
	425	/* A format string to turn the macro into a normal instruction.
	426	Each %N in the string is replaced with operand number N (zero
	427	based). */
	428	const char *format;
	429	};
	430
	431	extern const struct powerpc_macro powerpc_macros[];
	432	extern const int powerpc_num_macros;
	433
776fc418	434	extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t , const char );
69fe9ce5	435
11a0cf2e PB	436	static inline long
	437	ppc_optional_operand_value (const struct powerpc_operand *operand)
	438	{
	439	if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
	440	return (operand+1)->shift;
	441	return 0;
	442	}
	443
1fe0971e TS	444	#ifdef __cplusplus
	445	}
	446	#endif
	447
252b5132	448	#endif /* PPC_H */