[deliverable/binutils-gdb.git] / include / opcode / ppc.h

/* ppc.h -- Header file for PowerPC opcode table
   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   2007, 2008, 2009 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#ifndef PPC_H
#define PPC_H

typedef unsigned long ppc_cpu_t;

/* The opcode table is an array of struct powerpc_opcode.  */

struct powerpc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned long opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned long mask;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The defined values
     are listed below.  */
  ppc_cpu_t flags;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors no longer support the instructions.  The defined
     values are listed below.  */
  ppc_cpu_t deprecated;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[8];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;

/* Values defined for the flags field of a struct powerpc_opcode.  */

/* Opcode is defined for the PowerPC architecture.  */
#define PPC_OPCODE_PPC			 1

/* Opcode is defined for the POWER (RS/6000) architecture.  */
#define PPC_OPCODE_POWER		 2

/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
#define PPC_OPCODE_POWER2		 4

/* Opcode is only defined on 32 bit architectures.  */
#define PPC_OPCODE_32			 8

/* Opcode is only defined on 64 bit architectures.  */
#define PPC_OPCODE_64		      0x10

/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
   but it also supports many additional POWER instructions.  */
#define PPC_OPCODE_601		      0x20

/* Opcode is supported in both the Power and PowerPC architectures
   (ie, compiler's -mcpu=common or assembler's -mcom).  */
#define PPC_OPCODE_COMMON	      0x40

/* Opcode is supported for any Power or PowerPC platform (this is
   for the assembler's -many option, and it eliminates duplicates).  */
#define PPC_OPCODE_ANY		      0x80

/* Opcode is supported as part of the 64-bit bridge.  */
#define PPC_OPCODE_64_BRIDGE	     0x100

/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC	     0x200

/* Opcode is supported by PowerPC 403 processor.  */
#define PPC_OPCODE_403		     0x400

/* Opcode is supported by PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE	     0x800

/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE64	    0x1000

/* Opcode is supported by PowerPC 440 processor.  */
#define PPC_OPCODE_440		    0x2000

/* Opcode is only supported by Power4 architecture.  */
#define PPC_OPCODE_POWER4	    0x4000

/* Opcode is only supported by Power7 architecture.  */
#define PPC_OPCODE_POWER7	    0x8000

/* Opcode is only supported by POWERPC Classic architecture.  */
#define PPC_OPCODE_CLASSIC	   0x10000

/* Opcode is only supported by e500x2 Core.  */
#define PPC_OPCODE_SPE		   0x20000

/* Opcode is supported by e500x2 Integer select APU.  */
#define PPC_OPCODE_ISEL		   0x40000

/* Opcode is an e500 SPE floating point instruction.  */
#define PPC_OPCODE_EFS		   0x80000

/* Opcode is supported by branch locking APU.  */
#define PPC_OPCODE_BRLOCK	  0x100000

/* Opcode is supported by performance monitor APU.  */
#define PPC_OPCODE_PMR		  0x200000

/* Opcode is supported by cache locking APU.  */
#define PPC_OPCODE_CACHELCK	  0x400000

/* Opcode is supported by machine check APU.  */
#define PPC_OPCODE_RFMCI	  0x800000

/* Opcode is only supported by Power5 architecture.  */
#define PPC_OPCODE_POWER5	 0x1000000

/* Opcode is supported by PowerPC e300 family.  */
#define PPC_OPCODE_E300          0x2000000

/* Opcode is only supported by Power6 architecture.  */
#define PPC_OPCODE_POWER6	 0x4000000

/* Opcode is only supported by PowerPC Cell family.  */
#define PPC_OPCODE_CELL		 0x8000000

/* Opcode is supported by CPUs with paired singles support.  */
#define PPC_OPCODE_PPCPS	 0x10000000

/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC        0x20000000

/* Opcode is supported by PowerPC 405 processor.  */
#define PPC_OPCODE_405		 0x40000000

/* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX		 0x80000000

/* A macro to extract the major opcode from an instruction.  */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
\f
/* The operands table is an array of struct powerpc_operand.  */

struct powerpc_operand
{
  /* A bitmask of bits in the operand.  */
  unsigned int bitm;

  /* How far the operand is left shifted in the instruction.
     -1 to indicate that BITM and SHIFT cannot be used to determine
     where the operand goes in the insn.  */
  int shift;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & o->bitm) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the operand value).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.  It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).  If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned long (*insert)
    (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = (i >> o->shift) & o->bitm;
	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
	   sign_extend (op);
     (i is the instruction, o is a pointer to this structure, and op
     is the result).

     If this field is not NULL, then simply call it with the
     instruction value.  It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     non-zero if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);

  /* One bit syntax flags.  */
  unsigned long flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the powerpc_opcodes table.  */

extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;

/* Values defined for the flags field of a struct powerpc_operand.  */

/* This operand takes signed values.  */
#define PPC_OPERAND_SIGNED (0x1)

/* This operand takes signed values, but also accepts a full positive
   range of values when running in 32 bit mode.  That is, if bits is
   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
   this flag is ignored.  */
#define PPC_OPERAND_SIGNOPT (0x2)

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics such as mr, for which two
   operands fields are identical.  The assembler should call the
   insert function with any op value.  The disassembler should call
   the extract function, ignore the return value, and check the value
   placed in the valid argument.  */
#define PPC_OPERAND_FAKE (0x4)

/* The next operand should be wrapped in parentheses rather than
   separated from this one by a comma.  This is used for the load and
   store instructions which want their operands to look like
       reg,displacement(reg)
   */
#define PPC_OPERAND_PARENS (0x8)

/* This operand may use the symbolic names for the CR fields, which
   are
       lt  0	gt  1	eq  2	so  3	un  3
       cr0 0	cr1 1	cr2 2	cr3 3
       cr4 4	cr5 5	cr6 6	cr7 7
   These may be combined arithmetically, as in cr2*4+gt.  These are
   only supported on the PowerPC, not the POWER.  */
#define PPC_OPERAND_CR (0x10)

/* This operand names a register.  The disassembler uses this to print
   register names with a leading 'r'.  */
#define PPC_OPERAND_GPR (0x20)

/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
#define PPC_OPERAND_GPR_0 (0x40)

/* This operand names a floating point register.  The disassembler
   prints these with a leading 'f'.  */
#define PPC_OPERAND_FPR (0x80)

/* This operand is a relative branch displacement.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_RELATIVE (0x100)

/* This operand is an absolute branch address.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_ABSOLUTE (0x200)

/* This operand is optional, and is zero if omitted.  This is used for
   example, in the optional BF field in the comparison instructions.  The
   assembler must count the number of operands remaining on the line,
   and the number of operands remaining for the opcode, and decide
   whether this operand is present or not.  The disassembler should
   print this operand out only if it is not zero.  */
#define PPC_OPERAND_OPTIONAL (0x400)

/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
   is omitted, then for the next operand use this operand value plus
   1, ignoring the next operand field for the opcode.  This wretched
   hack is needed because the Power rotate instructions can take
   either 4 or 5 operands.  The disassembler should print this operand
   out regardless of the PPC_OPERAND_OPTIONAL field.  */
#define PPC_OPERAND_NEXT (0x800)

/* This operand should be regarded as a negative number for the
   purposes of overflow checking (i.e., the normal most negative
   number is disallowed and one more than the normal most positive
   number is allowed).  This flag will only be set for a signed
   operand.  */
#define PPC_OPERAND_NEGATIVE (0x1000)

/* This operand names a vector unit register.  The disassembler
   prints these with a leading 'v'.  */
#define PPC_OPERAND_VR (0x2000)

/* This operand is for the DS field in a DS form instruction.  */
#define PPC_OPERAND_DS (0x4000)

/* This operand is for the DQ field in a DQ form instruction.  */
#define PPC_OPERAND_DQ (0x8000)

/* Valid range of operand is 0..n rather than 0..n-1.  */
#define PPC_OPERAND_PLUS1 (0x10000)

/* Xilinx APU and FSL related operands */
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)

/* This operand names a vector-scalar unit register.  The disassembler
   prints these with a leading 'vs'.  */
#define PPC_OPERAND_VSR (0x100000)
\f
/* The POWER and PowerPC assemblers use a few macros.  We keep them
   with the operands table for simplicity.  The macro table is an
   array of struct powerpc_macro.  */

struct powerpc_macro
{
  /* The macro name.  */
  const char *name;

  /* The number of operands the macro takes.  */
  unsigned int operands;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The values are the
     same as those for the struct powerpc_opcode flags field.  */
  ppc_cpu_t flags;

  /* A format string to turn the macro into a normal instruction.
     Each %N in the string is replaced with operand number N (zero
     based).  */
  const char *format;
};

extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;

extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);

#endif /* PPC_H */
Commit	Line	Data
252b5132	1	/* ppc.h -- Header file for PowerPC opcode table
b84bf58a	2	Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
69fe9ce5	3	2007, 2008, 2009 Free Software Foundation, Inc.
252b5132 RH	4	Written by Ian Lance Taylor, Cygnus Support
	5
	6	This file is part of GDB, GAS, and the GNU binutils.
	7
	8	GDB, GAS, and the GNU binutils are free software; you can redistribute
	9	them and/or modify them under the terms of the GNU General Public
	10	License as published by the Free Software Foundation; either version
	11	1, or (at your option) any later version.
	12
	13	GDB, GAS, and the GNU binutils are distributed in the hope that they
	14	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	15	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	16	the GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this file; see the file COPYING. If not, write to the Free
e172dbf8	20	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 RH	21
	22	#ifndef PPC_H
	23	#define PPC_H
	24
fa452fa6 PB	25	typedef unsigned long ppc_cpu_t;
fa452fa6 PB	26
252b5132 RH	27	/* The opcode table is an array of struct powerpc_opcode. */
	28
	29	struct powerpc_opcode
	30	{
	31	/* The opcode name. */
	32	const char *name;
	33
	34	/* The opcode itself. Those bits which will be filled in with
	35	operands are zeroes. */
	36	unsigned long opcode;
	37
	38	/* The opcode mask. This is used by the disassembler. This is a
	39	mask containing ones indicating those bits which must match the
	40	opcode field, and zeroes indicating those bits which need not
	41	match (and are presumably filled in by operands). */
	42	unsigned long mask;
	43
	44	/* One bit flags for the opcode. These are used to indicate which
	45	specific processors support the instructions. The defined values
	46	are listed below. */
fa452fa6	47	ppc_cpu_t flags;
252b5132	48
1cb0a767 PB	49	/* One bit flags for the opcode. These are used to indicate which
	50	specific processors no longer support the instructions. The defined
	51	values are listed below. */
	52	ppc_cpu_t deprecated;
	53
252b5132 RH	54	/* An array of operand codes. Each code is an index into the
	55	operand table. They appear in the order which the operands must
	56	appear in assembly code, and are terminated by a zero. */
	57	unsigned char operands[8];
	58	};
	59
	60	/* The table itself is sorted by major opcode number, and is otherwise
	61	in the order in which the disassembler should consider
	62	instructions. */
	63	extern const struct powerpc_opcode powerpc_opcodes[];
	64	extern const int powerpc_num_opcodes;
	65
	66	/* Values defined for the flags field of a struct powerpc_opcode. */
	67
	68	/* Opcode is defined for the PowerPC architecture. */
68d23d21	69	#define PPC_OPCODE_PPC 1
252b5132 RH	70
252b5132 RH	71	/* Opcode is defined for the POWER (RS/6000) architecture. */
68d23d21	72	#define PPC_OPCODE_POWER 2
252b5132 RH	73
252b5132 RH	74	/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68d23d21	75	#define PPC_OPCODE_POWER2 4
252b5132 RH	76
252b5132 RH	77	/* Opcode is only defined on 32 bit architectures. */
68d23d21	78	#define PPC_OPCODE_32 8
252b5132 RH	79
252b5132 RH	80	/* Opcode is only defined on 64 bit architectures. */
68d23d21	81	#define PPC_OPCODE_64 0x10
252b5132 RH	82
	83	/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
	84	is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
	85	but it also supports many additional POWER instructions. */
68d23d21	86	#define PPC_OPCODE_601 0x20
252b5132 RH	87
	88	/* Opcode is supported in both the Power and PowerPC architectures
	89	(ie, compiler's -mcpu=common or assembler's -mcom). */
68d23d21	90	#define PPC_OPCODE_COMMON 0x40
252b5132 RH	91
	92	/* Opcode is supported for any Power or PowerPC platform (this is
	93	for the assembler's -many option, and it eliminates duplicates). */
68d23d21	94	#define PPC_OPCODE_ANY 0x80
252b5132	95
45c18104	96	/* Opcode is supported as part of the 64-bit bridge. */
68d23d21	97	#define PPC_OPCODE_64_BRIDGE 0x100
45c18104	98
966f959b	99	/* Opcode is supported by Altivec Vector Unit */
68d23d21	100	#define PPC_OPCODE_ALTIVEC 0x200
418c1742 MG	101
418c1742 MG	102	/* Opcode is supported by PowerPC 403 processor. */
68d23d21	103	#define PPC_OPCODE_403 0x400
418c1742	104
a09cf9bd	105	/* Opcode is supported by PowerPC BookE processor. */
68d23d21	106	#define PPC_OPCODE_BOOKE 0x800
418c1742	107
a09cf9bd	108	/* Opcode is only supported by 64-bit PowerPC BookE processor. */
68d23d21 AM	109	#define PPC_OPCODE_BOOKE64 0x1000
	110
	111	/* Opcode is supported by PowerPC 440 processor. */
	112	#define PPC_OPCODE_440 0x2000
966f959b	113
fc1e7121	114	/* Opcode is only supported by Power4 architecture. */
68d23d21	115	#define PPC_OPCODE_POWER4 0x4000
fc1e7121	116
066be9f7 PB	117	/* Opcode is only supported by Power7 architecture. */
	118	#define PPC_OPCODE_POWER7 0x8000
	119
0449635d	120	/* Opcode is only supported by POWERPC Classic architecture. */
68d23d21	121	#define PPC_OPCODE_CLASSIC 0x10000
0449635d EZ	122
0449635d EZ	123	/* Opcode is only supported by e500x2 Core. */
68d23d21	124	#define PPC_OPCODE_SPE 0x20000
0449635d EZ	125
0449635d EZ	126	/* Opcode is supported by e500x2 Integer select APU. */
68d23d21	127	#define PPC_OPCODE_ISEL 0x40000
0449635d EZ	128
0449635d EZ	129	/* Opcode is an e500 SPE floating point instruction. */
68d23d21	130	#define PPC_OPCODE_EFS 0x80000
0449635d EZ	131
0449635d EZ	132	/* Opcode is supported by branch locking APU. */
68d23d21	133	#define PPC_OPCODE_BRLOCK 0x100000
0449635d EZ	134
0449635d EZ	135	/* Opcode is supported by performance monitor APU. */
68d23d21	136	#define PPC_OPCODE_PMR 0x200000
0449635d EZ	137
0449635d EZ	138	/* Opcode is supported by cache locking APU. */
68d23d21	139	#define PPC_OPCODE_CACHELCK 0x400000
0449635d EZ	140
0449635d EZ	141	/* Opcode is supported by machine check APU. */
68d23d21	142	#define PPC_OPCODE_RFMCI 0x800000
0449635d	143
f4411256	144	/* Opcode is only supported by Power5 architecture. */
9622b051	145	#define PPC_OPCODE_POWER5 0x1000000
f4411256	146
36ae0db3	147	/* Opcode is supported by PowerPC e300 family. */
9622b051 AM	148	#define PPC_OPCODE_E300 0x2000000
	149
	150	/* Opcode is only supported by Power6 architecture. */
	151	#define PPC_OPCODE_POWER6 0x4000000
	152
ede602d7 AM	153	/* Opcode is only supported by PowerPC Cell family. */
ede602d7 AM	154	#define PPC_OPCODE_CELL 0x8000000
36ae0db3	155
c3d65c1c BE	156	/* Opcode is supported by CPUs with paired singles support. */
	157	#define PPC_OPCODE_PPCPS 0x10000000
	158
19a6653c AM	159	/* Opcode is supported by Power E500MC */
	160	#define PPC_OPCODE_E500MC 0x20000000
	161
081ba1b3 AM	162	/* Opcode is supported by PowerPC 405 processor. */
	163	#define PPC_OPCODE_405 0x40000000
	164
9b4e5766 PB	165	/* Opcode is supported by Vector-Scalar (VSX) Unit */
	166	#define PPC_OPCODE_VSX 0x80000000
	167
252b5132 RH	168	/* A macro to extract the major opcode from an instruction. */
	169	#define PPC_OP(i) (((i) >> 26) & 0x3f)
	170	\f
	171	/* The operands table is an array of struct powerpc_operand. */
	172
	173	struct powerpc_operand
	174	{
b84bf58a AM	175	/* A bitmask of bits in the operand. */
b84bf58a AM	176	unsigned int bitm;
252b5132	177
b84bf58a AM	178	/* How far the operand is left shifted in the instruction.
	179	-1 to indicate that BITM and SHIFT cannot be used to determine
	180	where the operand goes in the insn. */
252b5132 RH	181	int shift;
	182
	183	/* Insertion function. This is used by the assembler. To insert an
	184	operand value into an instruction, check this field.
	185
	186	If it is NULL, execute
b84bf58a	187	i \|= (op & o->bitm) << o->shift;
252b5132	188	(i is the instruction which we are filling in, o is a pointer to
b84bf58a	189	this structure, and op is the operand value).
252b5132 RH	190
	191	If this field is not NULL, then simply call it with the
	192	instruction and the operand value. It will return the new value
	193	of the instruction. If the ERRMSG argument is not NULL, then if
	194	the operand value is illegal, *ERRMSG will be set to a warning
	195	string (the operand will be inserted in any case). If the
	196	operand value is legal, *ERRMSG will be unchanged (most operands
	197	can accept any value). */
8cf3f354	198	unsigned long (*insert)
fa452fa6	199	(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
252b5132 RH	200
	201	/* Extraction function. This is used by the disassembler. To
	202	extract this operand type from an instruction, check this field.
	203
	204	If it is NULL, compute
b84bf58a AM	205	op = (i >> o->shift) & o->bitm;
	206	if ((o->flags & PPC_OPERAND_SIGNED) != 0)
	207	sign_extend (op);
252b5132	208	(i is the instruction, o is a pointer to this structure, and op
b84bf58a	209	is the result).
252b5132 RH	210
	211	If this field is not NULL, then simply call it with the
	212	instruction value. It will return the value of the operand. If
	213	the INVALID argument is not NULL, *INVALID will be set to
	214	non-zero if this operand type can not actually be extracted from
	215	this operand (i.e., the instruction does not match). If the
	216	operand is valid, INVALID will not be changed. /
fa452fa6	217	long (extract) (unsigned long instruction, ppc_cpu_t dialect, int invalid);
252b5132 RH	218
	219	/* One bit syntax flags. */
	220	unsigned long flags;
	221	};
	222
	223	/* Elements in the table are retrieved by indexing with values from
	224	the operands field of the powerpc_opcodes table. */
	225
	226	extern const struct powerpc_operand powerpc_operands[];
b84bf58a	227	extern const unsigned int num_powerpc_operands;
252b5132 RH	228
	229	/* Values defined for the flags field of a struct powerpc_operand. */
	230
	231	/* This operand takes signed values. */
b84bf58a	232	#define PPC_OPERAND_SIGNED (0x1)
252b5132 RH	233
	234	/* This operand takes signed values, but also accepts a full positive
	235	range of values when running in 32 bit mode. That is, if bits is
	236	16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
	237	this flag is ignored. */
b84bf58a	238	#define PPC_OPERAND_SIGNOPT (0x2)
252b5132 RH	239
	240	/* This operand does not actually exist in the assembler input. This
	241	is used to support extended mnemonics such as mr, for which two
	242	operands fields are identical. The assembler should call the
	243	insert function with any op value. The disassembler should call
	244	the extract function, ignore the return value, and check the value
	245	placed in the valid argument. */
b84bf58a	246	#define PPC_OPERAND_FAKE (0x4)
252b5132 RH	247
	248	/* The next operand should be wrapped in parentheses rather than
	249	separated from this one by a comma. This is used for the load and
	250	store instructions which want their operands to look like
	251	reg,displacement(reg)
	252	*/
b84bf58a	253	#define PPC_OPERAND_PARENS (0x8)
252b5132 RH	254
	255	/* This operand may use the symbolic names for the CR fields, which
	256	are
	257	lt 0 gt 1 eq 2 so 3 un 3
	258	cr0 0 cr1 1 cr2 2 cr3 3
	259	cr4 4 cr5 5 cr6 6 cr7 7
	260	These may be combined arithmetically, as in cr2*4+gt. These are
	261	only supported on the PowerPC, not the POWER. */
b84bf58a	262	#define PPC_OPERAND_CR (0x10)
252b5132 RH	263
	264	/* This operand names a register. The disassembler uses this to print
	265	register names with a leading 'r'. */
b84bf58a	266	#define PPC_OPERAND_GPR (0x20)
252b5132	267
fdd12ef3	268	/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
b84bf58a	269	#define PPC_OPERAND_GPR_0 (0x40)
fdd12ef3	270
252b5132 RH	271	/* This operand names a floating point register. The disassembler
252b5132 RH	272	prints these with a leading 'f'. */
b84bf58a	273	#define PPC_OPERAND_FPR (0x80)
252b5132 RH	274
	275	/* This operand is a relative branch displacement. The disassembler
	276	prints these symbolically if possible. */
b84bf58a	277	#define PPC_OPERAND_RELATIVE (0x100)
252b5132 RH	278
	279	/* This operand is an absolute branch address. The disassembler
	280	prints these symbolically if possible. */
b84bf58a	281	#define PPC_OPERAND_ABSOLUTE (0x200)
252b5132 RH	282
252b5132 RH	283	/* This operand is optional, and is zero if omitted. This is used for
2a309db0	284	example, in the optional BF field in the comparison instructions. The
252b5132 RH	285	assembler must count the number of operands remaining on the line,
	286	and the number of operands remaining for the opcode, and decide
	287	whether this operand is present or not. The disassembler should
	288	print this operand out only if it is not zero. */
b84bf58a	289	#define PPC_OPERAND_OPTIONAL (0x400)
252b5132 RH	290
	291	/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
	292	is omitted, then for the next operand use this operand value plus
	293	1, ignoring the next operand field for the opcode. This wretched
	294	hack is needed because the Power rotate instructions can take
	295	either 4 or 5 operands. The disassembler should print this operand
	296	out regardless of the PPC_OPERAND_OPTIONAL field. */
b84bf58a	297	#define PPC_OPERAND_NEXT (0x800)
252b5132 RH	298
	299	/* This operand should be regarded as a negative number for the
	300	purposes of overflow checking (i.e., the normal most negative
	301	number is disallowed and one more than the normal most positive
	302	number is allowed). This flag will only be set for a signed
	303	operand. */
b84bf58a	304	#define PPC_OPERAND_NEGATIVE (0x1000)
966f959b C	305
	306	/* This operand names a vector unit register. The disassembler
	307	prints these with a leading 'v'. */
b84bf58a	308	#define PPC_OPERAND_VR (0x2000)
966f959b	309
a6959011	310	/* This operand is for the DS field in a DS form instruction. */
b84bf58a	311	#define PPC_OPERAND_DS (0x4000)
adadcc0c AM	312
adadcc0c AM	313	/* This operand is for the DQ field in a DQ form instruction. */
b84bf58a AM	314	#define PPC_OPERAND_DQ (0x8000)
b84bf58a AM	315
3896c469	316	/* Valid range of operand is 0..n rather than 0..n-1. */
b84bf58a	317	#define PPC_OPERAND_PLUS1 (0x10000)
081ba1b3 AM	318
	319	/* Xilinx APU and FSL related operands */
	320	#define PPC_OPERAND_FSL (0x20000)
	321	#define PPC_OPERAND_FCR (0x40000)
	322	#define PPC_OPERAND_UDI (0x80000)
9b4e5766 PB	323
	324	/* This operand names a vector-scalar unit register. The disassembler
	325	prints these with a leading 'vs'. */
	326	#define PPC_OPERAND_VSR (0x100000)
252b5132 RH	327	\f
	328	/* The POWER and PowerPC assemblers use a few macros. We keep them
	329	with the operands table for simplicity. The macro table is an
	330	array of struct powerpc_macro. */
	331
	332	struct powerpc_macro
	333	{
	334	/* The macro name. */
	335	const char *name;
	336
	337	/* The number of operands the macro takes. */
	338	unsigned int operands;
	339
	340	/* One bit flags for the opcode. These are used to indicate which
	341	specific processors support the instructions. The values are the
	342	same as those for the struct powerpc_opcode flags field. */
fa452fa6	343	ppc_cpu_t flags;
252b5132 RH	344
	345	/* A format string to turn the macro into a normal instruction.
	346	Each %N in the string is replaced with operand number N (zero
	347	based). */
	348	const char *format;
	349	};
	350
	351	extern const struct powerpc_macro powerpc_macros[];
	352	extern const int powerpc_num_macros;
	353
69fe9ce5 AM	354	extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
69fe9ce5 AM	355
252b5132	356	#endif /* PPC_H */