Commit | Line | Data |
---|---|---|
e23eba97 | 1 | /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. |
2571583a | 2 | Copyright (C) 2011-2017 Free Software Foundation, Inc. |
e23eba97 NC |
3 | Contributed by Andrew Waterman |
4 | ||
5 | This file is part of GDB, GAS, and the GNU binutils. | |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version | |
10 | 3, or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef _RISCV_H_ | |
22 | #define _RISCV_H_ | |
23 | ||
24 | #include "riscv-opc.h" | |
25 | #include <stdlib.h> | |
26 | #include <stdint.h> | |
27 | ||
28 | typedef uint64_t insn_t; | |
29 | ||
30 | static inline unsigned int riscv_insn_length (insn_t insn) | |
31 | { | |
32 | if ((insn & 0x3) != 0x3) /* RVC. */ | |
33 | return 2; | |
34 | if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */ | |
35 | return 4; | |
36 | if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */ | |
37 | return 6; | |
38 | if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */ | |
39 | return 8; | |
40 | /* Longer instructions not supported at the moment. */ | |
41 | return 2; | |
42 | } | |
43 | ||
44 | static const char * const riscv_rm[8] = | |
45 | { | |
46 | "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" | |
47 | }; | |
48 | ||
49 | static const char * const riscv_pred_succ[16] = | |
50 | { | |
51 | 0, "w", "r", "rw", "o", "ow", "or", "orw", | |
52 | "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" | |
53 | }; | |
54 | ||
55 | #define RVC_JUMP_BITS 11 | |
56 | #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) | |
57 | ||
58 | #define RVC_BRANCH_BITS 8 | |
59 | #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) | |
60 | ||
61 | #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) | |
62 | #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) | |
63 | ||
64 | #define EXTRACT_ITYPE_IMM(x) \ | |
65 | (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) | |
66 | #define EXTRACT_STYPE_IMM(x) \ | |
67 | (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) | |
68 | #define EXTRACT_SBTYPE_IMM(x) \ | |
69 | ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) | |
70 | #define EXTRACT_UTYPE_IMM(x) \ | |
71 | ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) | |
72 | #define EXTRACT_UJTYPE_IMM(x) \ | |
73 | ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) | |
74 | #define EXTRACT_RVC_IMM(x) \ | |
75 | (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) | |
76 | #define EXTRACT_RVC_LUI_IMM(x) \ | |
77 | (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) | |
78 | #define EXTRACT_RVC_SIMM3(x) \ | |
79 | (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) | |
80 | #define EXTRACT_RVC_ADDI4SPN_IMM(x) \ | |
81 | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) | |
82 | #define EXTRACT_RVC_ADDI16SP_IMM(x) \ | |
83 | ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) | |
84 | #define EXTRACT_RVC_LW_IMM(x) \ | |
85 | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) | |
86 | #define EXTRACT_RVC_LD_IMM(x) \ | |
87 | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) | |
88 | #define EXTRACT_RVC_LWSP_IMM(x) \ | |
89 | ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) | |
90 | #define EXTRACT_RVC_LDSP_IMM(x) \ | |
91 | ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) | |
92 | #define EXTRACT_RVC_SWSP_IMM(x) \ | |
93 | ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) | |
94 | #define EXTRACT_RVC_SDSP_IMM(x) \ | |
95 | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) | |
96 | #define EXTRACT_RVC_B_IMM(x) \ | |
97 | ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) | |
98 | #define EXTRACT_RVC_J_IMM(x) \ | |
99 | ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) | |
100 | ||
101 | #define ENCODE_ITYPE_IMM(x) \ | |
102 | (RV_X(x, 0, 12) << 20) | |
103 | #define ENCODE_STYPE_IMM(x) \ | |
104 | ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) | |
105 | #define ENCODE_SBTYPE_IMM(x) \ | |
106 | ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) | |
107 | #define ENCODE_UTYPE_IMM(x) \ | |
108 | (RV_X(x, 12, 20) << 12) | |
109 | #define ENCODE_UJTYPE_IMM(x) \ | |
110 | ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) | |
111 | #define ENCODE_RVC_IMM(x) \ | |
112 | ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) | |
113 | #define ENCODE_RVC_LUI_IMM(x) \ | |
114 | ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) | |
115 | #define ENCODE_RVC_SIMM3(x) \ | |
116 | (RV_X(x, 0, 3) << 10) | |
117 | #define ENCODE_RVC_ADDI4SPN_IMM(x) \ | |
118 | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) | |
119 | #define ENCODE_RVC_ADDI16SP_IMM(x) \ | |
120 | ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) | |
121 | #define ENCODE_RVC_LW_IMM(x) \ | |
122 | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) | |
123 | #define ENCODE_RVC_LD_IMM(x) \ | |
124 | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) | |
125 | #define ENCODE_RVC_LWSP_IMM(x) \ | |
126 | ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) | |
127 | #define ENCODE_RVC_LDSP_IMM(x) \ | |
128 | ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) | |
129 | #define ENCODE_RVC_SWSP_IMM(x) \ | |
130 | ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) | |
131 | #define ENCODE_RVC_SDSP_IMM(x) \ | |
132 | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) | |
133 | #define ENCODE_RVC_B_IMM(x) \ | |
134 | ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) | |
135 | #define ENCODE_RVC_J_IMM(x) \ | |
136 | ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) | |
137 | ||
138 | #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) | |
139 | #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) | |
140 | #define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) | |
141 | #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) | |
142 | #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) | |
143 | #define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) | |
144 | #define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) | |
145 | #define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) | |
146 | #define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) | |
147 | #define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) | |
148 | #define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x)) | |
149 | #define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x)) | |
150 | #define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x)) | |
151 | #define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x)) | |
152 | #define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x)) | |
153 | #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x)) | |
154 | #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x)) | |
155 | #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x)) | |
156 | ||
157 | #define RISCV_RTYPE(insn, rd, rs1, rs2) \ | |
158 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) | |
159 | #define RISCV_ITYPE(insn, rd, rs1, imm) \ | |
160 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) | |
161 | #define RISCV_STYPE(insn, rs1, rs2, imm) \ | |
162 | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) | |
163 | #define RISCV_SBTYPE(insn, rs1, rs2, target) \ | |
164 | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) | |
165 | #define RISCV_UTYPE(insn, rd, bigimm) \ | |
166 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) | |
167 | #define RISCV_UJTYPE(insn, rd, target) \ | |
168 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) | |
169 | ||
170 | #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) | |
171 | #define RVC_NOP MATCH_C_ADDI | |
172 | ||
173 | #define RISCV_CONST_HIGH_PART(VALUE) \ | |
174 | (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) | |
175 | #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) | |
176 | #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) | |
177 | #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) | |
178 | ||
179 | #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS | |
180 | #define RISCV_JUMP_ALIGN_BITS 1 | |
181 | #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) | |
182 | #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) | |
183 | ||
184 | #define RISCV_IMM_BITS 12 | |
185 | #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) | |
186 | #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) | |
187 | #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) | |
188 | #define RISCV_RVC_IMM_REACH (1LL << 6) | |
189 | #define RISCV_BRANCH_BITS RISCV_IMM_BITS | |
190 | #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS | |
191 | #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) | |
192 | #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) | |
193 | ||
194 | /* RV fields. */ | |
195 | ||
196 | #define OP_MASK_OP 0x7f | |
197 | #define OP_SH_OP 0 | |
198 | #define OP_MASK_RS2 0x1f | |
199 | #define OP_SH_RS2 20 | |
200 | #define OP_MASK_RS1 0x1f | |
201 | #define OP_SH_RS1 15 | |
202 | #define OP_MASK_RS3 0x1f | |
203 | #define OP_SH_RS3 27 | |
204 | #define OP_MASK_RD 0x1f | |
205 | #define OP_SH_RD 7 | |
206 | #define OP_MASK_SHAMT 0x3f | |
207 | #define OP_SH_SHAMT 20 | |
208 | #define OP_MASK_SHAMTW 0x1f | |
209 | #define OP_SH_SHAMTW 20 | |
210 | #define OP_MASK_RM 0x7 | |
211 | #define OP_SH_RM 12 | |
212 | #define OP_MASK_PRED 0xf | |
213 | #define OP_SH_PRED 24 | |
214 | #define OP_MASK_SUCC 0xf | |
215 | #define OP_SH_SUCC 20 | |
216 | #define OP_MASK_AQ 0x1 | |
217 | #define OP_SH_AQ 26 | |
218 | #define OP_MASK_RL 0x1 | |
219 | #define OP_SH_RL 25 | |
220 | ||
221 | #define OP_MASK_CUSTOM_IMM 0x7f | |
222 | #define OP_SH_CUSTOM_IMM 25 | |
223 | #define OP_MASK_CSR 0xfff | |
224 | #define OP_SH_CSR 20 | |
225 | ||
226 | /* RVC fields. */ | |
227 | ||
228 | #define OP_MASK_CRS2 0x1f | |
229 | #define OP_SH_CRS2 2 | |
230 | #define OP_MASK_CRS1S 0x7 | |
231 | #define OP_SH_CRS1S 7 | |
232 | #define OP_MASK_CRS2S 0x7 | |
233 | #define OP_SH_CRS2S 2 | |
234 | ||
235 | /* ABI names for selected x-registers. */ | |
236 | ||
237 | #define X_RA 1 | |
238 | #define X_SP 2 | |
239 | #define X_GP 3 | |
240 | #define X_TP 4 | |
241 | #define X_T0 5 | |
242 | #define X_T1 6 | |
243 | #define X_T2 7 | |
244 | #define X_T3 28 | |
245 | ||
246 | #define NGPR 32 | |
247 | #define NFPR 32 | |
248 | ||
249 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in | |
250 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
251 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
252 | (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ | |
253 | | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) | |
254 | ||
255 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
256 | SHIFT places. */ | |
257 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
258 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
259 | ||
260 | /* Extract the operand given by FIELD from integer INSN. */ | |
261 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
262 | EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) | |
263 | ||
264 | /* This structure holds information for a particular instruction. */ | |
265 | ||
266 | struct riscv_opcode | |
267 | { | |
268 | /* The name of the instruction. */ | |
269 | const char *name; | |
270 | /* The ISA subset name (I, M, A, F, D, Xextension). */ | |
271 | const char *subset; | |
272 | /* A string describing the arguments for this instruction. */ | |
273 | const char *args; | |
274 | /* The basic opcode for the instruction. When assembling, this | |
275 | opcode is modified by the arguments to produce the actual opcode | |
276 | that is used. If pinfo is INSN_MACRO, then this is 0. */ | |
277 | insn_t match; | |
278 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
279 | relevant portions of the opcode when disassembling. If the | |
280 | actual opcode anded with the match field equals the opcode field, | |
281 | then we have found the correct instruction. If pinfo is | |
282 | INSN_MACRO, then this field is the macro identifier. */ | |
283 | insn_t mask; | |
284 | /* A function to determine if a word corresponds to this instruction. | |
285 | Usually, this computes ((word & mask) == match). */ | |
286 | int (*match_func) (const struct riscv_opcode *op, insn_t word); | |
287 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
288 | of bits describing the instruction, notably any relevant hazard | |
289 | information. */ | |
290 | unsigned long pinfo; | |
291 | }; | |
292 | ||
293 | /* Instruction is a simple alias (e.g. "mv" for "addi"). */ | |
294 | #define INSN_ALIAS 0x00000001 | |
295 | /* Instruction is actually a macro. It should be ignored by the | |
296 | disassembler, and requires special treatment by the assembler. */ | |
297 | #define INSN_MACRO 0xffffffff | |
298 | ||
299 | /* This is a list of macro expanded instructions. | |
300 | ||
301 | _I appended means immediate | |
302 | _A appended means address | |
303 | _AB appended means address with base register | |
304 | _D appended means 64 bit floating point constant | |
305 | _S appended means 32 bit floating point constant. */ | |
306 | ||
307 | enum | |
308 | { | |
309 | M_LA, | |
310 | M_LLA, | |
311 | M_LA_TLS_GD, | |
312 | M_LA_TLS_IE, | |
313 | M_LB, | |
314 | M_LBU, | |
315 | M_LH, | |
316 | M_LHU, | |
317 | M_LW, | |
318 | M_LWU, | |
319 | M_LD, | |
320 | M_SB, | |
321 | M_SH, | |
322 | M_SW, | |
323 | M_SD, | |
324 | M_FLW, | |
325 | M_FLD, | |
326 | M_FSW, | |
327 | M_FSD, | |
328 | M_CALL, | |
329 | M_J, | |
330 | M_LI, | |
331 | M_NUM_MACROS | |
332 | }; | |
333 | ||
334 | ||
335 | extern const char * const riscv_gpr_names_numeric[NGPR]; | |
336 | extern const char * const riscv_gpr_names_abi[NGPR]; | |
337 | extern const char * const riscv_fpr_names_numeric[NFPR]; | |
338 | extern const char * const riscv_fpr_names_abi[NFPR]; | |
339 | ||
340 | extern const struct riscv_opcode riscv_opcodes[]; | |
341 | ||
342 | #endif /* _RISCV_H_ */ |