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252b5132 | 1 | /* Definitions for opcode table for the sparc. |
8cf3f354 AM |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, |
3 | 2003 Free Software Foundation, Inc. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and | |
6 | the GNU Binutils. | |
7 | ||
8 | GAS/GDB is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS/GDB is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS or GDB; see the file COPYING. If not, write to | |
e172dbf8 NC |
20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 22 | |
b3f7d5fd | 23 | #include "ansidecl.h" |
252b5132 RH |
24 | |
25 | /* The SPARC opcode table (and other related data) is defined in | |
26 | the opcodes library in sparc-opc.c. If you change anything here, make | |
27 | sure you fix up that file, and vice versa. */ | |
28 | ||
29 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the | |
30 | instruction's name rather than the args. This would make gas faster, pinsn | |
31 | slower, but would mess up some macros a bit. xoxorich. */ | |
32 | ||
33 | /* List of instruction sets variations. | |
34 | These values are such that each element is either a superset of a | |
35 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P | |
36 | returns non-zero. | |
37 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. | |
38 | Don't change this without updating sparc-opc.c. */ | |
39 | ||
40 | enum sparc_opcode_arch_val { | |
41 | SPARC_OPCODE_ARCH_V6 = 0, | |
42 | SPARC_OPCODE_ARCH_V7, | |
43 | SPARC_OPCODE_ARCH_V8, | |
44 | SPARC_OPCODE_ARCH_SPARCLET, | |
45 | SPARC_OPCODE_ARCH_SPARCLITE, | |
46 | /* v9 variants must appear last */ | |
47 | SPARC_OPCODE_ARCH_V9, | |
48 | SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ | |
19f7b010 | 49 | SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ |
252b5132 RH |
50 | SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ |
51 | }; | |
52 | ||
53 | /* The highest architecture in the table. */ | |
54 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) | |
55 | ||
56 | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in | |
57 | insn encoding/decoding. */ | |
58 | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) | |
59 | ||
60 | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ | |
61 | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) | |
62 | ||
63 | /* Table of cpu variants. */ | |
64 | ||
65 | struct sparc_opcode_arch { | |
66 | const char *name; | |
67 | /* Mask of sparc_opcode_arch_val's supported. | |
68 | EG: For v7 this would be | |
69 | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). | |
70 | These are short's because sparc_opcode.architecture is. */ | |
71 | short supported; | |
72 | }; | |
73 | ||
74 | extern const struct sparc_opcode_arch sparc_opcode_archs[]; | |
75 | ||
76 | /* Given architecture name, look up it's sparc_opcode_arch_val value. */ | |
8cf3f354 | 77 | extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); |
252b5132 RH |
78 | |
79 | /* Return the bitmask of supported architectures for ARCH. */ | |
80 | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) | |
81 | ||
82 | /* Non-zero if ARCH1 conflicts with ARCH2. | |
83 | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ | |
84 | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ | |
85 | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ | |
86 | != SPARC_OPCODE_SUPPORTED (ARCH1)) \ | |
87 | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ | |
88 | != SPARC_OPCODE_SUPPORTED (ARCH2))) | |
89 | ||
90 | /* Structure of an opcode table entry. */ | |
91 | ||
92 | struct sparc_opcode { | |
93 | const char *name; | |
94 | unsigned long match; /* Bits that must be set. */ | |
95 | unsigned long lose; /* Bits that must not be set. */ | |
96 | const char *args; | |
97 | /* This was called "delayed" in versions before the flags. */ | |
98 | char flags; | |
99 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ | |
100 | }; | |
101 | ||
102 | #define F_DELAYED 1 /* Delayed branch */ | |
103 | #define F_ALIAS 2 /* Alias for a "real" instruction */ | |
104 | #define F_UNBR 4 /* Unconditional branch */ | |
105 | #define F_CONDBR 8 /* Conditional branch */ | |
106 | #define F_JSR 16 /* Subroutine call */ | |
107 | #define F_FLOAT 32 /* Floating point instruction (not a branch) */ | |
108 | #define F_FBR 64 /* Floating point branch */ | |
109 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ | |
110 | ||
111 | /* | |
112 | ||
113 | All sparc opcodes are 32 bits, except for the `set' instruction (really a | |
114 | macro), which is 64 bits. It is handled as a special case. | |
115 | ||
116 | The match component is a mask saying which bits must match a particular | |
117 | opcode in order for an instruction to be an instance of that opcode. | |
118 | ||
119 | The args component is a string containing one character for each operand of the | |
120 | instruction. | |
121 | ||
122 | Kinds of operands: | |
123 | # Number used by optimizer. It is ignored. | |
124 | 1 rs1 register. | |
125 | 2 rs2 register. | |
126 | d rd register. | |
127 | e frs1 floating point register. | |
128 | v frs1 floating point register (double/even). | |
129 | V frs1 floating point register (quad/multiple of 4). | |
130 | f frs2 floating point register. | |
131 | B frs2 floating point register (double/even). | |
132 | R frs2 floating point register (quad/multiple of 4). | |
133 | g frsd floating point register. | |
134 | H frsd floating point register (double/even). | |
135 | J frsd floating point register (quad/multiple of 4). | |
136 | b crs1 coprocessor register | |
137 | c crs2 coprocessor register | |
138 | D crsd coprocessor register | |
139 | m alternate space register (asr) in rd | |
140 | M alternate space register (asr) in rs1 | |
141 | h 22 high bits. | |
142 | X 5 bit unsigned immediate | |
143 | Y 6 bit unsigned immediate | |
19f7b010 | 144 | 3 SIAM mode (3 bits). (v9b) |
252b5132 RH |
145 | K MEMBAR mask (7 bits). (v9) |
146 | j 10 bit Immediate. (v9) | |
147 | I 11 bit Immediate. (v9) | |
148 | i 13 bit Immediate. | |
149 | n 22 bit immediate. | |
150 | k 2+14 bit PC relative immediate. (v9) | |
151 | G 19 bit PC relative immediate. (v9) | |
152 | l 22 bit PC relative immediate. | |
153 | L 30 bit PC relative immediate. | |
154 | a Annul. The annul bit is set. | |
155 | A Alternate address space. Stored as 8 bits. | |
156 | C Coprocessor state register. | |
157 | F floating point state register. | |
158 | p Processor state register. | |
159 | N Branch predict clear ",pn" (v9) | |
160 | T Branch predict set ",pt" (v9) | |
161 | z %icc. (v9) | |
162 | Z %xcc. (v9) | |
163 | q Floating point queue. | |
164 | r Single register that is both rs1 and rd. | |
165 | O Single register that is both rs2 and rd. | |
166 | Q Coprocessor queue. | |
167 | S Special case. | |
168 | t Trap base register. | |
169 | w Window invalid mask register. | |
170 | y Y register. | |
171 | u sparclet coprocessor registers in rd position | |
172 | U sparclet coprocessor registers in rs1 position | |
173 | E %ccr. (v9) | |
174 | s %fprs. (v9) | |
175 | P %pc. (v9) | |
176 | W %tick. (v9) | |
177 | o %asi. (v9) | |
178 | 6 %fcc0. (v9) | |
179 | 7 %fcc1. (v9) | |
180 | 8 %fcc2. (v9) | |
181 | 9 %fcc3. (v9) | |
182 | ! Privileged Register in rd (v9) | |
183 | ? Privileged Register in rs1 (v9) | |
184 | * Prefetch function constant. (v9) | |
185 | x OPF field (v9 impdep). | |
186 | 0 32/64 bit immediate for set or setx (v9) insns | |
187 | _ Ancillary state register in rd (v9a) | |
188 | / Ancillary state register in rs1 (v9a) | |
189 | ||
190 | The following chars are unused: (note: ,[] are used as punctuation) | |
19f7b010 | 191 | [45] |
252b5132 RH |
192 | |
193 | */ | |
194 | ||
195 | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ | |
196 | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ | |
197 | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ | |
198 | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ | |
199 | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ | |
200 | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ | |
201 | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ | |
202 | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ | |
203 | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ | |
204 | #define F1(x) (OP(x)) | |
205 | #define DISP30(x) ((x)&0x3fffffff) | |
206 | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ | |
207 | #define RS2(x) ((x)&0x1f) /* rs2 field */ | |
208 | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ | |
209 | #define RD(x) (((x)&0x1f) << 25) /* destination register field */ | |
210 | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ | |
211 | #define ASI_RS2(x) (SIMM13(x)) | |
212 | #define MEMBAR(x) ((x)&0x7f) | |
213 | #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ | |
214 | ||
215 | #define ANNUL (1<<29) | |
216 | #define BPRED (1<<19) /* v9 */ | |
217 | #define IMMED F3I(1) | |
218 | #define RD_G0 RD(~0) | |
219 | #define RS1_G0 RS1(~0) | |
220 | #define RS2_G0 RS2(~0) | |
221 | ||
222 | extern const struct sparc_opcode sparc_opcodes[]; | |
223 | extern const int sparc_num_opcodes; | |
224 | ||
8cf3f354 AM |
225 | extern int sparc_encode_asi (const char *); |
226 | extern const char *sparc_decode_asi (int); | |
227 | extern int sparc_encode_membar (const char *); | |
228 | extern const char *sparc_decode_membar (int); | |
229 | extern int sparc_encode_prefetch (const char *); | |
230 | extern const char *sparc_decode_prefetch (int); | |
231 | extern int sparc_encode_sparclet_cpreg (const char *); | |
232 | extern const char *sparc_decode_sparclet_cpreg (int); | |
252b5132 RH |
233 | |
234 | /* | |
235 | * Local Variables: | |
236 | * fill-column: 131 | |
237 | * comment-column: 0 | |
238 | * End: | |
239 | */ | |
240 | ||
241 | /* end of sparc.h */ |