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TIC4X testcase commit
[deliverable/binutils-gdb.git] / include / opcode / tic4x.h
CommitLineData
026df7c5
NC		 1/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
2
3 Copyright (c) 2002 Free Software Foundation.
4
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
44287f60
SS		 19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20*/
026df7c5 21
44287f60 22#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
026df7c5
NC		 23#define IS_CPU_C4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
24
25/* Define some bitfield extraction/insertion macros. */
26#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
27#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l))
28#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l))
29#define INSERTU(inst, val, m, l) (inst |= ((val) << (l)))
30#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
31
32/* Define register numbers. */
33typedef enum
34 {
35 REG_R0, REG_R1, REG_R2, REG_R3,
36 REG_R4, REG_R5, REG_R6, REG_R7,
37 REG_AR0, REG_AR1, REG_AR2, REG_AR3,
38 REG_AR4, REG_AR5, REG_AR6, REG_AR7,
39 REG_DP, REG_IR0, REG_IR1, REG_BK,
40 REG_SP, REG_ST, REG_DIE, REG_IIE,
41 REG_IIF, REG_RS, REG_RE, REG_RC,
42 REG_R8, REG_R9, REG_R10, REG_R11,
43 REG_IVTP, REG_TVTP
44 }
45c4x_reg_t;
46
47/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */
48
49#define REG_IE REG_DIE /* C3x only */
50#define REG_IF REG_IIE /* C3x only */
51#define REG_IOF REG_IIF /* C3x only */
52
53#define C3X_REG_MAX REG_RC
54#define C4X_REG_MAX REG_TVTP
55
56/* Register table size including C4x expansion regs. */
57#define REG_TABLE_SIZE (C4X_REG_MAX + 1)
58
59struct c4x_register
60{
61 char * name;
62 unsigned long regno;
63};
64
65typedef struct c4x_register c4x_register_t;
66
67/* We could store register synonyms here. */
68static const c4x_register_t c3x_registers[] =
69{
70 {"f0", REG_R0},
71 {"r0", REG_R0},
72 {"f1", REG_R1},
73 {"r1", REG_R1},
74 {"f2", REG_R2},
75 {"r2", REG_R2},
76 {"f3", REG_R3},
77 {"r3", REG_R3},
78 {"f4", REG_R4},
79 {"r4", REG_R4},
80 {"f5", REG_R5},
81 {"r5", REG_R5},
82 {"f6", REG_R6},
83 {"r6", REG_R6},
84 {"f7", REG_R7},
85 {"r7", REG_R7},
86 {"ar0", REG_AR0},
87 {"ar1", REG_AR1},
88 {"ar2", REG_AR2},
89 {"ar3", REG_AR3},
90 {"ar4", REG_AR4},
91 {"ar5", REG_AR5},
92 {"ar6", REG_AR6},
93 {"ar7", REG_AR7},
94 {"dp", REG_DP},
95 {"ir0", REG_IR0},
96 {"ir1", REG_IR1},
97 {"bk", REG_BK},
98 {"sp", REG_SP},
99 {"st", REG_ST},
100 {"ie", REG_IE},
101 {"if", REG_IF},
102 {"iof", REG_IOF},
103 {"rs", REG_RS},
104 {"re", REG_RE},
105 {"rc", REG_RC},
106 {"", 0}
107};
108
109const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1);
110
111/* Define C4x registers in addition to C3x registers. */
112static const c4x_register_t c4x_registers[] =
113{
114 {"die", REG_DIE}, /* Clobbers C3x REG_IE */
115 {"iie", REG_IIE}, /* Clobbers C3x REG_IF */
116 {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */
117 {"f8", REG_R8},
118 {"r8", REG_R8},
119 {"f9", REG_R9},
120 {"r9", REG_R9},
121 {"f10", REG_R10},
122 {"r10", REG_R10},
123 {"f11", REG_R11},
124 {"r11", REG_R11},
125 {"ivtp", REG_IVTP},
126 {"tvtp", REG_TVTP},
127 {"", 0}
128};
129
130const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
131
132/* Instruction template. */
133struct c4x_inst
134{
135 char * name;
136 unsigned long opcode;
137 unsigned long opmask;
138 char * args;
44287f60 139 unsigned long oplevel;
026df7c5
NC		 140};
141
142typedef struct c4x_inst c4x_inst_t;
143
44287f60
SS		 144/* Opcode infix
145 B condition 16--20 U,C,Z,LO,HI, etc.
146 C condition 23--27 U,C,Z,LO,HI, etc.
147
148 Arguments
026df7c5
NC		 149 , required arg follows
150 ; optional arg follows
44287f60
SS		 151
152 Argument types bits [classes] - example
153 -----------------------------------------------------------
154 * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
155 # direct (for LDP) 0--15 [Z] - @start, start
156 @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
157 A address register 22--24 [D] - AR0, AR7
158 B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x)
159 C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
160 E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
161 e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
162 F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1
163 G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
164 g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
165 H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
166 I indirect (no disp) 0--7 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
167 J indirect (no disp) 8--15 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
168 K register 19--21 [LL,M,Q,QC] - R0, R7
169 L register 22--24 [LL,LS,P,Q,QC] - R0, R7
170 M register (R2,R3) 22--22 [M] R2, R3
171 N register (R0,R1) 23--23 [M] R0, R1
172 O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5)
173 P displacement (PC Rel) 0--15 [D,J,JS] - @start, start
174 Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
175 q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11
176 R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
177 r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
178 S short int immediate 0--15 [A,AB,AY,BI] - -5, 5
179 T integer (C4x) 16--20 [Z] - -5, 12
180 U unsigned integer 0--15 [AU,A3] - 0, 65535
181 V vector (C4x: 0--8) 0--4 [Z] - 25, 7
182 W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5
183 X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP
184 Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0
185 Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
186*/
026df7c5
NC		 187
188#define C4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
189#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */
190
44287f60
SS		 191/* Define the instruction level */
192#define OP_C3X 0x0 /* C30 support - supported by all */
193#define OP_C4X 0x1 /* C40 support - C40, C44 */
194#define OP_C3XE 0x2 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
195 I and J is enhanced in these classes - C31>=6.0,
196 C32>=2.0, C33 */
197#define OP_LPWR 0x3 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
198 LC31, C31>=5.0, C32 */
199#define OP_IDLE 0x4 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
200 C32, C33, C40>=5.0, C44 */
201
202/* The following class definition is a classification scheme for
203 putting instructions with similar type of arguments together. It
204 simplifies the op-code definitions significantly, as we then only
205 need to use the class macroes for 95% of the DSP's opcodes.
206*/
207
208/* A: General 2-operand integer operations
209 Syntax: <i> src, dst
210 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
211 dst = Register (R)
212 Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
213 SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
214 MBn, MHn, MPYSHI, MPYUHI
215*/
216#define A_CLASS_INSN(name, opcode, level) \
217 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
218 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
219 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
220 { name, opcode|0x00600000, 0xffe00000, "S,R", level }
221
222/* AB: General 2-operand integer operation with condition
223 Syntax: <i>c src, dst
224 c = Condition
225 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
226 dst = Register (R)
227 Instr: 1/0 - LDIc
228*/
229#define AB_CLASS_INSN(name, opcode, level) \
230 { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
231 { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
232 { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
233 { name, opcode|0x40600000, 0xf0600000, "S,R", level }
234
235/* AU: General 2-operand unsigned integer operation
236 Syntax: <i> src, dst
237 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
238 dst = Register (R)
239 Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
240*/
241#define AU_CLASS_INSN(name, opcode, level) \
242 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
243 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
244 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
245 { name, opcode|0x00600000, 0xffe00000, "U,R", level }
246
247/* AF: General 2-operand float to integer operation
248 Syntax: <i> src, dst
249 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
250 dst = Register (R)
251 Instr: 1/0 - FIX
252*/
253#define AF_CLASS_INSN(name, opcode, level) \
254 { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
255 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
256 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
257 { name, opcode|0x00600000, 0xffe00000, "F,R", level }
258
259/* A2: Limited 1-operand (integer) operation
260 Syntax: <i> src
261 src = Register (Q), Indirect (*), None
262 Instr: 1/0 - NOP
263*/
264#define A2_CLASS_INSN(name, opcode, level) \
265 { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
266 { name, opcode|0x00400000, 0xffe00000, "*", level }, \
267 { name, opcode|0x00000000, 0xffe00000, "" , level }
268
269/* A3: General 1-operand unsigned integer operation
270 Syntax: <i> src
271 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
272 Instr: 1/0 - RPTS
273*/
274#define A3_CLASS_INSN(name, opcode, level) \
275 { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
276 { name, opcode|0x00200000, 0xffff0000, "@", level }, \
277 { name, opcode|0x00400000, 0xffff0000, "*", level }, \
278 { name, opcode|0x00600000, 0xffff0000, "U", level }
279
280/* A6: Limited 2-operand integer operation
281 Syntax: <i> src, dst
282 src = Direct (@), Indirect (*)
283 dst = Register (R)
284 Instr: 1/1 - LDII, C4x: SIGI
285*/
286#define A6_CLASS_INSN(name, opcode, level) \
287 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
288 { name, opcode|0x00400000, 0xffe00000, "*,R", level }
289
290/* A7: Limited 2-operand integer store operation
291 Syntax: <i> src, dst
292 src = Register (R)
293 dst = Direct (@), Indirect (*)
294 Instr: 2/0 - STI, STII
295*/
296#define A7_CLASS_INSN(name, opcode, level) \
297 { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
298 { name, opcode|0x00400000, 0xffe00000, "R,*", level }
299
300/* AY: General 2-operand signed address load operation
301 Syntax: <i> src, dst
302 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
303 dst = Address register - ARx, IRx, DP, BK, SP (Y)
304 Instr: 0/1 - C4x: LDA
305 Note: Q and Y should *never* be the same register
306*/
307#define AY_CLASS_INSN(name, opcode, level) \
308 { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
309 { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
310 { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
311 { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
312
313/* B: General 2-operand float operation
314 Syntax: <i> src, dst
315 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
316 dst = Register 0-11 (r)
317 Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
318 SUBF, SUBRF, C4x: RSQRF, TOIEEE
319*/
320#define B_CLASS_INSN(name, opcode, level) \
321 { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
322 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
323 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
324 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
325
326/* BA: General 2-operand integer to float operation
327 Syntax: <i> src, dst
328 src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
329 dst = Register 0-11 (r)
330 Instr: 0/1 - C4x: CRCPF
331*/
332#define BA_CLASS_INSN(name, opcode, level) \
333 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
334 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
335 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
336 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
337
338/* BB: General 2-operand conditional float operation
339 Syntax: <i>c src, dst
340 c = Condition
341 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
342 dst = Register 0-11 (r)
343 Instr: 1/0 - LDFc
344*/
345#define BB_CLASS_INSN(name, opcode, level) \
346 { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
347 { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
348 { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
349 { name, opcode|0x40600000, 0xf0600000, "F,r", level }
350
351/* BI: General 2-operand integer to float operation (yet different to BA)
352 Syntax: <i> src, dst
353 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
354 dst = Register 0-11 (r)
355 Instr: 1/0 - FLOAT
356*/
357#define BI_CLASS_INSN(name, opcode, level) \
358 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
359 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
360 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
361 { name, opcode|0x00600000, 0xffe00000, "S,r", level }
362
363/* B6: Limited 2-operand float operation
364 Syntax: <i> src, dst
365 src = Direct (@), Indirect (*)
366 dst = Register 0-11 (r)
367 Instr: 1/1 - LDFI, C4x: FRIEEE
368*/
369#define B6_CLASS_INSN(name, opcode, level) \
370 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
371 { name, opcode|0x00400000, 0xffe00000, "*,r", level }
372
373/* B7: Limited 2-operand float store operation
374 Syntax: <i> src, dst
375 src = Register 0-11 (r)
376 dst = Direct (@), Indirect (*)
377 Instr: 2/0 - STF, STFI
378*/
379#define B7_CLASS_INSN(name, opcode, level) \
380 { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
381 { name, opcode|0x00400000, 0xffe00000, "r,*", level }
382
383/* D: Decrement and brach operations
384 Syntax: <i>c ARn, dst
385 c = condition
386 ARn = AR register 0-7 (A)
387 dst = Register (Q), PC-relative (P)
388 Instr: 2/0 - DBc, DBcD
389 Alias: <name1> <name2>
390*/
391#define D_CLASS_INSN(name1, name2, opcode, level) \
392 { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
393 { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
394 { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
395 { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
396
397/* I: General branch operations
398 Syntax: <i> dst
399 dst = Address (B)
400 Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
401*/
402
403/* I2: General branch operations (C4x addition)
404 Syntax: <i> dst
405 dst = Address (B), C4x: Register (Q)
406 Instr: 2/0 - RPTB, RPTBD
407*/
408
409/* J: General conditional branch operations
410 Syntax: <i>c dst
411 c = Condition
412 dst = Register (Q), PC-relative (P)
413 Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
414 Alias: <name1> <name2>
415*/
416#define J_CLASS_INSN(name1, name2, opcode, level) \
417 { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
418 { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
419 { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
420 { name2, opcode|0x02000000, 0xffe00000, "P", level }
421
422/* JS: General conditional branch operations
423 Syntax: <i>c dst
424 c = Condition
425 dst = Register (Q), PC-relative (P)
426 Instr: 1/1 - CALLc, C4X: LAJc
427*/
428
429/* LL: Load-load parallell operation
430 Syntax: <i> src2, dst2 || <i> src1, dst1
431 src1 = Indirect 0,1,IR0,IR1 (J)
432 dst1 = Register 0-7 (K)
433 src2 = Indirect 0,1,IR0,IR1 (I)
434 dst2 = Register 0-7 (L)
435 Instr: 2/0 - LDF||LDF, LDI||LDI
436 Alias: i||i, i1||i2, i2||i1
437*/
438#define LL_CLASS_INSN(name, opcode, level) \
439 { name "_" name , opcode, 0xfe000000, "I,L|J,K", level }, \
440 { name "2_" name "1", opcode, 0xfe000000, "I,L|J,K", level }, \
441 { name "1_" name "2", opcode, 0xfe000000, "J,K|I,L", level }
442
443/* LS: Store-store parallell operation
444 Syntax: <i> src2, dst2 || <i> src1, dst1
445 src1 = Register 0-7 (H)
446 dst1 = Indirect 0,1,IR0,IR1 (J)
447 src2 = Register 0-7 (L)
448 dst2 = Indirect 0,1,IR0,IR1 (I)
449 Instr: 2/0 - STF||STF, STI||STI
450 Alias: i||i, i1||i2, i2||i1.
451*/
452#define LS_CLASS_INSN(name, opcode, level) \
453 { name "_" name , opcode, 0xfe000000, "L,I|H,J", level }, \
454 { name "2_" name "1", opcode, 0xfe000000, "L,I|H,J", level }, \
455 { name "1_" name "2", opcode, 0xfe000000, "H,J|L,I", level }
456
457/* M: General multiply and add/sub operations
458 Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
459 <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
460 <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
461 <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
462 <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
463 <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
464 src1 = Register 0-7 (K)
465 src2 = Register 0-7 (H)
466 src3 = Indirect 0,1,IR0,IR1 (J)
467 src4 = Indirect 0,1,IR0,IR1 (I)
468 dst1 = Register 0-1 (N)
469 dst2 = Register 2-3 (M)
470 Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
471 Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
472*/
473#define M_CLASS_INSN(namea, nameb, opcode, level) \
474 { namea "_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
475 { namea "_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
476 { namea "_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
477 { namea "_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
478 { namea "_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
479 { namea "_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
480 { namea "3_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
481 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
482 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
483 { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
484 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
485 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
486 { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
487 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
488 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
489 { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
490 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
491 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
492 { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
493 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
494 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
495 { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
496 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
497 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
498 { nameb "_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
499 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
500 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
501 { nameb "_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
502 { nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
503 { nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
504 { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
505 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
506 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
507 { nameb "3_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
508 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
509 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
510 { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
511 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
512 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
513 { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
514 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
515 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
516 { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
517 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
518 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
519 { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
520 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
521 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }
522
523/* P: General 2-operand operation with parallell store
524 Syntax: <ia> src2, dst1 || <ib> src3, dst2
525 src2 = Indirect 0,1,IR0,IR1 (I)
526 dst1 = Register 0-7 (L)
527 src3 = Register 0-7 (H)
528 dst2 = Indirect 0,1,IR0,IR1 (J)
529 Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
530 LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
531 TOIEEE||STF
532 Alias: a||b, b||a
533*/
534#define P_CLASS_INSN(namea, nameb, opcode, level) \
535 { namea "_" nameb, opcode, 0xfe000000, "I,L|H,J", level }, \
536 { nameb "_" namea, opcode, 0xfe000000, "H,J|I,L", level }
537
538/* Q: General 3-operand operation with parallell store
539 Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
540 src1 = Register 0-7 (K)
541 src2 = Indirect 0,1,IR0,IR1 (I)
542 dst1 = Register 0-7 (L)
543 src3 = Register 0-7 (H)
544 dst2 = Indirect 0,1,IR0,IR1 (J)
545 Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
546 Alias: a||b, b||a, a3||b, b||a3
547*/
548#define Q_CLASS_INSN(namea, nameb, opcode, level) \
549 { namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
550 { nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
551 { namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
552 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
553
554/* QC: General commutative 3-operand operation with parallell store
555 Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
556 <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
557 src1 = Register 0-7 (K)
558 src2 = Indirect 0,1,IR0,IR1 (I)
559 dst1 = Register 0-7 (L)
560 src3 = Register 0-7 (H)
561 dst2 = Indirect 0,1,IR0,IR1 (J)
562 Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
563 OR3||STI, XOR3||STI
564 Alias: a||b, b||a, a3||b, b||a3
565*/
566#define QC_CLASS_INSN(namea, nameb, opcode, level) \
567 { namea "_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
568 { namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
569 { nameb "_" namea , opcode, 0xfe000000, "H,J|I,K;L", level }, \
570 { nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
571 { namea "3_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
572 { namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
573 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|I,K;L", level }, \
574 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
575
576/* R: General register integer operation
577 Syntax: <i> dst
578 dst = Register (R)
579 Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
580*/
581#define R_CLASS_INSN(name, opcode, level) \
582 { name, opcode, 0xffe0ffff, "R", level }
583
584/* RF: General register float operation
585 Syntax: <i> dst
586 dst = Register 0-11 (r)
587 Instr: 2/0 - POPF, PUSHF
588*/
589#define RF_CLASS_INSN(name, opcode, level) \
590 { name, opcode, 0xffe0ffff, "r", level }
591
592/* S: General 3-operand float operation
593 Syntax: <i> src2, src1, dst
594 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
595 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
596 dst = Register 0-11 (r)
597 Instr: 1/0 - SUBF3
598 Alias: i, i3
599*/
600#define S_CLASS_INSN(name, opcode, level) \
601 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
602 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
603 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
604 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
605 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
606 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
607 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
608 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
609 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
610 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
611 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
612 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
613
614/* SC: General commutative 3-operand float operation
615 Syntax: <i> src2, src1, dst - Manual
616 <i> src1, src2, dst
617 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
618 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
619 dst = Register 0-11 (r)
620 Instr: 2/0 - ADDF3, MPYF3
621 Alias: i, i3
622*/
623#define SC_CLASS_INSN(name, opcode, level) \
624 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
625 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
626 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
627 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
628 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
629 { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
630 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
631 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
632 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
633 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
634 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
635 { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
636 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
637 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
638
639/* S2: General 3-operand float operation with 2 args
640 Syntax: <i> src2, src1
641 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
642 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
643 Instr: 1/0 - CMPF3
644 Alias: i, i3
645*/
646#define S2_CLASS_INSN(name, opcode, level) \
647 { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \
648 { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \
649 { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \
650 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
651 { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
652 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
653 { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \
654 { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \
655 { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \
656 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
657 { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
658 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
659
660/* T: General 3-operand integer operand
661 Syntax: <i> src2, src1, dst
662 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
663 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
664 dst = Register (R)
665 Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
666 Alias: i, i3
667*/
668#define T_CLASS_INSN(name, opcode, level) \
669 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
670 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
671 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
672 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
673 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
674 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
675 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
676 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
677 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
678 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
679 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
680 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
681 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
682 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
683 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
684 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
685
686/* TC: General commutative 3-operand integer operation
687 Syntax: <i> src2, src1, dst
688 <i> src1, src2, dst
689 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
690 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
691 dst = Register (R)
692 Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
693 Alias: i, i3
694*/
695#define TC_CLASS_INSN(name, opcode, level) \
696 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
697 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
698 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
699 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
700 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
701 { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
702 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
703 { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
704 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
705 { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
706 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
707 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
708 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
709 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
710 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
711 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
712 { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
713 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
714 { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
715 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
716 { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
717 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
718
719/* T2: General 3-operand integer operation with 2 args
720 Syntax: <i> src2, src1
721 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
722 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
723 Instr: 1/0 - CMPI3
724 Alias: i, i3
725*/
726#define T2_CLASS_INSN(name, opcode, level) \
727 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
728 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
729 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
730 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
731 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
732 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
733 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
734 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
735 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
736 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
737 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
738 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
739 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
740 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
741 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
742 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
743
744/* T2C: General commutative 3-operand integer operation with 2 args
745 Syntax: <i> src2, src1 - Manual
746 <i> src1, src2
747 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
748 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
749 Instr: 1/0 - TSTB3
750 Alias: i, i3
751*/
752#define T2C_CLASS_INSN(name, opcode, level) \
753 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
754 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
755 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
756 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
757 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
758 { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
759 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
760 { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
761 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
762 { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
763 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
764 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
765 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
766 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
767 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
768 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
769 { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
770 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
771 { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
772 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
773 { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
774 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
775
776/* Z: Misc operations with or without arguments
777 Syntax: <i> <arg1>,...
778 Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD,
779 TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
780*/
781
026df7c5
NC		 782
783/* Define c3x opcodes for assembler and disassembler. */
784static const c4x_inst_t c3x_insts[] =
785{
786 /* Put synonyms after the desired forms in table so that they get
787 overwritten in the lookup table. The disassembler will thus
788 print the `proper' mnemonics. Note that the disassembler
789 only decodes the 11 MSBs, so instructions like ldp @0x500 will
790 be printed as ldiu 5, dp. Note that with parallel instructions,
791 the second part is executed before the first part, unless
792 the sti1||sti2 form is used. We also allow sti2||sti1
793 which is equivalent to the default sti||sti form.
44287f60
SS		 794 */
795 B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
796 P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
797 A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
798 P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
799 A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
800 TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
801 B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
802 SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
803 QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
804 A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
805 TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
806 QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
807 AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
808 TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
809 QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
810 AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
811 T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
812 A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
813 T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
814 Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
815 J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
816 J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
817 { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
818 { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
819 { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
820 { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
821 { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
822 B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
823 S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
824 A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
825 T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
826 D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
827 D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
828 AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
829 P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
830 BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
831 P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
832 { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
833 { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
834 { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
835 { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE }, /* Z_CLASS */
836 B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
837 B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
838 LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
839 P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
840 BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
841 B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
842 A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
843 LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
844 P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
845 AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
846 A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
847 { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
848 B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
849 { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
850 A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
851 T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
852 Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
853 { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
854 B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
855 SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
856 M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
857 QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
858 M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
859 A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
860 TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
861 M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
862 QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
863 M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
864 A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
865 B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
866 P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
867 A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
868 P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
869 A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
870 B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
871 AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
872 P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
873 AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
874 TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
875 QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
876 R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
877 RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
878 R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
879 RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
880 { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
881 { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
882 { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
883 { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
884 B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
885 R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
886 R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
887 R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
888 R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
889 { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
890 { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
891 A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
892 { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
893 A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
894 B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
895 LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
896 B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
897 A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
898 { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
899 { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
900 LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
901 A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
902 A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
903 T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
904 A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
905 B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
906 S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
907 Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
908 A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
909 T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
910 Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
911 A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
912 B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
913 A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
914 { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
915 { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
916 { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
917 AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
918 T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
919 AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
920 TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
921 QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
026df7c5
NC		 922
923 /* Dummy entry, not included in c3x_num_insts. This
924 lets code examine entry i + 1 without checking
925 if we've run off the end of the table. */
44287f60 926 { "", 0x0, 0x00, "", 0 }
026df7c5
NC		 927};
928
929const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1);
930
931/* Define c4x additional opcodes for assembler and disassembler. */
932static const c4x_inst_t c4x_insts[] =
933{
44287f60
SS		 934 J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
935 J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
936 B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
937 P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
938 { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
939 { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
940 { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
941 { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
942 A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
943 A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
944 A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
945 A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
946 AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
947 AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
948 AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
949 AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
950 AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
951 { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
952 { "ldhi", 0x1fe00000, 0xffe00000, "U,r" , OP_C4X }, /* Z_CLASS */
953 { "ldhi", 0x1fe00000, 0xffe00000, "#,r" , OP_C4X }, /* Z_CLASS */
954 { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
955 { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
956 A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
957 A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
958 AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
959 AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
960 A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
961 A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
962 A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
963 A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
964 A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
965 A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
966 A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
967 A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
968 A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
969 A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
970 A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
971 A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
972 A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
973 A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
974 A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
975 A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
976 A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
977 TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
978 A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
979 TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
980 BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
981 { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
982 { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
983 { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
984 { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
985 B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
986 { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
987 { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
988 B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
989 P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
026df7c5
NC		 990
991 /* Dummy entry, not included in num_insts. This
992 lets code examine entry i+1 without checking
993 if we've run off the end of the table. */
44287f60 994 { "", 0x0, 0x00, "", 0 }
026df7c5
NC		 995};
996
997const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
998
999
1000struct c4x_cond
1001{
1002 char * name;
1003 unsigned long cond;
1004};
1005
1006typedef struct c4x_cond c4x_cond_t;
1007
1008/* Define conditional branch/load suffixes. Put desired form for
1009 disassembler last. */
1010static const c4x_cond_t c4x_conds[] =
1011{
1012 { "u", 0x00 },
1013 { "c", 0x01 }, { "lo", 0x01 },
1014 { "ls", 0x02 },
1015 { "hi", 0x03 },
1016 { "nc", 0x04 }, { "hs", 0x04 },
1017 { "z", 0x05 }, { "eq", 0x05 },
1018 { "nz", 0x06 }, { "ne", 0x06 },
1019 { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
1020 { "le", 0x08 },
1021 { "p", 0x09 }, { "gt", 0x09 },
1022 { "nn", 0x0a }, { "ge", 0x0a },
1023 { "nv", 0x0c },
1024 { "v", 0x0d },
1025 { "nuf", 0x0e },
1026 { "uf", 0x0f },
1027 { "nlv", 0x10 },
1028 { "lv", 0x11 },
1029 { "nluf", 0x12 },
1030 { "luf", 0x13 },
1031 { "zuf", 0x14 },
1032 /* Dummy entry, not included in num_conds. This
1033 lets code examine entry i+1 without checking
1034 if we've run off the end of the table. */
1035 { "", 0x0}
1036};
1037
1038const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
1039
1040struct c4x_indirect
1041{
1042 char * name;
1043 unsigned long modn;
1044};
1045
1046typedef struct c4x_indirect c4x_indirect_t;
1047
1048/* Define indirect addressing modes where:
1049 d displacement (signed)
1050 y ir0
1051 z ir1 */
1052
1053static const c4x_indirect_t c4x_indirects[] =
1054{
1055 { "*+a(d)", 0x00 },
1056 { "*-a(d)", 0x01 },
1057 { "*++a(d)", 0x02 },
1058 { "*--a(d)", 0x03 },
1059 { "*a++(d)", 0x04 },
1060 { "*a--(d)", 0x05 },
1061 { "*a++(d)%", 0x06 },
1062 { "*a--(d)%", 0x07 },
1063 { "*+a(y)", 0x08 },
1064 { "*-a(y)", 0x09 },
1065 { "*++a(y)", 0x0a },
1066 { "*--a(y)", 0x0b },
1067 { "*a++(y)", 0x0c },
1068 { "*a--(y)", 0x0d },
1069 { "*a++(y)%", 0x0e },
1070 { "*a--(y)%", 0x0f },
1071 { "*+a(z)", 0x10 },
1072 { "*-a(z)", 0x11 },
1073 { "*++a(z)", 0x12 },
1074 { "*--a(z)", 0x13 },
1075 { "*a++(z)", 0x14 },
1076 { "*a--(z)", 0x15 },
1077 { "*a++(z)%", 0x16 },
1078 { "*a--(z)%", 0x17 },
1079 { "*a", 0x18 },
1080 { "*a++(y)b", 0x19 },
1081 /* Dummy entry, not included in num_indirects. This
1082 lets code examine entry i+1 without checking
1083 if we've run off the end of the table. */
1084 { "", 0x0}
1085};
1086
1087#define C3X_MODN_MAX 0x19
1088
1089const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
GDB Binutils - Deliverables
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