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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba AD |
36 | |
37 | #define DRM_AMDGPU_GEM_CREATE 0x00 | |
38 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
39 | #define DRM_AMDGPU_CTX 0x02 | |
40 | #define DRM_AMDGPU_BO_LIST 0x03 | |
41 | #define DRM_AMDGPU_CS 0x04 | |
42 | #define DRM_AMDGPU_INFO 0x05 | |
43 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
44 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
45 | #define DRM_AMDGPU_GEM_VA 0x08 | |
46 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
47 | #define DRM_AMDGPU_GEM_OP 0x10 | |
48 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
49 | ||
50 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
51 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
52 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
53 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
54 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
55 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
56 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
57 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 58 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
59 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
60 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
62 | ||
63 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
64 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
65 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
66 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
67 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
68 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
69 | ||
81629cba AD |
70 | /* Flag that CPU access will be required for the case of VRAM domain */ |
71 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
72 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
73 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 74 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 75 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
81629cba | 76 | |
81629cba AD |
77 | struct drm_amdgpu_gem_create_in { |
78 | /** the requested memory size */ | |
79 | uint64_t bo_size; | |
80 | /** physical start_addr alignment in bytes for some HW requirements */ | |
81 | uint64_t alignment; | |
82 | /** the requested memory domains */ | |
83 | uint64_t domains; | |
84 | /** allocation flags */ | |
85 | uint64_t domain_flags; | |
86 | }; | |
87 | ||
88 | struct drm_amdgpu_gem_create_out { | |
89 | /** returned GEM object handle */ | |
90 | uint32_t handle; | |
91 | uint32_t _pad; | |
92 | }; | |
93 | ||
94 | union drm_amdgpu_gem_create { | |
95 | struct drm_amdgpu_gem_create_in in; | |
96 | struct drm_amdgpu_gem_create_out out; | |
97 | }; | |
98 | ||
99 | /** Opcode to create new residency list. */ | |
100 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
101 | /** Opcode to destroy previously created residency list */ | |
102 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
103 | /** Opcode to update resource information in the list */ | |
104 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
105 | ||
106 | struct drm_amdgpu_bo_list_in { | |
107 | /** Type of operation */ | |
108 | uint32_t operation; | |
109 | /** Handle of list or 0 if we want to create one */ | |
110 | uint32_t list_handle; | |
111 | /** Number of BOs in list */ | |
112 | uint32_t bo_number; | |
113 | /** Size of each element describing BO */ | |
114 | uint32_t bo_info_size; | |
115 | /** Pointer to array describing BOs */ | |
116 | uint64_t bo_info_ptr; | |
117 | }; | |
118 | ||
119 | struct drm_amdgpu_bo_list_entry { | |
120 | /** Handle of BO */ | |
121 | uint32_t bo_handle; | |
122 | /** New (if specified) BO priority to be used during migration */ | |
123 | uint32_t bo_priority; | |
124 | }; | |
125 | ||
126 | struct drm_amdgpu_bo_list_out { | |
127 | /** Handle of resource list */ | |
128 | uint32_t list_handle; | |
129 | uint32_t _pad; | |
130 | }; | |
131 | ||
132 | union drm_amdgpu_bo_list { | |
133 | struct drm_amdgpu_bo_list_in in; | |
134 | struct drm_amdgpu_bo_list_out out; | |
135 | }; | |
136 | ||
137 | /* context related */ | |
138 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
139 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
140 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
141 | ||
d94aed5a MO |
142 | /* GPU reset status */ |
143 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
144 | /* this the context caused it */ |
145 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
146 | /* some other context caused it */ | |
147 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
148 | /* unknown cause */ | |
149 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 150 | |
81629cba | 151 | struct drm_amdgpu_ctx_in { |
675da0dd | 152 | /** AMDGPU_CTX_OP_* */ |
81629cba | 153 | uint32_t op; |
675da0dd | 154 | /** For future use, no flags defined so far */ |
81629cba AD |
155 | uint32_t flags; |
156 | uint32_t ctx_id; | |
157 | uint32_t _pad; | |
158 | }; | |
159 | ||
160 | union drm_amdgpu_ctx_out { | |
161 | struct { | |
162 | uint32_t ctx_id; | |
163 | uint32_t _pad; | |
164 | } alloc; | |
165 | ||
166 | struct { | |
675da0dd | 167 | /** For future use, no flags defined so far */ |
81629cba | 168 | uint64_t flags; |
d94aed5a MO |
169 | /** Number of resets caused by this context so far. */ |
170 | uint32_t hangs; | |
171 | /** Reset status since the last call of the ioctl. */ | |
172 | uint32_t reset_status; | |
81629cba AD |
173 | } state; |
174 | }; | |
175 | ||
176 | union drm_amdgpu_ctx { | |
177 | struct drm_amdgpu_ctx_in in; | |
178 | union drm_amdgpu_ctx_out out; | |
179 | }; | |
180 | ||
181 | /* | |
182 | * This is not a reliable API and you should expect it to fail for any | |
183 | * number of reasons and have fallback path that do not use userptr to | |
184 | * perform any operation. | |
185 | */ | |
186 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
187 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
188 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
189 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
190 | ||
191 | struct drm_amdgpu_gem_userptr { | |
192 | uint64_t addr; | |
193 | uint64_t size; | |
675da0dd | 194 | /* AMDGPU_GEM_USERPTR_* */ |
81629cba | 195 | uint32_t flags; |
675da0dd | 196 | /* Resulting GEM handle */ |
81629cba AD |
197 | uint32_t handle; |
198 | }; | |
199 | ||
fbd76d59 MO |
200 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
201 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
202 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
203 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
204 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
205 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
206 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
207 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
208 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
209 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
210 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
211 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
212 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
213 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
214 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
215 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
216 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
217 | ||
218 | #define AMDGPU_TILING_SET(field, value) \ | |
219 | (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) | |
220 | #define AMDGPU_TILING_GET(value, field) \ | |
221 | (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) | |
81629cba AD |
222 | |
223 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
224 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
225 | ||
226 | /** The same structure is shared for input/output */ | |
227 | struct drm_amdgpu_gem_metadata { | |
675da0dd CK |
228 | /** GEM Object handle */ |
229 | uint32_t handle; | |
230 | /** Do we want get or set metadata */ | |
231 | uint32_t op; | |
81629cba | 232 | struct { |
675da0dd | 233 | /** For future use, no flags defined so far */ |
81629cba | 234 | uint64_t flags; |
675da0dd CK |
235 | /** family specific tiling info */ |
236 | uint64_t tiling_info; | |
81629cba AD |
237 | uint32_t data_size_bytes; |
238 | uint32_t data[64]; | |
239 | } data; | |
240 | }; | |
241 | ||
242 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd CK |
243 | /** the GEM object handle */ |
244 | uint32_t handle; | |
81629cba AD |
245 | uint32_t _pad; |
246 | }; | |
247 | ||
248 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd CK |
249 | /** mmap offset from the vma offset manager */ |
250 | uint64_t addr_ptr; | |
81629cba AD |
251 | }; |
252 | ||
253 | union drm_amdgpu_gem_mmap { | |
254 | struct drm_amdgpu_gem_mmap_in in; | |
255 | struct drm_amdgpu_gem_mmap_out out; | |
256 | }; | |
257 | ||
258 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd CK |
259 | /** GEM object handle */ |
260 | uint32_t handle; | |
261 | /** For future use, no flags defined so far */ | |
81629cba | 262 | uint32_t flags; |
675da0dd CK |
263 | /** Absolute timeout to wait */ |
264 | uint64_t timeout; | |
81629cba AD |
265 | }; |
266 | ||
267 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd CK |
268 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
269 | uint32_t status; | |
270 | /** Returned current memory domain */ | |
271 | uint32_t domain; | |
81629cba AD |
272 | }; |
273 | ||
274 | union drm_amdgpu_gem_wait_idle { | |
275 | struct drm_amdgpu_gem_wait_idle_in in; | |
276 | struct drm_amdgpu_gem_wait_idle_out out; | |
277 | }; | |
278 | ||
279 | struct drm_amdgpu_wait_cs_in { | |
675da0dd | 280 | /** Command submission handle */ |
81629cba | 281 | uint64_t handle; |
675da0dd | 282 | /** Absolute timeout to wait */ |
81629cba AD |
283 | uint64_t timeout; |
284 | uint32_t ip_type; | |
285 | uint32_t ip_instance; | |
286 | uint32_t ring; | |
66b3cf2a | 287 | uint32_t ctx_id; |
81629cba AD |
288 | }; |
289 | ||
290 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 291 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
81629cba AD |
292 | uint64_t status; |
293 | }; | |
294 | ||
295 | union drm_amdgpu_wait_cs { | |
296 | struct drm_amdgpu_wait_cs_in in; | |
297 | struct drm_amdgpu_wait_cs_out out; | |
298 | }; | |
299 | ||
675da0dd CK |
300 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
301 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
302 | ||
81629cba AD |
303 | /* Sets or returns a value associated with a buffer. */ |
304 | struct drm_amdgpu_gem_op { | |
675da0dd CK |
305 | /** GEM object handle */ |
306 | uint32_t handle; | |
307 | /** AMDGPU_GEM_OP_* */ | |
308 | uint32_t op; | |
309 | /** Input or return value */ | |
310 | uint64_t value; | |
81629cba AD |
311 | }; |
312 | ||
81629cba AD |
313 | #define AMDGPU_VA_OP_MAP 1 |
314 | #define AMDGPU_VA_OP_UNMAP 2 | |
315 | ||
fc220f65 CK |
316 | /* Delay the page table update till the next CS */ |
317 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
318 | ||
81629cba AD |
319 | /* Mapping flags */ |
320 | /* readable mapping */ | |
321 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
322 | /* writable mapping */ | |
323 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
324 | /* executable mapping, new for VI */ | |
325 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
326 | ||
34b5f6a6 | 327 | struct drm_amdgpu_gem_va { |
675da0dd | 328 | /** GEM object handle */ |
81629cba AD |
329 | uint32_t handle; |
330 | uint32_t _pad; | |
675da0dd | 331 | /** AMDGPU_VA_OP_* */ |
81629cba | 332 | uint32_t operation; |
675da0dd | 333 | /** AMDGPU_VM_PAGE_* */ |
81629cba | 334 | uint32_t flags; |
675da0dd | 335 | /** va address to assign . Must be correctly aligned.*/ |
81629cba | 336 | uint64_t va_address; |
675da0dd | 337 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
81629cba | 338 | uint64_t offset_in_bo; |
675da0dd | 339 | /** Specify mapping size. Must be correctly aligned. */ |
81629cba AD |
340 | uint64_t map_size; |
341 | }; | |
342 | ||
81629cba AD |
343 | #define AMDGPU_HW_IP_GFX 0 |
344 | #define AMDGPU_HW_IP_COMPUTE 1 | |
345 | #define AMDGPU_HW_IP_DMA 2 | |
346 | #define AMDGPU_HW_IP_UVD 3 | |
347 | #define AMDGPU_HW_IP_VCE 4 | |
348 | #define AMDGPU_HW_IP_NUM 5 | |
349 | ||
350 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
351 | ||
352 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
353 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 354 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 355 | |
81629cba AD |
356 | struct drm_amdgpu_cs_chunk { |
357 | uint32_t chunk_id; | |
358 | uint32_t length_dw; | |
359 | uint64_t chunk_data; | |
360 | }; | |
361 | ||
362 | struct drm_amdgpu_cs_in { | |
363 | /** Rendering context id */ | |
364 | uint32_t ctx_id; | |
365 | /** Handle of resource list associated with CS */ | |
366 | uint32_t bo_list_handle; | |
367 | uint32_t num_chunks; | |
368 | uint32_t _pad; | |
675da0dd | 369 | /** this points to uint64_t * which point to cs chunks */ |
81629cba AD |
370 | uint64_t chunks; |
371 | }; | |
372 | ||
373 | struct drm_amdgpu_cs_out { | |
374 | uint64_t handle; | |
375 | }; | |
376 | ||
377 | union drm_amdgpu_cs { | |
675da0dd CK |
378 | struct drm_amdgpu_cs_in in; |
379 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
380 | }; |
381 | ||
382 | /* Specify flags to be used for IB */ | |
383 | ||
384 | /* This IB should be submitted to CE */ | |
385 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
386 | ||
aa2bdb24 | 387 | /* CE Preamble */ |
cab6d57c | 388 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 389 | |
81629cba | 390 | struct drm_amdgpu_cs_chunk_ib { |
3ccec53c | 391 | uint32_t _pad; |
675da0dd CK |
392 | /** AMDGPU_IB_FLAG_* */ |
393 | uint32_t flags; | |
394 | /** Virtual address to begin IB execution */ | |
395 | uint64_t va_start; | |
396 | /** Size of submission */ | |
397 | uint32_t ib_bytes; | |
398 | /** HW IP to submit to */ | |
399 | uint32_t ip_type; | |
400 | /** HW IP index of the same type to submit to */ | |
401 | uint32_t ip_instance; | |
402 | /** Ring index to submit to */ | |
403 | uint32_t ring; | |
81629cba AD |
404 | }; |
405 | ||
2b48d323 CK |
406 | struct drm_amdgpu_cs_chunk_dep { |
407 | uint32_t ip_type; | |
408 | uint32_t ip_instance; | |
409 | uint32_t ring; | |
410 | uint32_t ctx_id; | |
411 | uint64_t handle; | |
412 | }; | |
413 | ||
81629cba AD |
414 | struct drm_amdgpu_cs_chunk_fence { |
415 | uint32_t handle; | |
416 | uint32_t offset; | |
417 | }; | |
418 | ||
419 | struct drm_amdgpu_cs_chunk_data { | |
420 | union { | |
421 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
422 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
423 | }; | |
424 | }; | |
425 | ||
426 | /** | |
427 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
428 | * | |
429 | */ | |
430 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
431 | ||
432 | /* indicate if acceleration can be working */ | |
433 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
434 | /* get the crtc_id from the mode object id? */ | |
435 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
436 | /* query hw IP info */ | |
437 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
438 | /* query hw IP instance count for the specified type */ | |
439 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
440 | /* timestamp for GL_ARB_timer_query */ | |
441 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
442 | /* Query the firmware version */ | |
443 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
444 | /* Subquery id: Query VCE firmware version */ | |
445 | #define AMDGPU_INFO_FW_VCE 0x1 | |
446 | /* Subquery id: Query UVD firmware version */ | |
447 | #define AMDGPU_INFO_FW_UVD 0x2 | |
448 | /* Subquery id: Query GMC firmware version */ | |
449 | #define AMDGPU_INFO_FW_GMC 0x03 | |
450 | /* Subquery id: Query GFX ME firmware version */ | |
451 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
452 | /* Subquery id: Query GFX PFP firmware version */ | |
453 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
454 | /* Subquery id: Query GFX CE firmware version */ | |
455 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
456 | /* Subquery id: Query GFX RLC firmware version */ | |
457 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
458 | /* Subquery id: Query GFX MEC firmware version */ | |
459 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
460 | /* Subquery id: Query SMC firmware version */ | |
461 | #define AMDGPU_INFO_FW_SMC 0x0a | |
462 | /* Subquery id: Query SDMA firmware version */ | |
463 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
464 | /* number of bytes moved for TTM migration */ | |
465 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
466 | /* the used VRAM size */ | |
467 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
468 | /* the used GTT size */ | |
469 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
470 | /* Information about GDS, etc. resource configuration */ | |
471 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
472 | /* Query information about VRAM and GTT domains */ | |
473 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
474 | /* Query information about register in MMR address space*/ | |
475 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
476 | /* Query information about device: rev id, family, etc. */ | |
477 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
478 | /* visible vram usage */ | |
479 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
480 | ||
481 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
482 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
483 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
484 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
485 | ||
486 | /* Input structure for the INFO ioctl */ | |
487 | struct drm_amdgpu_info { | |
488 | /* Where the return value will be stored */ | |
489 | uint64_t return_pointer; | |
490 | /* The size of the return value. Just like "size" in "snprintf", | |
491 | * it limits how many bytes the kernel can write. */ | |
492 | uint32_t return_size; | |
493 | /* The query request id. */ | |
494 | uint32_t query; | |
495 | ||
496 | union { | |
497 | struct { | |
498 | uint32_t id; | |
499 | uint32_t _pad; | |
500 | } mode_crtc; | |
501 | ||
502 | struct { | |
503 | /** AMDGPU_HW_IP_* */ | |
504 | uint32_t type; | |
505 | /** | |
675da0dd CK |
506 | * Index of the IP if there are more IPs of the same |
507 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba AD |
508 | */ |
509 | uint32_t ip_instance; | |
510 | } query_hw_ip; | |
511 | ||
512 | struct { | |
513 | uint32_t dword_offset; | |
675da0dd CK |
514 | /** number of registers to read */ |
515 | uint32_t count; | |
81629cba | 516 | uint32_t instance; |
675da0dd | 517 | /** For future use, no flags defined so far */ |
81629cba AD |
518 | uint32_t flags; |
519 | } read_mmr_reg; | |
520 | ||
521 | struct { | |
522 | /** AMDGPU_INFO_FW_* */ | |
523 | uint32_t fw_type; | |
675da0dd CK |
524 | /** |
525 | * Index of the IP if there are more IPs of | |
526 | * the same type. | |
527 | */ | |
81629cba AD |
528 | uint32_t ip_instance; |
529 | /** | |
530 | * Index of the engine. Whether this is used depends | |
531 | * on the firmware type. (e.g. MEC, SDMA) | |
532 | */ | |
533 | uint32_t index; | |
534 | uint32_t _pad; | |
535 | } query_fw; | |
536 | }; | |
537 | }; | |
538 | ||
539 | struct drm_amdgpu_info_gds { | |
540 | /** GDS GFX partition size */ | |
541 | uint32_t gds_gfx_partition_size; | |
542 | /** GDS compute partition size */ | |
543 | uint32_t compute_partition_size; | |
544 | /** total GDS memory size */ | |
545 | uint32_t gds_total_size; | |
546 | /** GWS size per GFX partition */ | |
547 | uint32_t gws_per_gfx_partition; | |
548 | /** GSW size per compute partition */ | |
549 | uint32_t gws_per_compute_partition; | |
550 | /** OA size per GFX partition */ | |
551 | uint32_t oa_per_gfx_partition; | |
552 | /** OA size per compute partition */ | |
553 | uint32_t oa_per_compute_partition; | |
554 | uint32_t _pad; | |
555 | }; | |
556 | ||
557 | struct drm_amdgpu_info_vram_gtt { | |
558 | uint64_t vram_size; | |
559 | uint64_t vram_cpu_accessible_size; | |
560 | uint64_t gtt_size; | |
561 | }; | |
562 | ||
563 | struct drm_amdgpu_info_firmware { | |
564 | uint32_t ver; | |
565 | uint32_t feature; | |
566 | }; | |
567 | ||
81c59f54 KW |
568 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
569 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
570 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
571 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
572 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
573 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
574 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
575 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
576 | ||
81629cba AD |
577 | struct drm_amdgpu_info_device { |
578 | /** PCI Device ID */ | |
579 | uint32_t device_id; | |
580 | /** Internal chip revision: A0, A1, etc.) */ | |
581 | uint32_t chip_rev; | |
582 | uint32_t external_rev; | |
583 | /** Revision id in PCI Config space */ | |
584 | uint32_t pci_rev; | |
585 | uint32_t family; | |
586 | uint32_t num_shader_engines; | |
587 | uint32_t num_shader_arrays_per_engine; | |
675da0dd CK |
588 | /* in KHz */ |
589 | uint32_t gpu_counter_freq; | |
590 | uint64_t max_engine_clock; | |
591 | uint64_t max_memory_clock; | |
81629cba AD |
592 | /* cu information */ |
593 | uint32_t cu_active_number; | |
594 | uint32_t cu_ao_mask; | |
595 | uint32_t cu_bitmap[4][4]; | |
596 | /** Render backend pipe mask. One render backend is CB+DB. */ | |
597 | uint32_t enabled_rb_pipes_mask; | |
598 | uint32_t num_rb_pipes; | |
599 | uint32_t num_hw_gfx_contexts; | |
600 | uint32_t _pad; | |
601 | uint64_t ids_flags; | |
602 | /** Starting virtual address for UMDs. */ | |
603 | uint64_t virtual_address_offset; | |
02b70c8c JZ |
604 | /** The maximum virtual address */ |
605 | uint64_t virtual_address_max; | |
81629cba AD |
606 | /** Required alignment of virtual addresses. */ |
607 | uint32_t virtual_address_alignment; | |
608 | /** Page table entry - fragment size */ | |
609 | uint32_t pte_fragment_size; | |
610 | uint32_t gart_page_size; | |
a101a899 KW |
611 | /** constant engine ram size*/ |
612 | uint32_t ce_ram_size; | |
cab6d57c | 613 | /** video memory type info*/ |
81c59f54 KW |
614 | uint32_t vram_type; |
615 | /** video memory bit width*/ | |
616 | uint32_t vram_bit_width; | |
fa92754e LL |
617 | /* vce harvesting instance */ |
618 | uint32_t vce_harvest_config; | |
81629cba AD |
619 | }; |
620 | ||
621 | struct drm_amdgpu_info_hw_ip { | |
622 | /** Version of h/w IP */ | |
623 | uint32_t hw_ip_version_major; | |
624 | uint32_t hw_ip_version_minor; | |
625 | /** Capabilities */ | |
626 | uint64_t capabilities_flags; | |
71062f43 KW |
627 | /** command buffer address start alignment*/ |
628 | uint32_t ib_start_alignment; | |
629 | /** command buffer size alignment*/ | |
630 | uint32_t ib_size_alignment; | |
81629cba AD |
631 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
632 | uint32_t available_rings; | |
633 | uint32_t _pad; | |
634 | }; | |
635 | ||
636 | /* | |
637 | * Supported GPU families | |
638 | */ | |
639 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
640 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ | |
641 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
642 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
643 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ | |
644 | ||
645 | #endif |