[deliverable/linux.git] / include / uapi / drm / nouveau_drm.h

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__

#define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

#define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
#define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)

#define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP       0x00000001
#define NOUVEAU_GEM_TILE_32BPP       0x00000002
#define NOUVEAU_GEM_TILE_ZETA        0x00000004
#define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008

struct drm_nouveau_gem_info {
	__u32 handle;
	__u32 domain;
	__u64 size;
	__u64 offset;
	__u64 map_handle;
	__u32 tile_mode;
	__u32 tile_flags;
};

struct drm_nouveau_gem_new {
	struct drm_nouveau_gem_info info;
	__u32 channel_hint;
	__u32 align;
};

#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
	__u32 valid;
	__u32 domain;
	__u64 offset;
};

struct drm_nouveau_gem_pushbuf_bo {
	__u64 user_priv;
	__u32 handle;
	__u32 read_domains;
	__u32 write_domains;
	__u32 valid_domains;
	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
};

#define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR   (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc {
	__u32 reloc_bo_index;
	__u32 reloc_bo_offset;
	__u32 bo_index;
	__u32 flags;
	__u32 data;
	__u32 vor;
	__u32 tor;
};

#define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push {
	__u32 bo_index;
	__u32 pad;
	__u64 offset;
	__u64 length;
};

struct drm_nouveau_gem_pushbuf {
	__u32 channel;
	__u32 nr_buffers;
	__u64 buffers;
	__u32 nr_relocs;
	__u32 nr_push;
	__u64 relocs;
	__u64 push;
	__u32 suffix0;
	__u32 suffix1;
	__u64 vram_available;
	__u64 gart_available;
};

#define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
struct drm_nouveau_gem_cpu_prep {
	__u32 handle;
	__u32 flags;
};

struct drm_nouveau_gem_cpu_fini {
	__u32 handle;
};

#define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
#define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_ALLOC      0x02 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_FREE       0x03 /* deprecated */
#define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
#define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
#define DRM_NOUVEAU_NVIF               0x07
#define DRM_NOUVEAU_GEM_NEW            0x40
#define DRM_NOUVEAU_GEM_PUSHBUF        0x41
#define DRM_NOUVEAU_GEM_CPU_PREP       0x42
#define DRM_NOUVEAU_GEM_CPU_FINI       0x43
#define DRM_NOUVEAU_GEM_INFO           0x44

#define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
#define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)

#if defined(__cplusplus)
}
#endif

#endif /* __NOUVEAU_DRM_H__ */
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#ifndef __NOUVEAU_DRM_H__
	26	#define __NOUVEAU_DRM_H__
	27
27111a23 BS	28	#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
27111a23 BS	29
c6734c68	30	#include "drm.h"
8860487e	31
8daf6359 EV	32	#if defined(__cplusplus)
	33	extern "C" {
	34	#endif
	35
6ee73861 BS	36	#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
	37	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	38	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	39	#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
996f545f	40	#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
6ee73861	41
8f7286f8	42	#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
f13b3263 FJ	43	#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
	44	#define NOUVEAU_GEM_TILE_16BPP 0x00000001
	45	#define NOUVEAU_GEM_TILE_32BPP 0x00000002
	46	#define NOUVEAU_GEM_TILE_ZETA 0x00000004
	47	#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
	48
6ee73861	49	struct drm_nouveau_gem_info {
8860487e MR	50	__u32 handle;
	51	__u32 domain;
	52	__u64 size;
	53	__u64 offset;
	54	__u64 map_handle;
	55	__u32 tile_mode;
	56	__u32 tile_flags;
6ee73861 BS	57	};
	58
	59	struct drm_nouveau_gem_new {
	60	struct drm_nouveau_gem_info info;
8860487e MR	61	__u32 channel_hint;
8860487e MR	62	__u32 align;
6ee73861 BS	63	};
6ee73861 BS	64
a1606a95 BS	65	#define NOUVEAU_GEM_MAX_BUFFERS 1024
a1606a95 BS	66	struct drm_nouveau_gem_pushbuf_bo_presumed {
8860487e MR	67	__u32 valid;
	68	__u32 domain;
	69	__u64 offset;
a1606a95 BS	70	};
a1606a95 BS	71
6ee73861	72	struct drm_nouveau_gem_pushbuf_bo {
8860487e MR	73	__u64 user_priv;
	74	__u32 handle;
	75	__u32 read_domains;
	76	__u32 write_domains;
	77	__u32 valid_domains;
a1606a95	78	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
6ee73861 BS	79	};
	80
	81	#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
	82	#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
	83	#define NOUVEAU_GEM_RELOC_OR (1 << 2)
a1606a95	84	#define NOUVEAU_GEM_MAX_RELOCS 1024
6ee73861	85	struct drm_nouveau_gem_pushbuf_reloc {
8860487e MR	86	__u32 reloc_bo_index;
	87	__u32 reloc_bo_offset;
	88	__u32 bo_index;
	89	__u32 flags;
	90	__u32 data;
	91	__u32 vor;
	92	__u32 tor;
6ee73861 BS	93	};
6ee73861 BS	94
a1606a95 BS	95	#define NOUVEAU_GEM_MAX_PUSH 512
a1606a95 BS	96	struct drm_nouveau_gem_pushbuf_push {
8860487e MR	97	__u32 bo_index;
	98	__u32 pad;
	99	__u64 offset;
	100	__u64 length;
a1606a95	101	};
6ee73861 BS	102
6ee73861 BS	103	struct drm_nouveau_gem_pushbuf {
8860487e MR	104	__u32 channel;
	105	__u32 nr_buffers;
	106	__u64 buffers;
	107	__u32 nr_relocs;
	108	__u32 nr_push;
	109	__u64 relocs;
	110	__u64 push;
	111	__u32 suffix0;
	112	__u32 suffix1;
	113	__u64 vram_available;
	114	__u64 gart_available;
6ee73861 BS	115	};
6ee73861 BS	116
6ee73861	117	#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
6ee73861 BS	118	#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
6ee73861 BS	119	struct drm_nouveau_gem_cpu_prep {
8860487e MR	120	__u32 handle;
8860487e MR	121	__u32 flags;
6ee73861 BS	122	};
	123
	124	struct drm_nouveau_gem_cpu_fini {
8860487e	125	__u32 handle;
6ee73861 BS	126	};
6ee73861 BS	127
2a259a3d BS	128	#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
	129	#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
	130	#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
	131	#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
	132	#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
	133	#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
	134	#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
27111a23	135	#define DRM_NOUVEAU_NVIF 0x07
6ee73861 BS	136	#define DRM_NOUVEAU_GEM_NEW 0x40
6ee73861 BS	137	#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
a1606a95 BS	138	#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
	139	#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
	140	#define DRM_NOUVEAU_GEM_INFO 0x44
6ee73861	141
1b2f1489 DA	142	#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
	143	#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
	144	#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
	145	#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
	146	#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
	147
8daf6359 EV	148	#if defined(__cplusplus)
	149	}
	150	#endif
	151
6ee73861	152	#endif /* __NOUVEAU_DRM_H__ */