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Staging: fbtft: Fix bug in fbtft-core
[deliverable/linux.git] / include / uapi / drm / radeon_drm.h
CommitLineData
1da177e4
LT		 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
e13af53e 36#include "drm.h"
1d7f83d5 37
6db26a94
EV		 38#if defined(__cplusplus)
39extern "C" {
40#endif
41
1da177e4
LT		 42/* WARNING: If you change any of these defines, make sure to change the
43 * defines in the X server file (radeon_sarea.h)
44 */
45#ifndef __RADEON_SAREA_DEFINES__
46#define __RADEON_SAREA_DEFINES__
47
48/* Old style state flags, required for sarea interface (1.1 and 1.2
49 * clears) and 1.2 drm_vertex2 ioctl.
50 */
51#define RADEON_UPLOAD_CONTEXT 0x00000001
52#define RADEON_UPLOAD_VERTFMT 0x00000002
53#define RADEON_UPLOAD_LINE 0x00000004
54#define RADEON_UPLOAD_BUMPMAP 0x00000008
55#define RADEON_UPLOAD_MASKS 0x00000010
56#define RADEON_UPLOAD_VIEWPORT 0x00000020
57#define RADEON_UPLOAD_SETUP 0x00000040
58#define RADEON_UPLOAD_TCL 0x00000080
59#define RADEON_UPLOAD_MISC 0x00000100
60#define RADEON_UPLOAD_TEX0 0x00000200
61#define RADEON_UPLOAD_TEX1 0x00000400
62#define RADEON_UPLOAD_TEX2 0x00000800
63#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
64#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
65#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
b5e89ed5 66#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
1da177e4 67#define RADEON_REQUIRE_QUIESCENCE 0x00010000
b5e89ed5 68#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
1da177e4
LT		 69#define RADEON_UPLOAD_ALL 0x003effff
70#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
71
1da177e4
LT		 72/* New style per-packet identifiers for use in cmd_buffer ioctl with
73 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
74 * state bits and the packet size:
75 */
b5e89ed5
DA		 76#define RADEON_EMIT_PP_MISC 0 /* context/7 */
77#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
78#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
79#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
80#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
81#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
82#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
83#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
84#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
85#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
86#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
87#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
88#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
89#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
90#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
91#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
92#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
93#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
94#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
95#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
96#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
97#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
98#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
99#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
100#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
101#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
102#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
103#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
104#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
105#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
106#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
107#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
108#define R200_EMIT_VAP_CTL 32 /* vap/1 */
109#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
110#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
111#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
112#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
113#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
114#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
115#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
116#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
117#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
118#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
119#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
120#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
121#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
122#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
123#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
124#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
125#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
126#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
127#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
128#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
129#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
130#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
131#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
132#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
133#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
134#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
135#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
136#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
1da177e4
LT		 137#define R200_EMIT_PP_CUBIC_FACES_0 61
138#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
139#define R200_EMIT_PP_CUBIC_FACES_1 63
140#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
141#define R200_EMIT_PP_CUBIC_FACES_2 65
142#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
143#define R200_EMIT_PP_CUBIC_FACES_3 67
144#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
145#define R200_EMIT_PP_CUBIC_FACES_4 69
146#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
147#define R200_EMIT_PP_CUBIC_FACES_5 71
148#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
149#define RADEON_EMIT_PP_TEX_SIZE_0 73
150#define RADEON_EMIT_PP_TEX_SIZE_1 74
151#define RADEON_EMIT_PP_TEX_SIZE_2 75
152#define R200_EMIT_RB3D_BLENDCOLOR 76
153#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
154#define RADEON_EMIT_PP_CUBIC_FACES_0 78
155#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
156#define RADEON_EMIT_PP_CUBIC_FACES_1 80
157#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
158#define RADEON_EMIT_PP_CUBIC_FACES_2 82
159#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
160#define R200_EMIT_PP_TRI_PERF_CNTL 84
9d17601c
DA		 161#define R200_EMIT_PP_AFS_0 85
162#define R200_EMIT_PP_AFS_1 86
163#define R200_EMIT_ATF_TFACTOR 87
164#define R200_EMIT_PP_TXCTLALL_0 88
165#define R200_EMIT_PP_TXCTLALL_1 89
166#define R200_EMIT_PP_TXCTLALL_2 90
167#define R200_EMIT_PP_TXCTLALL_3 91
168#define R200_EMIT_PP_TXCTLALL_4 92
169#define R200_EMIT_PP_TXCTLALL_5 93
d6fece05
DA		 170#define R200_EMIT_VAP_PVS_CNTL 94
171#define RADEON_MAX_STATE_PACKETS 95
1da177e4
LT		 172
173/* Commands understood by cmd_buffer ioctl. More can be added but
174 * obviously these can't be removed or changed:
175 */
b5e89ed5
DA		 176#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
177#define RADEON_CMD_SCALARS 2 /* emit scalar data */
178#define RADEON_CMD_VECTORS 3 /* emit vector data */
179#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
180#define RADEON_CMD_PACKET3 5 /* emit hw packet */
181#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
182#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
183#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
184 * doesn't make the cpu wait, just
185 * the graphics hardware */
d6fece05 186#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
1da177e4
LT		 187
188typedef union {
189 int i;
b5e89ed5 190 struct {
1da177e4
LT		 191 unsigned char cmd_type, pad0, pad1, pad2;
192 } header;
b5e89ed5 193 struct {
1da177e4
LT		 194 unsigned char cmd_type, packet_id, pad0, pad1;
195 } packet;
b5e89ed5
DA		 196 struct {
197 unsigned char cmd_type, offset, stride, count;
1da177e4 198 } scalars;
b5e89ed5
DA		 199 struct {
200 unsigned char cmd_type, offset, stride, count;
1da177e4 201 } vectors;
d6fece05
DA		 202 struct {
203 unsigned char cmd_type, addr_lo, addr_hi, count;
204 } veclinear;
b5e89ed5
DA		 205 struct {
206 unsigned char cmd_type, buf_idx, pad0, pad1;
1da177e4 207 } dma;
b5e89ed5
DA		 208 struct {
209 unsigned char cmd_type, flags, pad0, pad1;
1da177e4
LT		 210 } wait;
211} drm_radeon_cmd_header_t;
212
213#define RADEON_WAIT_2D 0x1
214#define RADEON_WAIT_3D 0x2
215
414ed537
DA		 216/* Allowed parameters for R300_CMD_PACKET3
217 */
218#define R300_CMD_PACKET3_CLEAR 0
219#define R300_CMD_PACKET3_RAW 1
220
221/* Commands understood by cmd_buffer ioctl for R300.
222 * The interface has not been stabilized, so some of these may be removed
223 * and eventually reordered before stabilization.
224 */
b5e89ed5
DA		 225#define R300_CMD_PACKET0 1
226#define R300_CMD_VPU 2 /* emit vertex program upload */
227#define R300_CMD_PACKET3 3 /* emit a packet3 */
228#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
414ed537
DA		 229#define R300_CMD_CP_DELAY 5
230#define R300_CMD_DMA_DISCARD 6
231#define R300_CMD_WAIT 7
bc5f4523
DA		 232# define R300_WAIT_2D 0x1
233# define R300_WAIT_3D 0x2
0c76be35
DA		 234/* these two defines are DOING IT WRONG - however
235 * we have userspace which relies on using these.
236 * The wait interface is backwards compat new
237 * code should use the NEW_WAIT defines below
238 * THESE ARE NOT BIT FIELDS
239 */
bc5f4523
DA		 240# define R300_WAIT_2D_CLEAN 0x3
241# define R300_WAIT_3D_CLEAN 0x4
0c76be35
DA		 242
243# define R300_NEW_WAIT_2D_3D 0x3
244# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
245# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
246# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
247
ee4621f0 248#define R300_CMD_SCRATCH 8
c0beb2a7 249#define R300_CMD_R500FP 9
414ed537
DA		 250
251typedef union {
252 unsigned int u;
253 struct {
254 unsigned char cmd_type, pad0, pad1, pad2;
255 } header;
256 struct {
257 unsigned char cmd_type, count, reglo, reghi;
258 } packet0;
259 struct {
260 unsigned char cmd_type, count, adrlo, adrhi;
261 } vpu;
262 struct {
263 unsigned char cmd_type, packet, pad0, pad1;
264 } packet3;
265 struct {
266 unsigned char cmd_type, packet;
b5e89ed5 267 unsigned short count; /* amount of packet2 to emit */
414ed537
DA		 268 } delay;
269 struct {
270 unsigned char cmd_type, buf_idx, pad0, pad1;
271 } dma;
272 struct {
b5e89ed5 273 unsigned char cmd_type, flags, pad0, pad1;
414ed537 274 } wait;
ee4621f0
DA		 275 struct {
276 unsigned char cmd_type, reg, n_bufs, flags;
277 } scratch;
c0beb2a7
DA		 278 struct {
279 unsigned char cmd_type, count, adrlo, adrhi_flags;
280 } r500fp;
414ed537 281} drm_r300_cmd_header_t;
1da177e4
LT		 282
283#define RADEON_FRONT 0x1
284#define RADEON_BACK 0x2
285#define RADEON_DEPTH 0x4
286#define RADEON_STENCIL 0x8
287#define RADEON_CLEAR_FASTZ 0x80000000
288#define RADEON_USE_HIERZ 0x40000000
289#define RADEON_USE_COMP_ZBUF 0x20000000
290
c0beb2a7
DA		 291#define R500FP_CONSTANT_TYPE (1 << 1)
292#define R500FP_CONSTANT_CLAMP (1 << 2)
293
1da177e4
LT		 294/* Primitive types
295 */
296#define RADEON_POINTS 0x1
297#define RADEON_LINES 0x2
298#define RADEON_LINE_STRIP 0x3
299#define RADEON_TRIANGLES 0x4
300#define RADEON_TRIANGLE_FAN 0x5
301#define RADEON_TRIANGLE_STRIP 0x6
302
303/* Vertex/indirect buffer size
304 */
305#define RADEON_BUFFER_SIZE 65536
306
307/* Byte offsets for indirect buffer data
308 */
309#define RADEON_INDEX_PRIM_OFFSET 20
310
311#define RADEON_SCRATCH_REG_OFFSET 32
312
befb73c2
AD		 313#define R600_SCRATCH_REG_OFFSET 256
314
1da177e4
LT		 315#define RADEON_NR_SAREA_CLIPRECTS 12
316
317/* There are 2 heaps (local/GART). Each region within a heap is a
318 * minimum of 64k, and there are at most 64 of them per heap.
319 */
320#define RADEON_LOCAL_TEX_HEAP 0
321#define RADEON_GART_TEX_HEAP 1
322#define RADEON_NR_TEX_HEAPS 2
323#define RADEON_NR_TEX_REGIONS 64
324#define RADEON_LOG_TEX_GRANULARITY 16
325
326#define RADEON_MAX_TEXTURE_LEVELS 12
327#define RADEON_MAX_TEXTURE_UNITS 3
328
329#define RADEON_MAX_SURFACES 8
330
331/* Blits have strict offset rules. All blit offset must be aligned on
332 * a 1K-byte boundary.
333 */
334#define RADEON_OFFSET_SHIFT 10
335#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
336#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
337
b5e89ed5 338#endif /* __RADEON_SAREA_DEFINES__ */
1da177e4
LT		 339
340typedef struct {
341 unsigned int red;
342 unsigned int green;
343 unsigned int blue;
344 unsigned int alpha;
345} radeon_color_regs_t;
346
347typedef struct {
348 /* Context state */
b5e89ed5 349 unsigned int pp_misc; /* 0x1c14 */
1da177e4
LT		 350 unsigned int pp_fog_color;
351 unsigned int re_solid_color;
352 unsigned int rb3d_blendcntl;
353 unsigned int rb3d_depthoffset;
354 unsigned int rb3d_depthpitch;
355 unsigned int rb3d_zstencilcntl;
356
b5e89ed5 357 unsigned int pp_cntl; /* 0x1c38 */
1da177e4
LT		 358 unsigned int rb3d_cntl;
359 unsigned int rb3d_coloroffset;
360 unsigned int re_width_height;
361 unsigned int rb3d_colorpitch;
362 unsigned int se_cntl;
363
364 /* Vertex format state */
b5e89ed5 365 unsigned int se_coord_fmt; /* 0x1c50 */
1da177e4
LT		 366
367 /* Line state */
b5e89ed5 368 unsigned int re_line_pattern; /* 0x1cd0 */
1da177e4
LT		 369 unsigned int re_line_state;
370
b5e89ed5 371 unsigned int se_line_width; /* 0x1db8 */
1da177e4
LT		 372
373 /* Bumpmap state */
b5e89ed5 374 unsigned int pp_lum_matrix; /* 0x1d00 */
1da177e4 375
b5e89ed5 376 unsigned int pp_rot_matrix_0; /* 0x1d58 */
1da177e4
LT		 377 unsigned int pp_rot_matrix_1;
378
379 /* Mask state */
b5e89ed5 380 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
1da177e4
LT		 381 unsigned int rb3d_ropcntl;
382 unsigned int rb3d_planemask;
383
384 /* Viewport state */
b5e89ed5 385 unsigned int se_vport_xscale; /* 0x1d98 */
1da177e4
LT		 386 unsigned int se_vport_xoffset;
387 unsigned int se_vport_yscale;
388 unsigned int se_vport_yoffset;
389 unsigned int se_vport_zscale;
390 unsigned int se_vport_zoffset;
391
392 /* Setup state */
b5e89ed5 393 unsigned int se_cntl_status; /* 0x2140 */
1da177e4
LT		 394
395 /* Misc state */
b5e89ed5 396 unsigned int re_top_left; /* 0x26c0 */
1da177e4
LT		 397 unsigned int re_misc;
398} drm_radeon_context_regs_t;
399
400typedef struct {
401 /* Zbias state */
b5e89ed5 402 unsigned int se_zbias_factor; /* 0x1dac */
1da177e4
LT		 403 unsigned int se_zbias_constant;
404} drm_radeon_context2_regs_t;
405
1da177e4
LT		 406/* Setup registers for each texture unit
407 */
408typedef struct {
409 unsigned int pp_txfilter;
410 unsigned int pp_txformat;
411 unsigned int pp_txoffset;
412 unsigned int pp_txcblend;
413 unsigned int pp_txablend;
414 unsigned int pp_tfactor;
415 unsigned int pp_border_color;
416} drm_radeon_texture_regs_t;
417
418typedef struct {
419 unsigned int start;
420 unsigned int finish;
421 unsigned int prim:8;
422 unsigned int stateidx:8;
b5e89ed5
DA		 423 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
424 unsigned int vc_format; /* vertex format */
1da177e4
LT		 425} drm_radeon_prim_t;
426
1da177e4
LT		 427typedef struct {
428 drm_radeon_context_regs_t context;
429 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
430 drm_radeon_context2_regs_t context2;
431 unsigned int dirty;
432} drm_radeon_state_t;
433
1da177e4
LT		 434typedef struct {
435 /* The channel for communication of state information to the
436 * kernel on firing a vertex buffer with either of the
437 * obsoleted vertex/index ioctls.
438 */
439 drm_radeon_context_regs_t context_state;
440 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
441 unsigned int dirty;
442 unsigned int vertsize;
443 unsigned int vc_format;
444
445 /* The current cliprects, or a subset thereof.
446 */
c60ce623 447 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
1da177e4
LT		 448 unsigned int nbox;
449
450 /* Counters for client-side throttling of rendering clients.
451 */
452 unsigned int last_frame;
453 unsigned int last_dispatch;
454 unsigned int last_clear;
455
c60ce623 456 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
b5e89ed5 457 1];
1da177e4
LT		 458 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
459 int ctx_owner;
b5e89ed5
DA		 460 int pfState; /* number of 3d windows (0,1,2ormore) */
461 int pfCurrentPage; /* which buffer is being displayed? */
462 int crtc2_base; /* CRTC2 frame offset */
1da177e4
LT		 463 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
464} drm_radeon_sarea_t;
465
1da177e4
LT		 466/* WARNING: If you change any of these defines, make sure to change the
467 * defines in the Xserver file (xf86drmRadeon.h)
468 *
469 * KW: actually it's illegal to change any of this (backwards compatibility).
470 */
471
472/* Radeon specific ioctls
473 * The device specific ioctl range is 0x40 to 0x79.
474 */
b5e89ed5
DA		 475#define DRM_RADEON_CP_INIT 0x00
476#define DRM_RADEON_CP_START 0x01
1da177e4
LT		 477#define DRM_RADEON_CP_STOP 0x02
478#define DRM_RADEON_CP_RESET 0x03
479#define DRM_RADEON_CP_IDLE 0x04
b5e89ed5 480#define DRM_RADEON_RESET 0x05
1da177e4 481#define DRM_RADEON_FULLSCREEN 0x06
b5e89ed5
DA		 482#define DRM_RADEON_SWAP 0x07
483#define DRM_RADEON_CLEAR 0x08
1da177e4
LT		 484#define DRM_RADEON_VERTEX 0x09
485#define DRM_RADEON_INDICES 0x0A
486#define DRM_RADEON_NOT_USED
487#define DRM_RADEON_STIPPLE 0x0C
488#define DRM_RADEON_INDIRECT 0x0D
489#define DRM_RADEON_TEXTURE 0x0E
490#define DRM_RADEON_VERTEX2 0x0F
491#define DRM_RADEON_CMDBUF 0x10
492#define DRM_RADEON_GETPARAM 0x11
493#define DRM_RADEON_FLIP 0x12
494#define DRM_RADEON_ALLOC 0x13
495#define DRM_RADEON_FREE 0x14
496#define DRM_RADEON_INIT_HEAP 0x15
497#define DRM_RADEON_IRQ_EMIT 0x16
498#define DRM_RADEON_IRQ_WAIT 0x17
499#define DRM_RADEON_CP_RESUME 0x18
500#define DRM_RADEON_SETPARAM 0x19
501#define DRM_RADEON_SURF_ALLOC 0x1a
502#define DRM_RADEON_SURF_FREE 0x1b
771fe6b9
JG		 503/* KMS ioctl */
504#define DRM_RADEON_GEM_INFO 0x1c
505#define DRM_RADEON_GEM_CREATE 0x1d
506#define DRM_RADEON_GEM_MMAP 0x1e
507#define DRM_RADEON_GEM_PREAD 0x21
508#define DRM_RADEON_GEM_PWRITE 0x22
509#define DRM_RADEON_GEM_SET_DOMAIN 0x23
510#define DRM_RADEON_GEM_WAIT_IDLE 0x24
511#define DRM_RADEON_CS 0x26
512#define DRM_RADEON_INFO 0x27
e024e110
DA		 513#define DRM_RADEON_GEM_SET_TILING 0x28
514#define DRM_RADEON_GEM_GET_TILING 0x29
e3b2415e 515#define DRM_RADEON_GEM_BUSY 0x2a
721604a1 516#define DRM_RADEON_GEM_VA 0x2b
bda72d58 517#define DRM_RADEON_GEM_OP 0x2c
f72a113a 518#define DRM_RADEON_GEM_USERPTR 0x2d
1da177e4
LT		 519
520#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
521#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
522#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
523#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
524#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
525#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
526#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
527#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
528#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
529#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
530#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
531#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
532#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
533#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
534#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
535#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
536#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
537#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
538#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
539#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
540#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
541#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
542#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
543#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
544#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
545#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
546#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
771fe6b9
JG		 547/* KMS */
548#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
549#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
550#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
551#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
552#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
553#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
554#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
555#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
556#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
1b2f1489
DA		 557#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
558#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
e3b2415e 559#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
721604a1 560#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
bda72d58 561#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
f72a113a 562#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
1da177e4
LT		 563
564typedef struct drm_radeon_init {
565 enum {
b5e89ed5 566 RADEON_INIT_CP = 0x01,
1da177e4
LT		 567 RADEON_CLEANUP_CP = 0x02,
568 RADEON_INIT_R200_CP = 0x03,
befb73c2
AD		 569 RADEON_INIT_R300_CP = 0x04,
570 RADEON_INIT_R600_CP = 0x05
1da177e4
LT		 571 } func;
572 unsigned long sarea_priv_offset;
573 int is_pci;
574 int cp_mode;
575 int gart_size;
576 int ring_size;
577 int usec_timeout;
578
579 unsigned int fb_bpp;
580 unsigned int front_offset, front_pitch;
581 unsigned int back_offset, back_pitch;
582 unsigned int depth_bpp;
583 unsigned int depth_offset, depth_pitch;
584
585 unsigned long fb_offset;
586 unsigned long mmio_offset;
587 unsigned long ring_offset;
588 unsigned long ring_rptr_offset;
589 unsigned long buffers_offset;
590 unsigned long gart_textures_offset;
591} drm_radeon_init_t;
592
593typedef struct drm_radeon_cp_stop {
594 int flush;
595 int idle;
596} drm_radeon_cp_stop_t;
597
598typedef struct drm_radeon_fullscreen {
599 enum {
b5e89ed5 600 RADEON_INIT_FULLSCREEN = 0x01,
1da177e4
LT		 601 RADEON_CLEANUP_FULLSCREEN = 0x02
602 } func;
603} drm_radeon_fullscreen_t;
604
605#define CLEAR_X1 0
606#define CLEAR_Y1 1
607#define CLEAR_X2 2
608#define CLEAR_Y2 3
609#define CLEAR_DEPTH 4
610
611typedef union drm_radeon_clear_rect {
612 float f[5];
613 unsigned int ui[5];
614} drm_radeon_clear_rect_t;
615
616typedef struct drm_radeon_clear {
617 unsigned int flags;
618 unsigned int clear_color;
619 unsigned int clear_depth;
620 unsigned int color_mask;
b5e89ed5 621 unsigned int depth_mask; /* misnamed field: should be stencil */
1da177e4
LT		 622 drm_radeon_clear_rect_t __user *depth_boxes;
623} drm_radeon_clear_t;
624
625typedef struct drm_radeon_vertex {
626 int prim;
b5e89ed5
DA		 627 int idx; /* Index of vertex buffer */
628 int count; /* Number of vertices in buffer */
629 int discard; /* Client finished with buffer? */
1da177e4
LT		 630} drm_radeon_vertex_t;
631
632typedef struct drm_radeon_indices {
633 int prim;
634 int idx;
635 int start;
636 int end;
b5e89ed5 637 int discard; /* Client finished with buffer? */
1da177e4
LT		 638} drm_radeon_indices_t;
639
640/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
641 * - allows multiple primitives and state changes in a single ioctl
642 * - supports driver change to emit native primitives
643 */
644typedef struct drm_radeon_vertex2 {
b5e89ed5
DA		 645 int idx; /* Index of vertex buffer */
646 int discard; /* Client finished with buffer? */
1da177e4
LT		 647 int nr_states;
648 drm_radeon_state_t __user *state;
649 int nr_prims;
650 drm_radeon_prim_t __user *prim;
651} drm_radeon_vertex2_t;
652
653/* v1.3 - obsoletes drm_radeon_vertex2
25985edc 654 * - allows arbitrarily large cliprect list
1da177e4
LT		 655 * - allows updating of tcl packet, vector and scalar state
656 * - allows memory-efficient description of state updates
b5e89ed5 657 * - allows state to be emitted without a primitive
1da177e4
LT		 658 * (for clears, ctx switches)
659 * - allows more than one dma buffer to be referenced per ioctl
660 * - supports tcl driver
661 * - may be extended in future versions with new cmd types, packets
662 */
663typedef struct drm_radeon_cmd_buffer {
664 int bufsz;
665 char __user *buf;
666 int nbox;
c60ce623 667 struct drm_clip_rect __user *boxes;
1da177e4
LT		 668} drm_radeon_cmd_buffer_t;
669
670typedef struct drm_radeon_tex_image {
b5e89ed5 671 unsigned int x, y; /* Blit coordinates */
1da177e4
LT		 672 unsigned int width, height;
673 const void __user *data;
674} drm_radeon_tex_image_t;
675
676typedef struct drm_radeon_texture {
677 unsigned int offset;
678 int pitch;
679 int format;
b5e89ed5 680 int width; /* Texture image coordinates */
1da177e4
LT		 681 int height;
682 drm_radeon_tex_image_t __user *image;
683} drm_radeon_texture_t;
684
685typedef struct drm_radeon_stipple {
686 unsigned int __user *mask;
687} drm_radeon_stipple_t;
688
689typedef struct drm_radeon_indirect {
690 int idx;
691 int start;
692 int end;
693 int discard;
694} drm_radeon_indirect_t;
695
d985c108
DA		 696/* enum for card type parameters */
697#define RADEON_CARD_PCI 0
698#define RADEON_CARD_AGP 1
699#define RADEON_CARD_PCIE 2
700
1da177e4 701/* 1.3: An ioctl to get parameters that aren't available to the 3d
b5e89ed5 702 * client any other way.
1da177e4 703 */
b5e89ed5 704#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
1da177e4
LT		 705#define RADEON_PARAM_LAST_FRAME 2
706#define RADEON_PARAM_LAST_DISPATCH 3
707#define RADEON_PARAM_LAST_CLEAR 4
708/* Added with DRM version 1.6. */
709#define RADEON_PARAM_IRQ_NR 5
b5e89ed5 710#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
1da177e4 711/* Added with DRM version 1.8. */
b5e89ed5 712#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
1da177e4
LT		 713#define RADEON_PARAM_STATUS_HANDLE 8
714#define RADEON_PARAM_SAREA_HANDLE 9
715#define RADEON_PARAM_GART_TEX_HANDLE 10
716#define RADEON_PARAM_SCRATCH_OFFSET 11
d985c108 717#define RADEON_PARAM_CARD_TYPE 12
ddbee333 718#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
3d5e2c13 719#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
5b92c404 720#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
771fe6b9 721#define RADEON_PARAM_DEVICE_ID 16
f779b3e5 722#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
1da177e4
LT		 723
724typedef struct drm_radeon_getparam {
725 int param;
726 void __user *value;
727} drm_radeon_getparam_t;
728
729/* 1.6: Set up a memory manager for regions of shared memory:
730 */
731#define RADEON_MEM_REGION_GART 1
732#define RADEON_MEM_REGION_FB 2
733
734typedef struct drm_radeon_mem_alloc {
735 int region;
736 int alignment;
737 int size;
738 int __user *region_offset; /* offset from start of fb or GART */
739} drm_radeon_mem_alloc_t;
740
741typedef struct drm_radeon_mem_free {
742 int region;
743 int region_offset;
744} drm_radeon_mem_free_t;
745
746typedef struct drm_radeon_mem_init_heap {
747 int region;
748 int size;
b5e89ed5 749 int start;
1da177e4
LT		 750} drm_radeon_mem_init_heap_t;
751
1da177e4
LT		 752/* 1.6: Userspace can request & wait on irq's:
753 */
754typedef struct drm_radeon_irq_emit {
755 int __user *irq_seq;
756} drm_radeon_irq_emit_t;
757
758typedef struct drm_radeon_irq_wait {
759 int irq_seq;
760} drm_radeon_irq_wait_t;
761
1da177e4
LT		 762/* 1.10: Clients tell the DRM where they think the framebuffer is located in
763 * the card's address space, via a new generic ioctl to set parameters
764 */
765
766typedef struct drm_radeon_setparam {
767 unsigned int param;
1d7f83d5 768 __s64 value;
1da177e4
LT		 769} drm_radeon_setparam_t;
770
771#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
772#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
b5e89ed5 773#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
d5ea702f 774#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
f2b04cd2 775#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
ddbee333 776#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
1da177e4
LT		 777/* 1.14: Clients can allocate/free a surface
778 */
779typedef struct drm_radeon_surface_alloc {
780 unsigned int address;
781 unsigned int size;
782 unsigned int flags;
783} drm_radeon_surface_alloc_t;
784
785typedef struct drm_radeon_surface_free {
786 unsigned int address;
787} drm_radeon_surface_free_t;
788
bc5f4523
DA		 789#define DRM_RADEON_VBLANK_CRTC1 1
790#define DRM_RADEON_VBLANK_CRTC2 2
ddbee333 791
771fe6b9
JG		 792/*
793 * Kernel modesetting world below.
794 */
795#define RADEON_GEM_DOMAIN_CPU 0x1
796#define RADEON_GEM_DOMAIN_GTT 0x2
797#define RADEON_GEM_DOMAIN_VRAM 0x4
798
799struct drm_radeon_gem_info {
31b4dfe2
MR		 800 __u64 gart_size;
801 __u64 vram_size;
802 __u64 vram_visible;
771fe6b9
JG		 803};
804
77497f27
MD		 805#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
806#define RADEON_GEM_GTT_UC (1 << 1)
807#define RADEON_GEM_GTT_WC (1 << 2)
c8584039
MD		 808/* BO is expected to be accessed by the CPU */
809#define RADEON_GEM_CPU_ACCESS (1 << 3)
f266f04d
AD		 810/* CPU access is not expected to work for this BO */
811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
771fe6b9
JG		 812
813struct drm_radeon_gem_create {
31b4dfe2
MR		 814 __u64 size;
815 __u64 alignment;
816 __u32 handle;
817 __u32 initial_domain;
818 __u32 flags;
771fe6b9
JG		 819};
820
f72a113a
CK		 821/*
822 * This is not a reliable API and you should expect it to fail for any
823 * number of reasons and have fallback path that do not use userptr to
824 * perform any operation.
825 */
826#define RADEON_GEM_USERPTR_READONLY (1 << 0)
ddd00e33 827#define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
2a84a447 828#define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
341cb9e4 829#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
f72a113a
CK		 830
831struct drm_radeon_gem_userptr {
31b4dfe2
MR		 832 __u64 addr;
833 __u64 size;
834 __u32 flags;
835 __u32 handle;
f72a113a
CK		 836};
837
285484e2
JG		 838#define RADEON_TILING_MACRO 0x1
839#define RADEON_TILING_MICRO 0x2
840#define RADEON_TILING_SWAP_16BIT 0x4
841#define RADEON_TILING_SWAP_32BIT 0x8
842/* this object requires a surface when mapped - i.e. front buffer */
843#define RADEON_TILING_SURFACE 0x10
844#define RADEON_TILING_MICRO_SQUARE 0x20
845#define RADEON_TILING_EG_BANKW_SHIFT 8
846#define RADEON_TILING_EG_BANKW_MASK 0xf
847#define RADEON_TILING_EG_BANKH_SHIFT 12
848#define RADEON_TILING_EG_BANKH_MASK 0xf
849#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
850#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
851#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
852#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
853#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
854#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
e024e110
DA		 855
856struct drm_radeon_gem_set_tiling {
31b4dfe2
MR		 857 __u32 handle;
858 __u32 tiling_flags;
859 __u32 pitch;
e024e110
DA		 860};
861
862struct drm_radeon_gem_get_tiling {
31b4dfe2
MR		 863 __u32 handle;
864 __u32 tiling_flags;
865 __u32 pitch;
e024e110
DA		 866};
867
771fe6b9 868struct drm_radeon_gem_mmap {
31b4dfe2
MR		 869 __u32 handle;
870 __u32 pad;
871 __u64 offset;
872 __u64 size;
873 __u64 addr_ptr;
771fe6b9
JG		 874};
875
876struct drm_radeon_gem_set_domain {
31b4dfe2
MR		 877 __u32 handle;
878 __u32 read_domains;
879 __u32 write_domain;
771fe6b9
JG		 880};
881
882struct drm_radeon_gem_wait_idle {
31b4dfe2
MR		 883 __u32 handle;
884 __u32 pad;
771fe6b9
JG		 885};
886
887struct drm_radeon_gem_busy {
31b4dfe2
MR		 888 __u32 handle;
889 __u32 domain;
771fe6b9
JG		 890};
891
892struct drm_radeon_gem_pread {
893 /** Handle for the object being read. */
31b4dfe2
MR		 894 __u32 handle;
895 __u32 pad;
771fe6b9 896 /** Offset into the object to read from */
31b4dfe2 897 __u64 offset;
771fe6b9 898 /** Length of data to read */
31b4dfe2 899 __u64 size;
771fe6b9
JG		 900 /** Pointer to write the data into. */
901 /* void *, but pointers are not 32/64 compatible */
31b4dfe2 902 __u64 data_ptr;
771fe6b9
JG		 903};
904
905struct drm_radeon_gem_pwrite {
906 /** Handle for the object being written to. */
31b4dfe2
MR		 907 __u32 handle;
908 __u32 pad;
771fe6b9 909 /** Offset into the object to write to */
31b4dfe2 910 __u64 offset;
771fe6b9 911 /** Length of data to write */
31b4dfe2 912 __u64 size;
771fe6b9
JG		 913 /** Pointer to read the data from. */
914 /* void *, but pointers are not 32/64 compatible */
31b4dfe2 915 __u64 data_ptr;
771fe6b9
JG		 916};
917
bda72d58
MO		 918/* Sets or returns a value associated with a buffer. */
919struct drm_radeon_gem_op {
31b4dfe2
MR		 920 __u32 handle; /* buffer */
921 __u32 op; /* RADEON_GEM_OP_* */
922 __u64 value; /* input or return value */
bda72d58
MO		 923};
924
925#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
926#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
927
721604a1
JG		 928#define RADEON_VA_MAP 1
929#define RADEON_VA_UNMAP 2
930
931#define RADEON_VA_RESULT_OK 0
932#define RADEON_VA_RESULT_ERROR 1
933#define RADEON_VA_RESULT_VA_EXIST 2
934
935#define RADEON_VM_PAGE_VALID (1 << 0)
936#define RADEON_VM_PAGE_READABLE (1 << 1)
937#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
938#define RADEON_VM_PAGE_SYSTEM (1 << 3)
939#define RADEON_VM_PAGE_SNOOPED (1 << 4)
940
941struct drm_radeon_gem_va {
31b4dfe2
MR		 942 __u32 handle;
943 __u32 operation;
944 __u32 vm_id;
945 __u32 flags;
946 __u64 offset;
721604a1
JG		 947};
948
771fe6b9
JG		 949#define RADEON_CHUNK_ID_RELOCS 0x01
950#define RADEON_CHUNK_ID_IB 0x02
e70f224c 951#define RADEON_CHUNK_ID_FLAGS 0x03
dfcf5f36 952#define RADEON_CHUNK_ID_CONST_IB 0x04
e70f224c
MO		 953
954/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
955#define RADEON_CS_KEEP_TILING_FLAGS 0x01
721604a1 956#define RADEON_CS_USE_VM 0x02
57f57083 957#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */
721604a1
JG		 958/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
959#define RADEON_CS_RING_GFX 0
960#define RADEON_CS_RING_COMPUTE 1
278a334c 961#define RADEON_CS_RING_DMA 2
f2ba57b5 962#define RADEON_CS_RING_UVD 3
d93f7937 963#define RADEON_CS_RING_VCE 4
721604a1
JG		 964/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
965/* 0 = normal, + = higher priority, - = lower priority */
771fe6b9
JG		 966
967struct drm_radeon_cs_chunk {
31b4dfe2
MR		 968 __u32 chunk_id;
969 __u32 length_dw;
970 __u64 chunk_data;
771fe6b9
JG		 971};
972
93504fce 973/* drm_radeon_cs_reloc.flags */
701e1e78 974#define RADEON_RELOC_PRIO_MASK (0xf << 0)
93504fce 975
771fe6b9 976struct drm_radeon_cs_reloc {
31b4dfe2
MR		 977 __u32 handle;
978 __u32 read_domains;
979 __u32 write_domain;
980 __u32 flags;
771fe6b9
JG		 981};
982
983struct drm_radeon_cs {
31b4dfe2
MR		 984 __u32 num_chunks;
985 __u32 cs_id;
986 /* this points to __u64 * which point to cs chunks */
987 __u64 chunks;
771fe6b9 988 /* updates to the limits after this CS ioctl */
31b4dfe2
MR		 989 __u64 gart_limit;
990 __u64 vram_limit;
771fe6b9
JG		 991};
992
993#define RADEON_INFO_DEVICE_ID 0x00
994#define RADEON_INFO_NUM_GB_PIPES 0x01
f779b3e5 995#define RADEON_INFO_NUM_Z_PIPES 0x02
733289c2 996#define RADEON_INFO_ACCEL_WORKING 0x03
bc35afdb 997#define RADEON_INFO_CRTC_FROM_ID 0x04
148a03bc 998#define RADEON_INFO_ACCEL_WORKING2 0x05
e7aeeba6 999#define RADEON_INFO_TILING_CONFIG 0x06
ab9e1f59 1000#define RADEON_INFO_WANT_HYPERZ 0x07
9eba4a93 1001#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
58bbf018 1002#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
486af189 1003#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
6565945b 1004#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
8aeb96f8 1005#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
e55b9422 1006#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
721604a1
JG		 1007/* virtual address start, va < start are reserved by the kernel */
1008#define RADEON_INFO_VA_START 0x0e
1009/* maximum size of ib using the virtual memory cs */
1010#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
609c1e15
TS		 1011/* max pipes - needed for compute shaders */
1012#define RADEON_INFO_MAX_PIPES 0x10
6759a0a7
MO		 1013/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
1014#define RADEON_INFO_TIMESTAMP 0x11
2e1a7674
AD		 1015/* max shader engines (SE) - needed for geometry shaders, etc. */
1016#define RADEON_INFO_MAX_SE 0x12
1017/* max SH per SE */
1018#define RADEON_INFO_MAX_SH_PER_SE 0x13
a0a53aa8
SL		 1019/* fast fb access is enabled */
1020#define RADEON_INFO_FASTFB_WORKING 0x14
902aaef6
CK		 1021/* query if a RADEON_CS_RING_* submission is supported */
1022#define RADEON_INFO_RING_WORKING 0x15
64d7b8be
JG		 1023/* SI tile mode array */
1024#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
e5b9e750
TS		 1025/* query if CP DMA is supported on the compute ring */
1026#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
32f79a8a
MD		 1027/* CIK macrotile mode array */
1028#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
439a1cff
MO		 1029/* query the number of render backends */
1030#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
f5f1f897
AD		 1031/* max engine clock - needed for OpenCL */
1032#define RADEON_INFO_MAX_SCLK 0x1a
98ccc291
CK		 1033/* version of VCE firmware */
1034#define RADEON_INFO_VCE_FW_VERSION 0x1b
1035/* version of VCE feedback */
1036#define RADEON_INFO_VCE_FB_VERSION 0x1c
67e8e3f9
MO		 1037#define RADEON_INFO_NUM_BYTES_MOVED 0x1d
1038#define RADEON_INFO_VRAM_USAGE 0x1e
1039#define RADEON_INFO_GTT_USAGE 0x1f
65fcf668 1040#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
d6d2a188 1041#define RADEON_INFO_CURRENT_GPU_TEMP 0x21
5c363a86
AD		 1042#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
1043#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
4535cb9c 1044#define RADEON_INFO_READ_REG 0x24
3bc980bf 1045#define RADEON_INFO_VA_UNMAP_WORKING 0x25
099bfbfc 1046#define RADEON_INFO_GPU_RESET_COUNTER 0x26
771fe6b9
JG		 1047
1048struct drm_radeon_info {
31b4dfe2
MR		 1049 __u32 request;
1050 __u32 pad;
1051 __u64 value;
771fe6b9
JG		 1052};
1053
64d7b8be
JG		 1054/* Those correspond to the tile index to use, this is to explicitly state
1055 * the API that is implicitly defined by the tile mode array.
1056 */
1057#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
1058#define SI_TILE_MODE_COLOR_1D 13
1059#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
1060#define SI_TILE_MODE_COLOR_2D_8BPP 14
1061#define SI_TILE_MODE_COLOR_2D_16BPP 15
1062#define SI_TILE_MODE_COLOR_2D_32BPP 16
1063#define SI_TILE_MODE_COLOR_2D_64BPP 17
1064#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
1065#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
1066#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
1067#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
1068#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
1069#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
1070#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
1071
42baf21d
MD		 1072#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
1073
6db26a94
EV		 1074#if defined(__cplusplus)
1075}
1076#endif
1077
1da177e4 1078#endif
Linux kernel - Deliverables
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