[deliverable/linux.git] / include / uapi / drm / tegra_drm.h

/*
 * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _UAPI_TEGRA_DRM_H_
#define _UAPI_TEGRA_DRM_H_

#include <drm/drm.h>

#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)

struct drm_tegra_gem_create {
	__u64 size;
	__u32 flags;
	__u32 handle;
};

struct drm_tegra_gem_mmap {
	__u32 handle;
	__u32 pad;
	__u64 offset;
};

struct drm_tegra_syncpt_read {
	__u32 id;
	__u32 value;
};

struct drm_tegra_syncpt_incr {
	__u32 id;
	__u32 pad;
};

struct drm_tegra_syncpt_wait {
	__u32 id;
	__u32 thresh;
	__u32 timeout;
	__u32 value;
};

#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)

struct drm_tegra_open_channel {
	__u32 client;
	__u32 pad;
	__u64 context;
};

struct drm_tegra_close_channel {
	__u64 context;
};

struct drm_tegra_get_syncpt {
	__u64 context;
	__u32 index;
	__u32 id;
};

struct drm_tegra_get_syncpt_base {
	__u64 context;
	__u32 syncpt;
	__u32 id;
};

struct drm_tegra_syncpt {
	__u32 id;
	__u32 incrs;
};

struct drm_tegra_cmdbuf {
	__u32 handle;
	__u32 offset;
	__u32 words;
	__u32 pad;
};

struct drm_tegra_reloc {
	struct {
		__u32 handle;
		__u32 offset;
	} cmdbuf;
	struct {
		__u32 handle;
		__u32 offset;
	} target;
	__u32 shift;
	__u32 pad;
};

struct drm_tegra_waitchk {
	__u32 handle;
	__u32 offset;
	__u32 syncpt;
	__u32 thresh;
};

struct drm_tegra_submit {
	__u64 context;
	__u32 num_syncpts;
	__u32 num_cmdbufs;
	__u32 num_relocs;
	__u32 num_waitchks;
	__u32 waitchk_mask;
	__u32 timeout;
	__u64 syncpts;
	__u64 cmdbufs;
	__u64 relocs;
	__u64 waitchks;
	__u32 fence;		/* Return value */

	__u32 reserved[5];	/* future expansion */
};

#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2

struct drm_tegra_gem_set_tiling {
	/* input */
	__u32 handle;
	__u32 mode;
	__u32 value;
	__u32 pad;
};

struct drm_tegra_gem_get_tiling {
	/* input */
	__u32 handle;
	/* output */
	__u32 mode;
	__u32 value;
	__u32 pad;
};

#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)

struct drm_tegra_gem_set_flags {
	/* input */
	__u32 handle;
	/* output */
	__u32 flags;
};

struct drm_tegra_gem_get_flags {
	/* input */
	__u32 handle;
	/* output */
	__u32 flags;
};

#define DRM_TEGRA_GEM_CREATE		0x00
#define DRM_TEGRA_GEM_MMAP		0x01
#define DRM_TEGRA_SYNCPT_READ		0x02
#define DRM_TEGRA_SYNCPT_INCR		0x03
#define DRM_TEGRA_SYNCPT_WAIT		0x04
#define DRM_TEGRA_OPEN_CHANNEL		0x05
#define DRM_TEGRA_CLOSE_CHANNEL		0x06
#define DRM_TEGRA_GET_SYNCPT		0x07
#define DRM_TEGRA_SUBMIT		0x08
#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
#define DRM_TEGRA_GEM_SET_TILING	0x0a
#define DRM_TEGRA_GEM_GET_TILING	0x0b
#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
#define DRM_TEGRA_GEM_GET_FLAGS		0x0d

#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)

#endif
Commit	Line	Data
d43f81cb TB	1	/*
	2	* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
	3	*
248141db TR	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
d43f81cb	10	*
248141db TR	11	* The above copyright notice and this permission notice shall be included in
248141db TR	12	* all copies or substantial portions of the Software.
d43f81cb	13	*
248141db TR	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
d43f81cb TB	21	*/
	22
	23	#ifndef _UAPI_TEGRA_DRM_H_
	24	#define _UAPI_TEGRA_DRM_H_
	25
a191e48d EG	26	#include <drm/drm.h>
a191e48d EG	27
db7fbdfd TR	28	#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
db7fbdfd TR	29	#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
773af77f	30
d43f81cb TB	31	struct drm_tegra_gem_create {
	32	__u64 size;
	33	__u32 flags;
	34	__u32 handle;
	35	};
	36
	37	struct drm_tegra_gem_mmap {
	38	__u32 handle;
bdf76507 SP	39	__u32 pad;
bdf76507 SP	40	__u64 offset;
d43f81cb TB	41	};
	42
	43	struct drm_tegra_syncpt_read {
	44	__u32 id;
	45	__u32 value;
	46	};
	47
	48	struct drm_tegra_syncpt_incr {
	49	__u32 id;
	50	__u32 pad;
	51	};
	52
	53	struct drm_tegra_syncpt_wait {
	54	__u32 id;
	55	__u32 thresh;
	56	__u32 timeout;
	57	__u32 value;
	58	};
	59
	60	#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
	61
	62	struct drm_tegra_open_channel {
	63	__u32 client;
	64	__u32 pad;
	65	__u64 context;
	66	};
	67
	68	struct drm_tegra_close_channel {
	69	__u64 context;
	70	};
	71
	72	struct drm_tegra_get_syncpt {
	73	__u64 context;
	74	__u32 index;
	75	__u32 id;
	76	};
	77
c54a169b AM	78	struct drm_tegra_get_syncpt_base {
	79	__u64 context;
	80	__u32 syncpt;
	81	__u32 id;
	82	};
	83
d43f81cb TB	84	struct drm_tegra_syncpt {
	85	__u32 id;
	86	__u32 incrs;
	87	};
	88
	89	struct drm_tegra_cmdbuf {
	90	__u32 handle;
	91	__u32 offset;
	92	__u32 words;
	93	__u32 pad;
	94	};
	95
	96	struct drm_tegra_reloc {
	97	struct {
	98	__u32 handle;
	99	__u32 offset;
	100	} cmdbuf;
	101	struct {
	102	__u32 handle;
	103	__u32 offset;
	104	} target;
	105	__u32 shift;
	106	__u32 pad;
	107	};
	108
	109	struct drm_tegra_waitchk {
	110	__u32 handle;
	111	__u32 offset;
	112	__u32 syncpt;
	113	__u32 thresh;
	114	};
	115
	116	struct drm_tegra_submit {
	117	__u64 context;
	118	__u32 num_syncpts;
	119	__u32 num_cmdbufs;
	120	__u32 num_relocs;
	121	__u32 num_waitchks;
	122	__u32 waitchk_mask;
	123	__u32 timeout;
d43f81cb TB	124	__u64 syncpts;
	125	__u64 cmdbufs;
	126	__u64 relocs;
	127	__u64 waitchks;
	128	__u32 fence; /* Return value */
	129
	130	__u32 reserved[5]; /* future expansion */
	131	};
	132
7678d71f TR	133	#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
	134	#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
	135	#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
	136
	137	struct drm_tegra_gem_set_tiling {
	138	/* input */
	139	__u32 handle;
	140	__u32 mode;
	141	__u32 value;
	142	__u32 pad;
	143	};
	144
	145	struct drm_tegra_gem_get_tiling {
	146	/* input */
	147	__u32 handle;
	148	/* output */
	149	__u32 mode;
	150	__u32 value;
	151	__u32 pad;
	152	};
	153
7b129087 TR	154	#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
	155	#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
	156
	157	struct drm_tegra_gem_set_flags {
	158	/* input */
	159	__u32 handle;
	160	/* output */
	161	__u32 flags;
	162	};
	163
	164	struct drm_tegra_gem_get_flags {
	165	/* input */
	166	__u32 handle;
	167	/* output */
	168	__u32 flags;
	169	};
	170
c54a169b AM	171	#define DRM_TEGRA_GEM_CREATE 0x00
	172	#define DRM_TEGRA_GEM_MMAP 0x01
	173	#define DRM_TEGRA_SYNCPT_READ 0x02
	174	#define DRM_TEGRA_SYNCPT_INCR 0x03
	175	#define DRM_TEGRA_SYNCPT_WAIT 0x04
	176	#define DRM_TEGRA_OPEN_CHANNEL 0x05
	177	#define DRM_TEGRA_CLOSE_CHANNEL 0x06
	178	#define DRM_TEGRA_GET_SYNCPT 0x07
	179	#define DRM_TEGRA_SUBMIT 0x08
	180	#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
7678d71f TR	181	#define DRM_TEGRA_GEM_SET_TILING 0x0a
7678d71f TR	182	#define DRM_TEGRA_GEM_GET_TILING 0x0b
7b129087 TR	183	#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
7b129087 TR	184	#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
d43f81cb TB	185
	186	#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
	187	#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
	188	#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
	189	#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
	190	#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
	191	#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
	192	#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
	193	#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
	194	#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
c54a169b	195	#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
7678d71f TR	196	#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
7678d71f TR	197	#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
7b129087 TR	198	#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
7b129087 TR	199	#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
d43f81cb TB	200
d43f81cb TB	201	#endif