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1 | /* |
2 | * linux/drivers/char/serial_core.h | |
3 | * | |
4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef _UAPILINUX_SERIAL_CORE_H | |
21 | #define _UAPILINUX_SERIAL_CORE_H | |
22 | ||
23 | #include <linux/serial.h> | |
24 | ||
25 | /* | |
26 | * The type definitions. These are from Ted Ts'o's serial.h | |
27 | */ | |
28 | #define PORT_UNKNOWN 0 | |
29 | #define PORT_8250 1 | |
30 | #define PORT_16450 2 | |
31 | #define PORT_16550 3 | |
32 | #define PORT_16550A 4 | |
33 | #define PORT_CIRRUS 5 | |
34 | #define PORT_16650 6 | |
35 | #define PORT_16650V2 7 | |
36 | #define PORT_16750 8 | |
37 | #define PORT_STARTECH 9 | |
38 | #define PORT_16C950 10 | |
39 | #define PORT_16654 11 | |
40 | #define PORT_16850 12 | |
41 | #define PORT_RSA 13 | |
42 | #define PORT_NS16550A 14 | |
43 | #define PORT_XSCALE 15 | |
44 | #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ | |
45 | #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ | |
46 | #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ | |
47 | #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ | |
48 | #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ | |
49 | #define PORT_XR17D15X 21 /* Exar XR17D15x UART */ | |
50 | #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */ | |
51 | #define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */ | |
52 | #define PORT_MAX_8250 23 /* max port ID */ | |
53 | ||
54 | /* | |
55 | * ARM specific type numbers. These are not currently guaranteed | |
56 | * to be implemented, and will change in the future. These are | |
57 | * separate so any additions to the old serial.c that occur before | |
58 | * we are merged can be easily merged here. | |
59 | */ | |
60 | #define PORT_PXA 31 | |
61 | #define PORT_AMBA 32 | |
62 | #define PORT_CLPS711X 33 | |
63 | #define PORT_SA1100 34 | |
64 | #define PORT_UART00 35 | |
65 | #define PORT_21285 37 | |
66 | ||
67 | /* Sparc type numbers. */ | |
68 | #define PORT_SUNZILOG 38 | |
69 | #define PORT_SUNSAB 39 | |
70 | ||
71 | /* DEC */ | |
72 | #define PORT_DZ 46 | |
73 | #define PORT_ZS 47 | |
74 | ||
75 | /* Parisc type numbers. */ | |
76 | #define PORT_MUX 48 | |
77 | ||
78 | /* Atmel AT91 / AT32 SoC */ | |
79 | #define PORT_ATMEL 49 | |
80 | ||
81 | /* Macintosh Zilog type numbers */ | |
82 | #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ | |
83 | #define PORT_PMAC_ZILOG 51 | |
84 | ||
85 | /* SH-SCI */ | |
86 | #define PORT_SCI 52 | |
87 | #define PORT_SCIF 53 | |
88 | #define PORT_IRDA 54 | |
89 | ||
90 | /* Samsung S3C2410 SoC and derivatives thereof */ | |
91 | #define PORT_S3C2410 55 | |
92 | ||
93 | /* SGI IP22 aka Indy / Challenge S / Indigo 2 */ | |
94 | #define PORT_IP22ZILOG 56 | |
95 | ||
96 | /* Sharp LH7a40x -- an ARM9 SoC series */ | |
97 | #define PORT_LH7A40X 57 | |
98 | ||
99 | /* PPC CPM type number */ | |
100 | #define PORT_CPM 58 | |
101 | ||
102 | /* MPC52xx (and MPC512x) type numbers */ | |
103 | #define PORT_MPC52xx 59 | |
104 | ||
105 | /* IBM icom */ | |
106 | #define PORT_ICOM 60 | |
107 | ||
108 | /* Samsung S3C2440 SoC */ | |
109 | #define PORT_S3C2440 61 | |
110 | ||
111 | /* Motorola i.MX SoC */ | |
112 | #define PORT_IMX 62 | |
113 | ||
114 | /* Marvell MPSC */ | |
115 | #define PORT_MPSC 63 | |
116 | ||
117 | /* TXX9 type number */ | |
118 | #define PORT_TXX9 64 | |
119 | ||
120 | /* NEC VR4100 series SIU/DSIU */ | |
121 | #define PORT_VR41XX_SIU 65 | |
122 | #define PORT_VR41XX_DSIU 66 | |
123 | ||
124 | /* Samsung S3C2400 SoC */ | |
125 | #define PORT_S3C2400 67 | |
126 | ||
127 | /* M32R SIO */ | |
128 | #define PORT_M32R_SIO 68 | |
129 | ||
130 | /*Digi jsm */ | |
131 | #define PORT_JSM 69 | |
132 | ||
133 | #define PORT_PNX8XXX 70 | |
134 | ||
135 | /* Hilscher netx */ | |
136 | #define PORT_NETX 71 | |
137 | ||
138 | /* SUN4V Hypervisor Console */ | |
139 | #define PORT_SUNHV 72 | |
140 | ||
141 | #define PORT_S3C2412 73 | |
142 | ||
143 | /* Xilinx uartlite */ | |
144 | #define PORT_UARTLITE 74 | |
145 | ||
146 | /* Blackfin bf5xx */ | |
147 | #define PORT_BFIN 75 | |
148 | ||
149 | /* Micrel KS8695 */ | |
150 | #define PORT_KS8695 76 | |
151 | ||
152 | /* Broadcom SB1250, etc. SOC */ | |
153 | #define PORT_SB1250_DUART 77 | |
154 | ||
155 | /* Freescale ColdFire */ | |
156 | #define PORT_MCF 78 | |
157 | ||
158 | /* Blackfin SPORT */ | |
159 | #define PORT_BFIN_SPORT 79 | |
160 | ||
161 | /* MN10300 on-chip UART numbers */ | |
162 | #define PORT_MN10300 80 | |
163 | #define PORT_MN10300_CTS 81 | |
164 | ||
165 | #define PORT_SC26XX 82 | |
166 | ||
167 | /* SH-SCI */ | |
168 | #define PORT_SCIFA 83 | |
169 | ||
170 | #define PORT_S3C6400 84 | |
171 | ||
172 | /* NWPSERIAL */ | |
173 | #define PORT_NWPSERIAL 85 | |
174 | ||
175 | /* MAX3100 */ | |
176 | #define PORT_MAX3100 86 | |
177 | ||
178 | /* Timberdale UART */ | |
179 | #define PORT_TIMBUART 87 | |
180 | ||
181 | /* Qualcomm MSM SoCs */ | |
182 | #define PORT_MSM 88 | |
183 | ||
184 | /* BCM63xx family SoCs */ | |
185 | #define PORT_BCM63XX 89 | |
186 | ||
187 | /* Aeroflex Gaisler GRLIB APBUART */ | |
188 | #define PORT_APBUART 90 | |
189 | ||
190 | /* Altera UARTs */ | |
191 | #define PORT_ALTERA_JTAGUART 91 | |
192 | #define PORT_ALTERA_UART 92 | |
193 | ||
194 | /* SH-SCI */ | |
195 | #define PORT_SCIFB 93 | |
196 | ||
197 | /* MAX310X */ | |
198 | #define PORT_MAX310X 94 | |
199 | ||
200 | /* High Speed UART for Medfield */ | |
201 | #define PORT_MFD 95 | |
202 | ||
203 | /* TI OMAP-UART */ | |
204 | #define PORT_OMAP 96 | |
205 | ||
206 | /* VIA VT8500 SoC */ | |
207 | #define PORT_VT8500 97 | |
208 | ||
209 | /* Xilinx PSS UART */ | |
210 | #define PORT_XUARTPS 98 | |
211 | ||
212 | /* Atheros AR933X SoC */ | |
213 | #define PORT_AR933X 99 | |
214 | ||
215 | /* Energy Micro efm32 SoC */ | |
216 | #define PORT_EFMUART 100 | |
217 | ||
2ac4ad2a VG |
218 | /* ARC (Synopsys) on-chip UART */ |
219 | #define PORT_ARC 101 | |
607ca46e DH |
220 | |
221 | #endif /* _UAPILINUX_SERIAL_CORE_H */ |