Commit | Line | Data |
---|---|---|
559d6701 | 1 | /* |
559d6701 TV |
2 | * Copyright (C) 2008 Nokia Corporation |
3 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a0b38cc4 TV |
18 | #ifndef __OMAP_OMAPDSS_H |
19 | #define __OMAP_OMAPDSS_H | |
559d6701 TV |
20 | |
21 | #include <linux/list.h> | |
22 | #include <linux/kobject.h> | |
23 | #include <linux/device.h> | |
348be69d | 24 | #include <linux/interrupt.h> |
559d6701 | 25 | |
6fcd485b TV |
26 | #include <video/videomode.h> |
27 | ||
559d6701 TV |
28 | #define DISPC_IRQ_FRAMEDONE (1 << 0) |
29 | #define DISPC_IRQ_VSYNC (1 << 1) | |
30 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) | |
31 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) | |
32 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) | |
33 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) | |
34 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) | |
35 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) | |
36 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) | |
37 | #define DISPC_IRQ_OCP_ERR (1 << 9) | |
38 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) | |
39 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) | |
40 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) | |
41 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) | |
42 | #define DISPC_IRQ_SYNC_LOST (1 << 14) | |
43 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) | |
44 | #define DISPC_IRQ_WAKEUP (1 << 16) | |
2a205f34 SS |
45 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
46 | #define DISPC_IRQ_VSYNC2 (1 << 18) | |
b8c095b4 AT |
47 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) |
48 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) | |
2a205f34 SS |
49 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
50 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | |
7f6f3c4b TV |
51 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) |
52 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) | |
53 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) | |
14d33d38 CM |
54 | #define DISPC_IRQ_SYNC_LOST3 (1 << 27) |
55 | #define DISPC_IRQ_VSYNC3 (1 << 28) | |
56 | #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) | |
57 | #define DISPC_IRQ_FRAMEDONE3 (1 << 30) | |
559d6701 TV |
58 | |
59 | struct omap_dss_device; | |
60 | struct omap_overlay_manager; | |
a97a9634 | 61 | struct dss_lcd_mgr_config; |
9c0b8420 RN |
62 | struct snd_aes_iec958; |
63 | struct snd_cea_861_aud_if; | |
559d6701 TV |
64 | |
65 | enum omap_display_type { | |
66 | OMAP_DISPLAY_TYPE_NONE = 0, | |
67 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, | |
68 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, | |
69 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, | |
70 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, | |
71 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, | |
b119601d | 72 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
559d6701 TV |
73 | }; |
74 | ||
75 | enum omap_plane { | |
76 | OMAP_DSS_GFX = 0, | |
77 | OMAP_DSS_VIDEO1 = 1, | |
b8c095b4 AT |
78 | OMAP_DSS_VIDEO2 = 2, |
79 | OMAP_DSS_VIDEO3 = 3, | |
66a0f9e4 | 80 | OMAP_DSS_WB = 4, |
559d6701 TV |
81 | }; |
82 | ||
83 | enum omap_channel { | |
84 | OMAP_DSS_CHANNEL_LCD = 0, | |
85 | OMAP_DSS_CHANNEL_DIGIT = 1, | |
8613b000 | 86 | OMAP_DSS_CHANNEL_LCD2 = 2, |
ff6331e2 | 87 | OMAP_DSS_CHANNEL_LCD3 = 3, |
559d6701 TV |
88 | }; |
89 | ||
90 | enum omap_color_mode { | |
91 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ | |
92 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ | |
93 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ | |
94 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ | |
95 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ | |
96 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ | |
97 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ | |
98 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ | |
99 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ | |
100 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ | |
101 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ | |
102 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ | |
103 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ | |
104 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ | |
f20e4220 AJ |
105 | OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ |
106 | OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ | |
107 | OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ | |
108 | OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ | |
109 | OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ | |
559d6701 TV |
110 | }; |
111 | ||
559d6701 TV |
112 | enum omap_dss_load_mode { |
113 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, | |
114 | OMAP_DSS_LOAD_CLUT_ONLY = 1, | |
115 | OMAP_DSS_LOAD_FRAME_ONLY = 2, | |
116 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, | |
117 | }; | |
118 | ||
119 | enum omap_dss_trans_key_type { | |
120 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, | |
121 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, | |
122 | }; | |
123 | ||
124 | enum omap_rfbi_te_mode { | |
125 | OMAP_DSS_RFBI_TE_MODE_1 = 1, | |
126 | OMAP_DSS_RFBI_TE_MODE_2 = 2, | |
127 | }; | |
128 | ||
a8d5e41c AT |
129 | enum omap_dss_signal_level { |
130 | OMAPDSS_SIG_ACTIVE_HIGH = 0, | |
131 | OMAPDSS_SIG_ACTIVE_LOW = 1, | |
132 | }; | |
133 | ||
134 | enum omap_dss_signal_edge { | |
135 | OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | |
136 | OMAPDSS_DRIVE_SIG_RISING_EDGE, | |
137 | OMAPDSS_DRIVE_SIG_FALLING_EDGE, | |
138 | }; | |
139 | ||
559d6701 TV |
140 | enum omap_dss_venc_type { |
141 | OMAP_DSS_VENC_TYPE_COMPOSITE, | |
142 | OMAP_DSS_VENC_TYPE_SVIDEO, | |
143 | }; | |
144 | ||
a3b3cc2b AT |
145 | enum omap_dss_dsi_pixel_format { |
146 | OMAP_DSS_DSI_FMT_RGB888, | |
147 | OMAP_DSS_DSI_FMT_RGB666, | |
148 | OMAP_DSS_DSI_FMT_RGB666_PACKED, | |
149 | OMAP_DSS_DSI_FMT_RGB565, | |
150 | }; | |
151 | ||
7e951ee9 AT |
152 | enum omap_dss_dsi_mode { |
153 | OMAP_DSS_DSI_CMD_MODE = 0, | |
154 | OMAP_DSS_DSI_VIDEO_MODE, | |
155 | }; | |
156 | ||
559d6701 TV |
157 | enum omap_display_caps { |
158 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | |
159 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | |
160 | }; | |
161 | ||
559d6701 TV |
162 | enum omap_dss_display_state { |
163 | OMAP_DSS_DISPLAY_DISABLED = 0, | |
164 | OMAP_DSS_DISPLAY_ACTIVE, | |
559d6701 TV |
165 | }; |
166 | ||
9c0b8420 RN |
167 | enum omap_dss_audio_state { |
168 | OMAP_DSS_AUDIO_DISABLED = 0, | |
169 | OMAP_DSS_AUDIO_ENABLED, | |
170 | OMAP_DSS_AUDIO_CONFIGURED, | |
171 | OMAP_DSS_AUDIO_PLAYING, | |
172 | }; | |
173 | ||
559d6701 | 174 | enum omap_dss_rotation_type { |
65e006ff CM |
175 | OMAP_DSS_ROT_DMA = 1 << 0, |
176 | OMAP_DSS_ROT_VRFB = 1 << 1, | |
177 | OMAP_DSS_ROT_TILER = 1 << 2, | |
559d6701 TV |
178 | }; |
179 | ||
180 | /* clockwise rotation angle */ | |
181 | enum omap_dss_rotation_angle { | |
182 | OMAP_DSS_ROT_0 = 0, | |
183 | OMAP_DSS_ROT_90 = 1, | |
184 | OMAP_DSS_ROT_180 = 2, | |
185 | OMAP_DSS_ROT_270 = 3, | |
186 | }; | |
187 | ||
188 | enum omap_overlay_caps { | |
189 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | |
f6dc8150 TV |
190 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
191 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, | |
11354dd5 | 192 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, |
d79db853 AT |
193 | OMAP_DSS_OVL_CAP_POS = 1 << 4, |
194 | OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, | |
559d6701 TV |
195 | }; |
196 | ||
197 | enum omap_overlay_manager_caps { | |
4a9e78ab | 198 | OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ |
559d6701 TV |
199 | }; |
200 | ||
89a35e51 AT |
201 | enum omap_dss_clk_source { |
202 | OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK | |
203 | * OMAP4: DSS_FCLK */ | |
204 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK | |
205 | * OMAP4: PLL1_CLK1 */ | |
206 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK | |
207 | * OMAP4: PLL1_CLK2 */ | |
5a8b572d AT |
208 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ |
209 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ | |
89a35e51 AT |
210 | }; |
211 | ||
9a901683 M |
212 | enum omap_hdmi_flags { |
213 | OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, | |
214 | }; | |
215 | ||
484dc404 AT |
216 | enum omap_dss_output_id { |
217 | OMAP_DSS_OUTPUT_DPI = 1 << 0, | |
218 | OMAP_DSS_OUTPUT_DBI = 1 << 1, | |
219 | OMAP_DSS_OUTPUT_SDI = 1 << 2, | |
220 | OMAP_DSS_OUTPUT_DSI1 = 1 << 3, | |
221 | OMAP_DSS_OUTPUT_DSI2 = 1 << 4, | |
222 | OMAP_DSS_OUTPUT_VENC = 1 << 5, | |
223 | OMAP_DSS_OUTPUT_HDMI = 1 << 6, | |
224 | }; | |
225 | ||
559d6701 TV |
226 | /* RFBI */ |
227 | ||
228 | struct rfbi_timings { | |
229 | int cs_on_time; | |
230 | int cs_off_time; | |
231 | int we_on_time; | |
232 | int we_off_time; | |
233 | int re_on_time; | |
234 | int re_off_time; | |
235 | int we_cycle_time; | |
236 | int re_cycle_time; | |
237 | int cs_pulse_width; | |
238 | int access_time; | |
239 | ||
240 | int clk_div; | |
241 | ||
242 | u32 tim[5]; /* set by rfbi_convert_timings() */ | |
243 | ||
244 | int converted; | |
245 | }; | |
246 | ||
247 | void omap_rfbi_write_command(const void *buf, u32 len); | |
248 | void omap_rfbi_read_data(void *buf, u32 len); | |
249 | void omap_rfbi_write_data(const void *buf, u32 len); | |
250 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
251 | u16 x, u16 y, | |
252 | u16 w, u16 h); | |
253 | int omap_rfbi_enable_te(bool enable, unsigned line); | |
254 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
255 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
256 | int hs_pol_inv, int vs_pol_inv, int extif_div); | |
773139f1 TV |
257 | void rfbi_bus_lock(void); |
258 | void rfbi_bus_unlock(void); | |
559d6701 TV |
259 | |
260 | /* DSI */ | |
8af6ff01 | 261 | |
478d7df8 TV |
262 | enum omap_dss_dsi_trans_mode { |
263 | /* Sync Pulses: both sync start and end packets sent */ | |
264 | OMAP_DSS_DSI_PULSE_MODE, | |
265 | /* Sync Events: only sync start packets sent */ | |
266 | OMAP_DSS_DSI_EVENT_MODE, | |
267 | /* Burst: only sync start packets sent, pixels are time compressed */ | |
268 | OMAP_DSS_DSI_BURST_MODE, | |
269 | }; | |
270 | ||
6b849375 | 271 | struct omap_dss_dsi_videomode_timings { |
f1e0001f TV |
272 | unsigned long hsclk; |
273 | ||
274 | unsigned ndl; | |
275 | unsigned bitspp; | |
276 | ||
277 | /* pixels */ | |
278 | u16 hact; | |
279 | /* lines */ | |
280 | u16 vact; | |
281 | ||
8af6ff01 AT |
282 | /* DSI video mode blanking data */ |
283 | /* Unit: byte clock cycles */ | |
f1e0001f | 284 | u16 hss; |
8af6ff01 | 285 | u16 hsa; |
f1e0001f | 286 | u16 hse; |
8af6ff01 AT |
287 | u16 hfp; |
288 | u16 hbp; | |
289 | /* Unit: line clocks */ | |
290 | u16 vsa; | |
291 | u16 vfp; | |
292 | u16 vbp; | |
293 | ||
294 | /* DSI blanking modes */ | |
295 | int blanking_mode; | |
296 | int hsa_blanking_mode; | |
297 | int hbp_blanking_mode; | |
298 | int hfp_blanking_mode; | |
299 | ||
478d7df8 | 300 | enum omap_dss_dsi_trans_mode trans_mode; |
8af6ff01 AT |
301 | |
302 | bool ddr_clk_always_on; | |
303 | int window_sync; | |
304 | }; | |
305 | ||
777f05cc TV |
306 | struct omap_dss_dsi_config { |
307 | enum omap_dss_dsi_mode mode; | |
308 | enum omap_dss_dsi_pixel_format pixel_format; | |
309 | const struct omap_video_timings *timings; | |
777f05cc | 310 | |
f1e0001f TV |
311 | unsigned long hs_clk_min, hs_clk_max; |
312 | unsigned long lp_clk_min, lp_clk_max; | |
313 | ||
314 | bool ddr_clk_always_on; | |
315 | enum omap_dss_dsi_trans_mode trans_mode; | |
777f05cc TV |
316 | }; |
317 | ||
1ffefe75 AT |
318 | void dsi_bus_lock(struct omap_dss_device *dssdev); |
319 | void dsi_bus_unlock(struct omap_dss_device *dssdev); | |
320 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
321 | int len); | |
6ff8aa31 AT |
322 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
323 | int len); | |
324 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); | |
325 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); | |
1ffefe75 AT |
326 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
327 | u8 param); | |
6ff8aa31 AT |
328 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
329 | u8 param); | |
330 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
331 | u8 param1, u8 param2); | |
1ffefe75 AT |
332 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
333 | u8 *data, int len); | |
6ff8aa31 AT |
334 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
335 | u8 *data, int len); | |
1ffefe75 AT |
336 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
337 | u8 *buf, int buflen); | |
b3b89c05 AT |
338 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, |
339 | int buflen); | |
340 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
341 | u8 *buf, int buflen); | |
342 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
343 | u8 param1, u8 param2, u8 *buf, int buflen); | |
1ffefe75 AT |
344 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
345 | u16 len); | |
346 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); | |
347 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); | |
9a147a65 TV |
348 | int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); |
349 | void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); | |
559d6701 | 350 | |
acd18af9 TV |
351 | enum omapdss_version { |
352 | OMAPDSS_VER_UNKNOWN = 0, | |
353 | OMAPDSS_VER_OMAP24xx, | |
354 | OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */ | |
355 | OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */ | |
356 | OMAPDSS_VER_OMAP3630, | |
357 | OMAPDSS_VER_AM35xx, | |
358 | OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */ | |
359 | OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */ | |
360 | OMAPDSS_VER_OMAP4, /* All other OMAP4s */ | |
361 | OMAPDSS_VER_OMAP5, | |
362 | }; | |
363 | ||
559d6701 TV |
364 | /* Board specific data */ |
365 | struct omap_dss_board_info { | |
aac927c9 | 366 | int (*get_context_loss_count)(struct device *dev); |
559d6701 TV |
367 | int num_devices; |
368 | struct omap_dss_device **devices; | |
369 | struct omap_dss_device *default_device; | |
0a200126 | 370 | const char *default_display_name; |
5bc416cb TV |
371 | int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); |
372 | void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); | |
62c1dcfc | 373 | int (*set_min_bus_tput)(struct device *dev, unsigned long r); |
acd18af9 | 374 | enum omapdss_version version; |
559d6701 TV |
375 | }; |
376 | ||
b7ee79ab SS |
377 | /* Init with the board info */ |
378 | extern int omap_display_init(struct omap_dss_board_info *board_data); | |
ee9dfd82 | 379 | /* HDMI mux init*/ |
9a901683 | 380 | extern int omap_hdmi_init(enum omap_hdmi_flags flags); |
b7ee79ab | 381 | |
559d6701 TV |
382 | struct omap_video_timings { |
383 | /* Unit: pixels */ | |
384 | u16 x_res; | |
385 | /* Unit: pixels */ | |
386 | u16 y_res; | |
387 | /* Unit: KHz */ | |
388 | u32 pixel_clock; | |
389 | /* Unit: pixel clocks */ | |
390 | u16 hsw; /* Horizontal synchronization pulse width */ | |
391 | /* Unit: pixel clocks */ | |
392 | u16 hfp; /* Horizontal front porch */ | |
393 | /* Unit: pixel clocks */ | |
394 | u16 hbp; /* Horizontal back porch */ | |
395 | /* Unit: line clocks */ | |
396 | u16 vsw; /* Vertical synchronization pulse width */ | |
397 | /* Unit: line clocks */ | |
398 | u16 vfp; /* Vertical front porch */ | |
399 | /* Unit: line clocks */ | |
400 | u16 vbp; /* Vertical back porch */ | |
a8d5e41c AT |
401 | |
402 | /* Vsync logic level */ | |
403 | enum omap_dss_signal_level vsync_level; | |
404 | /* Hsync logic level */ | |
405 | enum omap_dss_signal_level hsync_level; | |
23c8f88e AT |
406 | /* Interlaced or Progressive timings */ |
407 | bool interlace; | |
a8d5e41c AT |
408 | /* Pixel clock edge to drive LCD data */ |
409 | enum omap_dss_signal_edge data_pclk_edge; | |
410 | /* Data enable logic level */ | |
411 | enum omap_dss_signal_level de_level; | |
412 | /* Pixel clock edges to drive HSYNC and VSYNC signals */ | |
413 | enum omap_dss_signal_edge sync_pclk_edge; | |
559d6701 TV |
414 | }; |
415 | ||
416 | #ifdef CONFIG_OMAP2_DSS_VENC | |
417 | /* Hardcoded timings for tv modes. Venc only uses these to | |
418 | * identify the mode, and does not actually use the configs | |
419 | * itself. However, the configs should be something that | |
420 | * a normal monitor can also show */ | |
5a1819e3 TK |
421 | extern const struct omap_video_timings omap_dss_pal_timings; |
422 | extern const struct omap_video_timings omap_dss_ntsc_timings; | |
559d6701 TV |
423 | #endif |
424 | ||
3c07cae2 TV |
425 | struct omap_dss_cpr_coefs { |
426 | s16 rr, rg, rb; | |
427 | s16 gr, gg, gb; | |
428 | s16 br, bg, bb; | |
429 | }; | |
430 | ||
559d6701 | 431 | struct omap_overlay_info { |
559d6701 | 432 | u32 paddr; |
0d66cbb5 | 433 | u32 p_uv_addr; /* for NV12 format */ |
559d6701 TV |
434 | u16 screen_width; |
435 | u16 width; | |
436 | u16 height; | |
437 | enum omap_color_mode color_mode; | |
438 | u8 rotation; | |
439 | enum omap_dss_rotation_type rotation_type; | |
440 | bool mirror; | |
441 | ||
442 | u16 pos_x; | |
443 | u16 pos_y; | |
444 | u16 out_width; /* if 0, out_width == width */ | |
445 | u16 out_height; /* if 0, out_height == height */ | |
446 | u8 global_alpha; | |
fd28a390 | 447 | u8 pre_mult_alpha; |
54128701 | 448 | u8 zorder; |
559d6701 TV |
449 | }; |
450 | ||
451 | struct omap_overlay { | |
452 | struct kobject kobj; | |
453 | struct list_head list; | |
454 | ||
455 | /* static fields */ | |
456 | const char *name; | |
4a9e78ab | 457 | enum omap_plane id; |
559d6701 TV |
458 | enum omap_color_mode supported_modes; |
459 | enum omap_overlay_caps caps; | |
460 | ||
461 | /* dynamic fields */ | |
462 | struct omap_overlay_manager *manager; | |
559d6701 | 463 | |
9d11c321 TV |
464 | /* |
465 | * The following functions do not block: | |
466 | * | |
467 | * is_enabled | |
468 | * set_overlay_info | |
469 | * get_overlay_info | |
470 | * | |
471 | * The rest of the functions may block and cannot be called from | |
472 | * interrupt context | |
473 | */ | |
474 | ||
aaa874a9 TV |
475 | int (*enable)(struct omap_overlay *ovl); |
476 | int (*disable)(struct omap_overlay *ovl); | |
477 | bool (*is_enabled)(struct omap_overlay *ovl); | |
478 | ||
559d6701 TV |
479 | int (*set_manager)(struct omap_overlay *ovl, |
480 | struct omap_overlay_manager *mgr); | |
481 | int (*unset_manager)(struct omap_overlay *ovl); | |
482 | ||
483 | int (*set_overlay_info)(struct omap_overlay *ovl, | |
484 | struct omap_overlay_info *info); | |
485 | void (*get_overlay_info)(struct omap_overlay *ovl, | |
486 | struct omap_overlay_info *info); | |
487 | ||
488 | int (*wait_for_go)(struct omap_overlay *ovl); | |
794bc4ee AT |
489 | |
490 | struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); | |
559d6701 TV |
491 | }; |
492 | ||
493 | struct omap_overlay_manager_info { | |
494 | u32 default_color; | |
495 | ||
496 | enum omap_dss_trans_key_type trans_key_type; | |
497 | u32 trans_key; | |
498 | bool trans_enabled; | |
499 | ||
11354dd5 | 500 | bool partial_alpha_enabled; |
3c07cae2 TV |
501 | |
502 | bool cpr_enable; | |
503 | struct omap_dss_cpr_coefs cpr_coefs; | |
559d6701 TV |
504 | }; |
505 | ||
506 | struct omap_overlay_manager { | |
507 | struct kobject kobj; | |
559d6701 TV |
508 | |
509 | /* static fields */ | |
510 | const char *name; | |
4a9e78ab | 511 | enum omap_channel id; |
559d6701 | 512 | enum omap_overlay_manager_caps caps; |
07e327c9 | 513 | struct list_head overlays; |
559d6701 | 514 | enum omap_display_type supported_displays; |
97f01b3a | 515 | enum omap_dss_output_id supported_outputs; |
559d6701 TV |
516 | |
517 | /* dynamic fields */ | |
1f68d9c4 | 518 | struct omap_dss_device *output; |
559d6701 | 519 | |
9d11c321 TV |
520 | /* |
521 | * The following functions do not block: | |
522 | * | |
523 | * set_manager_info | |
524 | * get_manager_info | |
525 | * apply | |
526 | * | |
527 | * The rest of the functions may block and cannot be called from | |
528 | * interrupt context | |
529 | */ | |
530 | ||
97f01b3a | 531 | int (*set_output)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 532 | struct omap_dss_device *output); |
97f01b3a | 533 | int (*unset_output)(struct omap_overlay_manager *mgr); |
559d6701 TV |
534 | |
535 | int (*set_manager_info)(struct omap_overlay_manager *mgr, | |
536 | struct omap_overlay_manager_info *info); | |
537 | void (*get_manager_info)(struct omap_overlay_manager *mgr, | |
538 | struct omap_overlay_manager_info *info); | |
539 | ||
540 | int (*apply)(struct omap_overlay_manager *mgr); | |
541 | int (*wait_for_go)(struct omap_overlay_manager *mgr); | |
3f71cbe7 | 542 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
794bc4ee AT |
543 | |
544 | struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
545 | }; |
546 | ||
e4a9e94c TV |
547 | /* 22 pins means 1 clk lane and 10 data lanes */ |
548 | #define OMAP_DSS_MAX_DSI_PINS 22 | |
549 | ||
550 | struct omap_dsi_pin_config { | |
551 | int num_pins; | |
552 | /* | |
553 | * pin numbers in the following order: | |
554 | * clk+, clk- | |
555 | * data1+, data1- | |
556 | * data2+, data2- | |
557 | * ... | |
558 | */ | |
559 | int pins[OMAP_DSS_MAX_DSI_PINS]; | |
560 | }; | |
561 | ||
749feffa AT |
562 | struct omap_dss_writeback_info { |
563 | u32 paddr; | |
564 | u32 p_uv_addr; | |
565 | u16 buf_width; | |
566 | u16 width; | |
567 | u16 height; | |
568 | enum omap_color_mode color_mode; | |
569 | u8 rotation; | |
570 | enum omap_dss_rotation_type rotation_type; | |
571 | bool mirror; | |
572 | u8 pre_mult_alpha; | |
573 | }; | |
574 | ||
559d6701 | 575 | struct omap_dss_device { |
ecc8b370 TV |
576 | /* old device, to be removed */ |
577 | struct device old_dev; | |
578 | ||
579 | /* new device, pointer to panel device */ | |
580 | struct device *dev; | |
559d6701 | 581 | |
4f3e44ea TV |
582 | struct module *owner; |
583 | ||
2e7e3dc7 TV |
584 | struct list_head panel_list; |
585 | ||
586 | /* alias in the form of "display%d" */ | |
587 | char alias[16]; | |
588 | ||
559d6701 | 589 | enum omap_display_type type; |
1f68d9c4 | 590 | enum omap_display_type output_type; |
559d6701 | 591 | |
2eea5ae6 | 592 | /* obsolete, to be removed */ |
18faa1b6 SS |
593 | enum omap_channel channel; |
594 | ||
559d6701 TV |
595 | union { |
596 | struct { | |
597 | u8 data_lines; | |
598 | } dpi; | |
599 | ||
600 | struct { | |
601 | u8 channel; | |
602 | u8 data_lines; | |
603 | } rfbi; | |
604 | ||
605 | struct { | |
606 | u8 datapairs; | |
607 | } sdi; | |
608 | ||
609 | struct { | |
a72b64b9 AT |
610 | int module; |
611 | ||
559d6701 TV |
612 | bool ext_te; |
613 | u8 ext_te_gpio; | |
614 | } dsi; | |
615 | ||
616 | struct { | |
617 | enum omap_dss_venc_type type; | |
618 | bool invert_polarity; | |
619 | } venc; | |
620 | } phy; | |
621 | ||
622 | struct { | |
623 | struct omap_video_timings timings; | |
624 | ||
a3b3cc2b | 625 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; |
7e951ee9 | 626 | enum omap_dss_dsi_mode dsi_mode; |
559d6701 TV |
627 | } panel; |
628 | ||
629 | struct { | |
630 | u8 pixel_size; | |
631 | struct rfbi_timings rfbi_timings; | |
559d6701 TV |
632 | } ctrl; |
633 | ||
634 | int reset_gpio; | |
635 | ||
636 | int max_backlight_level; | |
637 | ||
638 | const char *name; | |
639 | ||
640 | /* used to match device to driver */ | |
641 | const char *driver_name; | |
642 | ||
643 | void *data; | |
644 | ||
645 | struct omap_dss_driver *driver; | |
646 | ||
647 | /* helper variable for driver suspend/resume */ | |
648 | bool activate_after_resume; | |
649 | ||
650 | enum omap_display_caps caps; | |
651 | ||
1f68d9c4 | 652 | struct omap_dss_device *output; |
559d6701 TV |
653 | |
654 | enum omap_dss_display_state state; | |
655 | ||
9c0b8420 RN |
656 | enum omap_dss_audio_state audio_state; |
657 | ||
559d6701 TV |
658 | /* platform specific */ |
659 | int (*platform_enable)(struct omap_dss_device *dssdev); | |
660 | void (*platform_disable)(struct omap_dss_device *dssdev); | |
661 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | |
662 | int (*get_backlight)(struct omap_dss_device *dssdev); | |
1f68d9c4 TV |
663 | |
664 | ||
665 | /* OMAP DSS output specific fields */ | |
666 | ||
667 | struct list_head list; | |
668 | ||
669 | /* DISPC channel for this output */ | |
670 | enum omap_channel dispc_channel; | |
671 | ||
672 | /* output instance */ | |
673 | enum omap_dss_output_id id; | |
674 | ||
675 | /* dynamic fields */ | |
676 | struct omap_overlay_manager *manager; | |
677 | ||
678 | struct omap_dss_device *device; | |
559d6701 TV |
679 | }; |
680 | ||
c49d005b TV |
681 | struct omap_dss_hdmi_data |
682 | { | |
cca35017 TV |
683 | int ct_cp_hpd_gpio; |
684 | int ls_oe_gpio; | |
c49d005b TV |
685 | int hpd_gpio; |
686 | }; | |
687 | ||
9c0b8420 RN |
688 | struct omap_dss_audio { |
689 | struct snd_aes_iec958 *iec; | |
690 | struct snd_cea_861_aud_if *cea; | |
691 | }; | |
692 | ||
559d6701 TV |
693 | struct omap_dss_driver { |
694 | struct device_driver driver; | |
695 | ||
696 | int (*probe)(struct omap_dss_device *); | |
697 | void (*remove)(struct omap_dss_device *); | |
698 | ||
a7e71e7f TV |
699 | int (*connect)(struct omap_dss_device *dssdev); |
700 | void (*disconnect)(struct omap_dss_device *dssdev); | |
701 | ||
559d6701 TV |
702 | int (*enable)(struct omap_dss_device *display); |
703 | void (*disable)(struct omap_dss_device *display); | |
559d6701 TV |
704 | int (*run_test)(struct omap_dss_device *display, int test); |
705 | ||
18946f62 TV |
706 | int (*update)(struct omap_dss_device *dssdev, |
707 | u16 x, u16 y, u16 w, u16 h); | |
708 | int (*sync)(struct omap_dss_device *dssdev); | |
709 | ||
559d6701 | 710 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
225b650d | 711 | int (*get_te)(struct omap_dss_device *dssdev); |
559d6701 TV |
712 | |
713 | u8 (*get_rotate)(struct omap_dss_device *dssdev); | |
714 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); | |
715 | ||
716 | bool (*get_mirror)(struct omap_dss_device *dssdev); | |
717 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); | |
718 | ||
719 | int (*memory_read)(struct omap_dss_device *dssdev, | |
720 | void *buf, size_t size, | |
721 | u16 x, u16 y, u16 w, u16 h); | |
96adcece TV |
722 | |
723 | void (*get_resolution)(struct omap_dss_device *dssdev, | |
724 | u16 *xres, u16 *yres); | |
7a0987bf JN |
725 | void (*get_dimensions)(struct omap_dss_device *dssdev, |
726 | u32 *width, u32 *height); | |
a2699504 | 727 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
36511312 | 728 | |
69b2048f TV |
729 | int (*check_timings)(struct omap_dss_device *dssdev, |
730 | struct omap_video_timings *timings); | |
731 | void (*set_timings)(struct omap_dss_device *dssdev, | |
732 | struct omap_video_timings *timings); | |
733 | void (*get_timings)(struct omap_dss_device *dssdev, | |
734 | struct omap_video_timings *timings); | |
735 | ||
36511312 TV |
736 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
737 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
3d5e0ef7 TV |
738 | |
739 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | |
df4769c9 | 740 | bool (*detect)(struct omap_dss_device *dssdev); |
9c0b8420 RN |
741 | |
742 | /* | |
743 | * For display drivers that support audio. This encompasses | |
744 | * HDMI and DisplayPort at the moment. | |
745 | */ | |
746 | /* | |
747 | * Note: These functions might sleep. Do not call while | |
748 | * holding a spinlock/readlock. | |
749 | */ | |
750 | int (*audio_enable)(struct omap_dss_device *dssdev); | |
751 | void (*audio_disable)(struct omap_dss_device *dssdev); | |
752 | bool (*audio_supported)(struct omap_dss_device *dssdev); | |
753 | int (*audio_config)(struct omap_dss_device *dssdev, | |
754 | struct omap_dss_audio *audio); | |
755 | /* Note: These functions may not sleep */ | |
756 | int (*audio_start)(struct omap_dss_device *dssdev); | |
757 | void (*audio_stop)(struct omap_dss_device *dssdev); | |
758 | ||
559d6701 TV |
759 | }; |
760 | ||
b2c7d54f | 761 | enum omapdss_version omapdss_get_version(void); |
591a0ac7 | 762 | bool omapdss_is_initialized(void); |
b2c7d54f | 763 | |
559d6701 TV |
764 | int omap_dss_register_driver(struct omap_dss_driver *); |
765 | void omap_dss_unregister_driver(struct omap_dss_driver *); | |
766 | ||
2e7e3dc7 TV |
767 | int omapdss_register_display(struct omap_dss_device *dssdev); |
768 | void omapdss_unregister_display(struct omap_dss_device *dssdev); | |
769 | ||
559d6701 TV |
770 | void omap_dss_get_device(struct omap_dss_device *dssdev); |
771 | void omap_dss_put_device(struct omap_dss_device *dssdev); | |
772 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) | |
773 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); | |
774 | struct omap_dss_device *omap_dss_find_device(void *data, | |
775 | int (*match)(struct omap_dss_device *dssdev, void *data)); | |
2bbcce5e | 776 | const char *omapdss_get_default_display_name(void); |
559d6701 | 777 | |
6fcd485b TV |
778 | void videomode_to_omap_video_timings(const struct videomode *vm, |
779 | struct omap_video_timings *ovt); | |
780 | void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, | |
781 | struct videomode *vm); | |
782 | ||
eda34273 TV |
783 | int dss_feat_get_num_mgrs(void); |
784 | int dss_feat_get_num_ovls(void); | |
785 | enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); | |
786 | enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); | |
787 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); | |
788 | ||
789 | ||
790 | ||
559d6701 TV |
791 | int omap_dss_get_num_overlay_managers(void); |
792 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); | |
793 | ||
794 | int omap_dss_get_num_overlays(void); | |
795 | struct omap_overlay *omap_dss_get_overlay(int num); | |
796 | ||
1f68d9c4 TV |
797 | struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); |
798 | struct omap_dss_device *omap_dss_find_output(const char *name); | |
799 | struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node); | |
800 | int omapdss_output_set_device(struct omap_dss_device *out, | |
6d71b923 | 801 | struct omap_dss_device *dssdev); |
1f68d9c4 | 802 | int omapdss_output_unset_device(struct omap_dss_device *out); |
484dc404 | 803 | |
1f68d9c4 | 804 | struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); |
be8e8e1c TV |
805 | struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); |
806 | ||
96adcece TV |
807 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
808 | u16 *xres, u16 *yres); | |
a2699504 | 809 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
4b6430fc GI |
810 | void omapdss_default_get_timings(struct omap_dss_device *dssdev, |
811 | struct omap_video_timings *timings); | |
a2699504 | 812 | |
559d6701 TV |
813 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
814 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
815 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
816 | ||
348be69d TV |
817 | u32 dispc_read_irqstatus(void); |
818 | void dispc_clear_irqstatus(u32 mask); | |
819 | u32 dispc_read_irqenable(void); | |
820 | void dispc_write_irqenable(u32 mask); | |
821 | ||
822 | int dispc_request_irq(irq_handler_t handler, void *dev_id); | |
823 | void dispc_free_irq(void *dev_id); | |
824 | ||
825 | int dispc_runtime_get(void); | |
826 | void dispc_runtime_put(void); | |
827 | ||
828 | void dispc_mgr_enable(enum omap_channel channel, bool enable); | |
829 | bool dispc_mgr_is_enabled(enum omap_channel channel); | |
830 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); | |
831 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); | |
832 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); | |
833 | bool dispc_mgr_go_busy(enum omap_channel channel); | |
834 | void dispc_mgr_go(enum omap_channel channel); | |
835 | void dispc_mgr_set_lcd_config(enum omap_channel channel, | |
836 | const struct dss_lcd_mgr_config *config); | |
837 | void dispc_mgr_set_timings(enum omap_channel channel, | |
838 | const struct omap_video_timings *timings); | |
839 | void dispc_mgr_setup(enum omap_channel channel, | |
840 | const struct omap_overlay_manager_info *info); | |
841 | ||
842 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, | |
843 | const struct omap_overlay_info *oi, | |
844 | const struct omap_video_timings *timings, | |
845 | int *x_predecim, int *y_predecim); | |
846 | ||
847 | int dispc_ovl_enable(enum omap_plane plane, bool enable); | |
848 | bool dispc_ovl_enabled(enum omap_plane plane); | |
849 | void dispc_ovl_set_channel_out(enum omap_plane plane, | |
850 | enum omap_channel channel); | |
851 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, | |
852 | bool replication, const struct omap_video_timings *mgr_timings, | |
853 | bool mem_to_mem); | |
854 | ||
559d6701 | 855 | #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) |
ecc8b370 | 856 | #define to_dss_device(x) container_of((x), struct omap_dss_device, old_dev) |
559d6701 | 857 | |
1ffefe75 AT |
858 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
859 | bool enable); | |
225b650d | 860 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); |
777f05cc TV |
861 | int omapdss_dsi_set_config(struct omap_dss_device *dssdev, |
862 | const struct omap_dss_dsi_config *config); | |
61140c9a | 863 | |
5476e74a | 864 | int omap_dsi_update(struct omap_dss_device *dssdev, int channel, |
18946f62 | 865 | void (*callback)(int, void *), void *data); |
5ee3c144 AT |
866 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); |
867 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); | |
868 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); | |
e4a9e94c TV |
869 | int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, |
870 | const struct omap_dsi_pin_config *pin_cfg); | |
18946f62 | 871 | |
37ac60e4 | 872 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); |
2a89dc15 | 873 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 874 | bool disconnect_lanes, bool enter_ulps); |
37ac60e4 TV |
875 | |
876 | int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); | |
877 | void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); | |
c499144c AT |
878 | void omapdss_dpi_set_timings(struct omap_dss_device *dssdev, |
879 | struct omap_video_timings *timings); | |
69b2048f TV |
880 | int dpi_check_timings(struct omap_dss_device *dssdev, |
881 | struct omap_video_timings *timings); | |
c6b393d4 | 882 | void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines); |
37ac60e4 TV |
883 | |
884 | int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); | |
885 | void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); | |
c7833f7b AT |
886 | void omapdss_sdi_set_timings(struct omap_dss_device *dssdev, |
887 | struct omap_video_timings *timings); | |
889b4fd7 | 888 | void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs); |
37ac60e4 TV |
889 | |
890 | int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); | |
891 | void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); | |
43eab861 AT |
892 | int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), |
893 | void *data); | |
475989b7 | 894 | int omap_rfbi_configure(struct omap_dss_device *dssdev); |
6ff9dd5a | 895 | void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); |
b02875be AT |
896 | void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev, |
897 | int pixel_size); | |
475989b7 AT |
898 | void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev, |
899 | int data_lines); | |
6e883324 AT |
900 | void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev, |
901 | struct rfbi_timings *timings); | |
18946f62 | 902 | |
8dd2491a TV |
903 | int omapdss_compat_init(void); |
904 | void omapdss_compat_uninit(void); | |
905 | ||
a97a9634 | 906 | struct dss_mgr_ops { |
a7e71e7f | 907 | int (*connect)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 908 | struct omap_dss_device *dst); |
a7e71e7f | 909 | void (*disconnect)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 910 | struct omap_dss_device *dst); |
a7e71e7f | 911 | |
a97a9634 TV |
912 | void (*start_update)(struct omap_overlay_manager *mgr); |
913 | int (*enable)(struct omap_overlay_manager *mgr); | |
914 | void (*disable)(struct omap_overlay_manager *mgr); | |
915 | void (*set_timings)(struct omap_overlay_manager *mgr, | |
916 | const struct omap_video_timings *timings); | |
917 | void (*set_lcd_config)(struct omap_overlay_manager *mgr, | |
918 | const struct dss_lcd_mgr_config *config); | |
919 | int (*register_framedone_handler)(struct omap_overlay_manager *mgr, | |
920 | void (*handler)(void *), void *data); | |
921 | void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr, | |
922 | void (*handler)(void *), void *data); | |
923 | }; | |
924 | ||
925 | int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); | |
926 | void dss_uninstall_mgr_ops(void); | |
927 | ||
a7e71e7f | 928 | int dss_mgr_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 929 | struct omap_dss_device *dst); |
a7e71e7f | 930 | void dss_mgr_disconnect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 931 | struct omap_dss_device *dst); |
a97a9634 TV |
932 | void dss_mgr_set_timings(struct omap_overlay_manager *mgr, |
933 | const struct omap_video_timings *timings); | |
934 | void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, | |
935 | const struct dss_lcd_mgr_config *config); | |
936 | int dss_mgr_enable(struct omap_overlay_manager *mgr); | |
937 | void dss_mgr_disable(struct omap_overlay_manager *mgr); | |
938 | void dss_mgr_start_update(struct omap_overlay_manager *mgr); | |
939 | int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr, | |
940 | void (*handler)(void *), void *data); | |
941 | void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr, | |
942 | void (*handler)(void *), void *data); | |
a7e71e7f TV |
943 | |
944 | static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) | |
945 | { | |
946 | return dssdev->output; | |
947 | } | |
948 | ||
949 | static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) | |
950 | { | |
951 | return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; | |
952 | } | |
953 | ||
559d6701 | 954 | #endif |