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18f19aa6 JF |
1 | /* |
2 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
3 | * of this software and associated documentation files (the "Software"), to | |
4 | * deal in the Software without restriction, including without limitation the | |
5 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or | |
6 | * sell copies of the Software, and to permit persons to whom the Software is | |
7 | * furnished to do so, subject to the following conditions: | |
8 | * | |
9 | * The above copyright notice and this permission notice shall be included in | |
10 | * all copies or substantial portions of the Software. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |
15 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
16 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
17 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
18 | * DEALINGS IN THE SOFTWARE. | |
19 | */ | |
20 | ||
21 | #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ | |
22 | #define __XEN_PUBLIC_HVM_PARAMS_H__ | |
23 | ||
a1ce3928 | 24 | #include <xen/interface/hvm/hvm_op.h> |
18f19aa6 JF |
25 | |
26 | /* | |
27 | * Parameter space for HVMOP_{set,get}_param. | |
28 | */ | |
29 | ||
b6f0bcc2 | 30 | #define HVM_PARAM_CALLBACK_IRQ 0 |
18f19aa6 JF |
31 | /* |
32 | * How should CPU0 event-channel notifications be delivered? | |
b6f0bcc2 | 33 | * |
18f19aa6 | 34 | * If val == 0 then CPU0 event-channel notifications are not delivered. |
b6f0bcc2 SZ |
35 | * If val != 0, val[63:56] encodes the type, as follows: |
36 | */ | |
37 | ||
38 | #define HVM_PARAM_CALLBACK_TYPE_GSI 0 | |
39 | /* | |
40 | * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, | |
41 | * and disables all notifications. | |
42 | */ | |
43 | ||
44 | #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 | |
45 | /* | |
46 | * val[55:0] is a delivery PCI INTx line: | |
47 | * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] | |
48 | */ | |
49 | ||
383ff518 | 50 | #if defined(__i386__) || defined(__x86_64__) |
b6f0bcc2 SZ |
51 | #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 |
52 | /* | |
53 | * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know | |
54 | * if this delivery method is available. | |
18f19aa6 | 55 | */ |
383ff518 SZ |
56 | #elif defined(__arm__) || defined(__aarch64__) |
57 | #define HVM_PARAM_CALLBACK_TYPE_PPI 2 | |
58 | /* | |
59 | * val[55:16] needs to be zero. | |
60 | * val[15:8] is interrupt flag of the PPI used by event-channel: | |
61 | * bit 8: the PPI is edge(1) or level(0) triggered | |
62 | * bit 9: the PPI is active low(1) or high(0) | |
63 | * val[7:0] is a PPI number used by event-channel. | |
64 | * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to | |
65 | * the notification is handled by the interrupt controller. | |
66 | */ | |
67 | #endif | |
18f19aa6 JF |
68 | |
69 | #define HVM_PARAM_STORE_PFN 1 | |
70 | #define HVM_PARAM_STORE_EVTCHN 2 | |
71 | ||
72 | #define HVM_PARAM_PAE_ENABLED 4 | |
73 | ||
74 | #define HVM_PARAM_IOREQ_PFN 5 | |
75 | ||
76 | #define HVM_PARAM_BUFIOREQ_PFN 6 | |
77 | ||
78 | /* | |
79 | * Set mode for virtual timers (currently x86 only): | |
80 | * delay_for_missed_ticks (default): | |
81 | * Do not advance a vcpu's time beyond the correct delivery time for | |
82 | * interrupts that have been missed due to preemption. Deliver missed | |
83 | * interrupts when the vcpu is rescheduled and advance the vcpu's virtual | |
84 | * time stepwise for each one. | |
85 | * no_delay_for_missed_ticks: | |
86 | * As above, missed interrupts are delivered, but guest time always tracks | |
87 | * wallclock (i.e., real) time while doing so. | |
88 | * no_missed_ticks_pending: | |
89 | * No missed interrupts are held pending. Instead, to ensure ticks are | |
90 | * delivered at some non-zero rate, if we detect missed ticks then the | |
91 | * internal tick alarm is not disabled if the VCPU is preempted during the | |
92 | * next tick period. | |
93 | * one_missed_tick_pending: | |
94 | * Missed interrupts are collapsed together and delivered as one 'late tick'. | |
95 | * Guest time always tracks wallclock (i.e., real) time. | |
96 | */ | |
97 | #define HVM_PARAM_TIMER_MODE 10 | |
98 | #define HVMPTM_delay_for_missed_ticks 0 | |
99 | #define HVMPTM_no_delay_for_missed_ticks 1 | |
100 | #define HVMPTM_no_missed_ticks_pending 2 | |
101 | #define HVMPTM_one_missed_tick_pending 3 | |
102 | ||
103 | /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ | |
104 | #define HVM_PARAM_HPET_ENABLED 11 | |
105 | ||
106 | /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ | |
107 | #define HVM_PARAM_IDENT_PT 12 | |
108 | ||
109 | /* Device Model domain, defaults to 0. */ | |
110 | #define HVM_PARAM_DM_DOMAIN 13 | |
111 | ||
112 | /* ACPI S state: currently support S0 and S3 on x86. */ | |
113 | #define HVM_PARAM_ACPI_S_STATE 14 | |
114 | ||
115 | /* TSS used on Intel when CR0.PE=0. */ | |
116 | #define HVM_PARAM_VM86_TSS 15 | |
117 | ||
118 | /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ | |
119 | #define HVM_PARAM_VPT_ALIGN 16 | |
120 | ||
eb5ef071 SS |
121 | /* Console debug shared memory ring and event channel */ |
122 | #define HVM_PARAM_CONSOLE_PFN 17 | |
123 | #define HVM_PARAM_CONSOLE_EVTCHN 18 | |
124 | ||
125 | #define HVM_NR_PARAMS 19 | |
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126 | |
127 | #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ |