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e0001a05 | 1 | /* Xtensa configuration settings. |
82704155 | 2 | Copyright (C) 2001-2019 Free Software Foundation, Inc. |
0a5b531f | 3 | Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. |
e0001a05 | 4 | |
c6d600f0 BW |
5 | This program is free software; you can redistribute it and/or modify |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2, or (at your option) | |
8 | any later version. | |
e0001a05 | 9 | |
c6d600f0 BW |
10 | This program is distributed in the hope that it will be useful, but |
11 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | General Public License for more details. | |
e0001a05 | 14 | |
c6d600f0 BW |
15 | You should have received a copy of the GNU General Public License |
16 | along with this program; if not, write to the Free Software | |
e172dbf8 | 17 | Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
e0001a05 NC |
18 | |
19 | #ifndef XTENSA_CONFIG_H | |
20 | #define XTENSA_CONFIG_H | |
21 | ||
22 | /* The macros defined here match those with the same names in the Xtensa | |
23 | compile-time HAL (Hardware Abstraction Layer). Please refer to the | |
24 | Xtensa System Software Reference Manual for documentation of these | |
25 | macros. */ | |
26 | ||
05235f71 | 27 | #undef XCHAL_HAVE_BE |
e0001a05 | 28 | #define XCHAL_HAVE_BE 1 |
05235f71 BW |
29 | |
30 | #undef XCHAL_HAVE_DENSITY | |
e0001a05 | 31 | #define XCHAL_HAVE_DENSITY 1 |
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32 | |
33 | #undef XCHAL_HAVE_CONST16 | |
902695bc | 34 | #define XCHAL_HAVE_CONST16 0 |
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35 | |
36 | #undef XCHAL_HAVE_ABS | |
902695bc | 37 | #define XCHAL_HAVE_ABS 1 |
05235f71 BW |
38 | |
39 | #undef XCHAL_HAVE_ADDX | |
902695bc | 40 | #define XCHAL_HAVE_ADDX 1 |
05235f71 BW |
41 | |
42 | #undef XCHAL_HAVE_L32R | |
902695bc | 43 | #define XCHAL_HAVE_L32R 1 |
05235f71 | 44 | |
43cd72b9 BW |
45 | #undef XSHAL_USE_ABSOLUTE_LITERALS |
46 | #define XSHAL_USE_ABSOLUTE_LITERALS 0 | |
47 | ||
0a5b531f DD |
48 | #undef XSHAL_HAVE_TEXT_SECTION_LITERALS |
49 | #define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ | |
50 | ||
05235f71 | 51 | #undef XCHAL_HAVE_MAC16 |
e0001a05 | 52 | #define XCHAL_HAVE_MAC16 0 |
05235f71 BW |
53 | |
54 | #undef XCHAL_HAVE_MUL16 | |
33430bd0 | 55 | #define XCHAL_HAVE_MUL16 1 |
05235f71 BW |
56 | |
57 | #undef XCHAL_HAVE_MUL32 | |
33430bd0 | 58 | #define XCHAL_HAVE_MUL32 1 |
05235f71 | 59 | |
51d04b5c BW |
60 | #undef XCHAL_HAVE_MUL32_HIGH |
61 | #define XCHAL_HAVE_MUL32_HIGH 0 | |
62 | ||
05235f71 | 63 | #undef XCHAL_HAVE_DIV32 |
33430bd0 | 64 | #define XCHAL_HAVE_DIV32 1 |
05235f71 BW |
65 | |
66 | #undef XCHAL_HAVE_NSA | |
e0001a05 | 67 | #define XCHAL_HAVE_NSA 1 |
05235f71 BW |
68 | |
69 | #undef XCHAL_HAVE_MINMAX | |
33430bd0 | 70 | #define XCHAL_HAVE_MINMAX 1 |
05235f71 BW |
71 | |
72 | #undef XCHAL_HAVE_SEXT | |
33430bd0 | 73 | #define XCHAL_HAVE_SEXT 1 |
05235f71 BW |
74 | |
75 | #undef XCHAL_HAVE_LOOPS | |
e0001a05 | 76 | #define XCHAL_HAVE_LOOPS 1 |
05235f71 | 77 | |
0a05a876 | 78 | #undef XCHAL_HAVE_THREADPTR |
33430bd0 | 79 | #define XCHAL_HAVE_THREADPTR 1 |
0a05a876 BW |
80 | |
81 | #undef XCHAL_HAVE_RELEASE_SYNC | |
33430bd0 | 82 | #define XCHAL_HAVE_RELEASE_SYNC 1 |
0a05a876 BW |
83 | |
84 | #undef XCHAL_HAVE_S32C1I | |
33430bd0 | 85 | #define XCHAL_HAVE_S32C1I 1 |
0a05a876 | 86 | |
05235f71 | 87 | #undef XCHAL_HAVE_BOOLEANS |
e0001a05 | 88 | #define XCHAL_HAVE_BOOLEANS 0 |
05235f71 BW |
89 | |
90 | #undef XCHAL_HAVE_FP | |
e0001a05 | 91 | #define XCHAL_HAVE_FP 0 |
05235f71 BW |
92 | |
93 | #undef XCHAL_HAVE_FP_DIV | |
e0001a05 | 94 | #define XCHAL_HAVE_FP_DIV 0 |
05235f71 BW |
95 | |
96 | #undef XCHAL_HAVE_FP_RECIP | |
e0001a05 | 97 | #define XCHAL_HAVE_FP_RECIP 0 |
05235f71 BW |
98 | |
99 | #undef XCHAL_HAVE_FP_SQRT | |
e0001a05 | 100 | #define XCHAL_HAVE_FP_SQRT 0 |
05235f71 BW |
101 | |
102 | #undef XCHAL_HAVE_FP_RSQRT | |
e0001a05 | 103 | #define XCHAL_HAVE_FP_RSQRT 0 |
05235f71 | 104 | |
0a5b531f DD |
105 | #undef XCHAL_HAVE_DFP_accel |
106 | #define XCHAL_HAVE_DFP_accel 0 | |
05235f71 | 107 | #undef XCHAL_HAVE_WINDOWED |
e0001a05 NC |
108 | #define XCHAL_HAVE_WINDOWED 1 |
109 | ||
6c7d412c | 110 | #undef XCHAL_NUM_AREGS |
33430bd0 | 111 | #define XCHAL_NUM_AREGS 32 |
6c7d412c | 112 | |
b2d179be BW |
113 | #undef XCHAL_HAVE_WIDE_BRANCHES |
114 | #define XCHAL_HAVE_WIDE_BRANCHES 0 | |
115 | ||
43cd72b9 BW |
116 | #undef XCHAL_HAVE_PREDICTED_BRANCHES |
117 | #define XCHAL_HAVE_PREDICTED_BRANCHES 0 | |
118 | ||
05235f71 BW |
119 | |
120 | #undef XCHAL_ICACHE_SIZE | |
33430bd0 | 121 | #define XCHAL_ICACHE_SIZE 16384 |
05235f71 BW |
122 | |
123 | #undef XCHAL_DCACHE_SIZE | |
33430bd0 | 124 | #define XCHAL_DCACHE_SIZE 16384 |
05235f71 BW |
125 | |
126 | #undef XCHAL_ICACHE_LINESIZE | |
33430bd0 | 127 | #define XCHAL_ICACHE_LINESIZE 32 |
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128 | |
129 | #undef XCHAL_DCACHE_LINESIZE | |
33430bd0 | 130 | #define XCHAL_DCACHE_LINESIZE 32 |
05235f71 BW |
131 | |
132 | #undef XCHAL_ICACHE_LINEWIDTH | |
33430bd0 | 133 | #define XCHAL_ICACHE_LINEWIDTH 5 |
05235f71 BW |
134 | |
135 | #undef XCHAL_DCACHE_LINEWIDTH | |
33430bd0 | 136 | #define XCHAL_DCACHE_LINEWIDTH 5 |
05235f71 BW |
137 | |
138 | #undef XCHAL_DCACHE_IS_WRITEBACK | |
33430bd0 | 139 | #define XCHAL_DCACHE_IS_WRITEBACK 1 |
e0001a05 | 140 | |
05235f71 BW |
141 | |
142 | #undef XCHAL_HAVE_MMU | |
e0001a05 | 143 | #define XCHAL_HAVE_MMU 1 |
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144 | |
145 | #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE | |
e0001a05 NC |
146 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 |
147 | ||
05235f71 BW |
148 | |
149 | #undef XCHAL_HAVE_DEBUG | |
e0001a05 | 150 | #define XCHAL_HAVE_DEBUG 1 |
05235f71 BW |
151 | |
152 | #undef XCHAL_NUM_IBREAK | |
e0001a05 | 153 | #define XCHAL_NUM_IBREAK 2 |
05235f71 BW |
154 | |
155 | #undef XCHAL_NUM_DBREAK | |
e0001a05 | 156 | #define XCHAL_NUM_DBREAK 2 |
05235f71 BW |
157 | |
158 | #undef XCHAL_DEBUGLEVEL | |
33430bd0 | 159 | #define XCHAL_DEBUGLEVEL 6 |
e0001a05 | 160 | |
05235f71 | 161 | |
6c7d412c BW |
162 | #undef XCHAL_MAX_INSTRUCTION_SIZE |
163 | #define XCHAL_MAX_INSTRUCTION_SIZE 3 | |
164 | ||
43cd72b9 BW |
165 | #undef XCHAL_INST_FETCH_WIDTH |
166 | #define XCHAL_INST_FETCH_WIDTH 4 | |
e0001a05 | 167 | |
2caa7ca0 BW |
168 | |
169 | #undef XSHAL_ABI | |
170 | #undef XTHAL_ABI_WINDOWED | |
171 | #undef XTHAL_ABI_CALL0 | |
172 | #define XSHAL_ABI XTHAL_ABI_WINDOWED | |
173 | #define XTHAL_ABI_WINDOWED 0 | |
174 | #define XTHAL_ABI_CALL0 1 | |
175 | ||
e0001a05 | 176 | #endif /* !XTENSA_CONFIG_H */ |