include/
[deliverable/binutils-gdb.git] / include / xtensa-config.h
CommitLineData
e0001a05 1/* Xtensa configuration settings.
33430bd0 2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
2caa7ca0 3 Free Software Foundation, Inc.
e0001a05
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4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5
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6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
e0001a05 10
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11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
e0001a05 15
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16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
e172dbf8 18 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
e0001a05
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19
20#ifndef XTENSA_CONFIG_H
21#define XTENSA_CONFIG_H
22
23/* The macros defined here match those with the same names in the Xtensa
24 compile-time HAL (Hardware Abstraction Layer). Please refer to the
25 Xtensa System Software Reference Manual for documentation of these
26 macros. */
27
05235f71 28#undef XCHAL_HAVE_BE
e0001a05 29#define XCHAL_HAVE_BE 1
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30
31#undef XCHAL_HAVE_DENSITY
e0001a05 32#define XCHAL_HAVE_DENSITY 1
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33
34#undef XCHAL_HAVE_CONST16
902695bc 35#define XCHAL_HAVE_CONST16 0
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36
37#undef XCHAL_HAVE_ABS
902695bc 38#define XCHAL_HAVE_ABS 1
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39
40#undef XCHAL_HAVE_ADDX
902695bc 41#define XCHAL_HAVE_ADDX 1
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42
43#undef XCHAL_HAVE_L32R
902695bc 44#define XCHAL_HAVE_L32R 1
05235f71 45
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46#undef XSHAL_USE_ABSOLUTE_LITERALS
47#define XSHAL_USE_ABSOLUTE_LITERALS 0
48
05235f71 49#undef XCHAL_HAVE_MAC16
e0001a05 50#define XCHAL_HAVE_MAC16 0
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51
52#undef XCHAL_HAVE_MUL16
33430bd0 53#define XCHAL_HAVE_MUL16 1
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54
55#undef XCHAL_HAVE_MUL32
33430bd0 56#define XCHAL_HAVE_MUL32 1
05235f71 57
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58#undef XCHAL_HAVE_MUL32_HIGH
59#define XCHAL_HAVE_MUL32_HIGH 0
60
05235f71 61#undef XCHAL_HAVE_DIV32
33430bd0 62#define XCHAL_HAVE_DIV32 1
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63
64#undef XCHAL_HAVE_NSA
e0001a05 65#define XCHAL_HAVE_NSA 1
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66
67#undef XCHAL_HAVE_MINMAX
33430bd0 68#define XCHAL_HAVE_MINMAX 1
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69
70#undef XCHAL_HAVE_SEXT
33430bd0 71#define XCHAL_HAVE_SEXT 1
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72
73#undef XCHAL_HAVE_LOOPS
e0001a05 74#define XCHAL_HAVE_LOOPS 1
05235f71 75
0a05a876 76#undef XCHAL_HAVE_THREADPTR
33430bd0 77#define XCHAL_HAVE_THREADPTR 1
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78
79#undef XCHAL_HAVE_RELEASE_SYNC
33430bd0 80#define XCHAL_HAVE_RELEASE_SYNC 1
0a05a876
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81
82#undef XCHAL_HAVE_S32C1I
33430bd0 83#define XCHAL_HAVE_S32C1I 1
0a05a876 84
05235f71 85#undef XCHAL_HAVE_BOOLEANS
e0001a05 86#define XCHAL_HAVE_BOOLEANS 0
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87
88#undef XCHAL_HAVE_FP
e0001a05 89#define XCHAL_HAVE_FP 0
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90
91#undef XCHAL_HAVE_FP_DIV
e0001a05 92#define XCHAL_HAVE_FP_DIV 0
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93
94#undef XCHAL_HAVE_FP_RECIP
e0001a05 95#define XCHAL_HAVE_FP_RECIP 0
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96
97#undef XCHAL_HAVE_FP_SQRT
e0001a05 98#define XCHAL_HAVE_FP_SQRT 0
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99
100#undef XCHAL_HAVE_FP_RSQRT
e0001a05 101#define XCHAL_HAVE_FP_RSQRT 0
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102
103#undef XCHAL_HAVE_WINDOWED
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104#define XCHAL_HAVE_WINDOWED 1
105
6c7d412c 106#undef XCHAL_NUM_AREGS
33430bd0 107#define XCHAL_NUM_AREGS 32
6c7d412c 108
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109#undef XCHAL_HAVE_WIDE_BRANCHES
110#define XCHAL_HAVE_WIDE_BRANCHES 0
111
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112#undef XCHAL_HAVE_PREDICTED_BRANCHES
113#define XCHAL_HAVE_PREDICTED_BRANCHES 0
114
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115
116#undef XCHAL_ICACHE_SIZE
33430bd0 117#define XCHAL_ICACHE_SIZE 16384
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118
119#undef XCHAL_DCACHE_SIZE
33430bd0 120#define XCHAL_DCACHE_SIZE 16384
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121
122#undef XCHAL_ICACHE_LINESIZE
33430bd0 123#define XCHAL_ICACHE_LINESIZE 32
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124
125#undef XCHAL_DCACHE_LINESIZE
33430bd0 126#define XCHAL_DCACHE_LINESIZE 32
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127
128#undef XCHAL_ICACHE_LINEWIDTH
33430bd0 129#define XCHAL_ICACHE_LINEWIDTH 5
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130
131#undef XCHAL_DCACHE_LINEWIDTH
33430bd0 132#define XCHAL_DCACHE_LINEWIDTH 5
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133
134#undef XCHAL_DCACHE_IS_WRITEBACK
33430bd0 135#define XCHAL_DCACHE_IS_WRITEBACK 1
e0001a05 136
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137
138#undef XCHAL_HAVE_MMU
e0001a05 139#define XCHAL_HAVE_MMU 1
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140
141#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
e0001a05
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142#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
143
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144
145#undef XCHAL_HAVE_DEBUG
e0001a05 146#define XCHAL_HAVE_DEBUG 1
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147
148#undef XCHAL_NUM_IBREAK
e0001a05 149#define XCHAL_NUM_IBREAK 2
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150
151#undef XCHAL_NUM_DBREAK
e0001a05 152#define XCHAL_NUM_DBREAK 2
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153
154#undef XCHAL_DEBUGLEVEL
33430bd0 155#define XCHAL_DEBUGLEVEL 6
e0001a05 156
05235f71 157
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158#undef XCHAL_MAX_INSTRUCTION_SIZE
159#define XCHAL_MAX_INSTRUCTION_SIZE 3
160
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161#undef XCHAL_INST_FETCH_WIDTH
162#define XCHAL_INST_FETCH_WIDTH 4
e0001a05 163
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164
165#undef XSHAL_ABI
166#undef XTHAL_ABI_WINDOWED
167#undef XTHAL_ABI_CALL0
168#define XSHAL_ABI XTHAL_ABI_WINDOWED
169#define XTHAL_ABI_WINDOWED 0
170#define XTHAL_ABI_CALL0 1
171
e0001a05 172#endif /* !XTENSA_CONFIG_H */
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