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1 | /* Xtensa configuration settings. |
2 | Copyright (C) 2003 Free Software Foundation, Inc. | |
3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. | |
4 | ||
5 | ** NOTE: This file was automatically generated by the Xtensa Processor | |
6 | ** Generator. Changes made here will be lost when this file is | |
7 | ** updated or replaced with the settings for a different Xtensa | |
8 | ** processor configuration. DO NOT EDIT! | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, but | |
16 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | */ | |
24 | ||
25 | #ifndef XTENSA_CONFIG_H | |
26 | #define XTENSA_CONFIG_H | |
27 | ||
28 | /* The macros defined here match those with the same names in the Xtensa | |
29 | compile-time HAL (Hardware Abstraction Layer). Please refer to the | |
30 | Xtensa System Software Reference Manual for documentation of these | |
31 | macros. */ | |
32 | ||
33 | #define XCHAL_HAVE_BE 1 | |
34 | #define XCHAL_HAVE_DENSITY 1 | |
35 | #define XCHAL_HAVE_MAC16 0 | |
36 | #define XCHAL_HAVE_MUL16 0 | |
37 | #define XCHAL_HAVE_MUL32 0 | |
38 | #define XCHAL_HAVE_DIV32 0 | |
39 | #define XCHAL_HAVE_NSA 1 | |
40 | #define XCHAL_HAVE_MINMAX 0 | |
41 | #define XCHAL_HAVE_SEXT 0 | |
42 | #define XCHAL_HAVE_LOOPS 1 | |
43 | #define XCHAL_HAVE_BOOLEANS 0 | |
44 | #define XCHAL_HAVE_FP 0 | |
45 | #define XCHAL_HAVE_FP_DIV 0 | |
46 | #define XCHAL_HAVE_FP_RECIP 0 | |
47 | #define XCHAL_HAVE_FP_SQRT 0 | |
48 | #define XCHAL_HAVE_FP_RSQRT 0 | |
49 | #define XCHAL_HAVE_WINDOWED 1 | |
50 | ||
51 | #define XCHAL_ICACHE_SIZE 8192 | |
52 | #define XCHAL_DCACHE_SIZE 8192 | |
53 | #define XCHAL_ICACHE_LINESIZE 16 | |
54 | #define XCHAL_DCACHE_LINESIZE 16 | |
55 | #define XCHAL_ICACHE_LINEWIDTH 4 | |
56 | #define XCHAL_DCACHE_LINEWIDTH 4 | |
57 | #define XCHAL_DCACHE_IS_WRITEBACK 0 | |
58 | ||
59 | #define XCHAL_HAVE_MMU 1 | |
60 | #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 | |
61 | ||
62 | #define XCHAL_HAVE_DEBUG 1 | |
63 | #define XCHAL_NUM_IBREAK 2 | |
64 | #define XCHAL_NUM_DBREAK 2 | |
65 | #define XCHAL_DEBUGLEVEL 4 | |
66 | ||
67 | #define XCHAL_EXTRA_SA_SIZE 0 | |
68 | #define XCHAL_EXTRA_SA_ALIGN 1 | |
69 | ||
70 | #endif /* !XTENSA_CONFIG_H */ |