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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel_stat.h> | |
17 | ||
18 | #include "internals.h" | |
19 | ||
3a16d713 EB |
20 | /** |
21 | * dynamic_irq_init - initialize a dynamically allocated irq | |
22 | * @irq: irq number to initialize | |
23 | */ | |
24 | void dynamic_irq_init(unsigned int irq) | |
25 | { | |
26 | struct irq_desc *desc; | |
27 | unsigned long flags; | |
28 | ||
29 | if (irq >= NR_IRQS) { | |
30 | printk(KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); | |
31 | WARN_ON(1); | |
32 | return; | |
33 | } | |
34 | ||
35 | /* Ensure we don't have left over values from a previous use of this irq */ | |
36 | desc = irq_desc + irq; | |
37 | spin_lock_irqsave(&desc->lock, flags); | |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
42 | desc->handler_data = NULL; | |
43 | desc->chip_data = NULL; | |
44 | desc->action = NULL; | |
45 | desc->irq_count = 0; | |
46 | desc->irqs_unhandled = 0; | |
47 | #ifdef CONFIG_SMP | |
48 | desc->affinity = CPU_MASK_ALL; | |
49 | #endif | |
50 | spin_unlock_irqrestore(&desc->lock, flags); | |
51 | } | |
52 | ||
53 | /** | |
54 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
55 | * @irq: irq number to initialize | |
56 | */ | |
57 | void dynamic_irq_cleanup(unsigned int irq) | |
58 | { | |
59 | struct irq_desc *desc; | |
60 | unsigned long flags; | |
61 | ||
62 | if (irq >= NR_IRQS) { | |
63 | printk(KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); | |
64 | WARN_ON(1); | |
65 | return; | |
66 | } | |
67 | ||
68 | desc = irq_desc + irq; | |
69 | spin_lock_irqsave(&desc->lock, flags); | |
70 | desc->handle_irq = handle_bad_irq; | |
71 | desc->chip = &no_irq_chip; | |
72 | spin_unlock_irqrestore(&desc->lock, flags); | |
73 | } | |
74 | ||
75 | ||
dd87eb3a TG |
76 | /** |
77 | * set_irq_chip - set the irq chip for an irq | |
78 | * @irq: irq number | |
79 | * @chip: pointer to irq chip description structure | |
80 | */ | |
81 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
82 | { | |
83 | struct irq_desc *desc; | |
84 | unsigned long flags; | |
85 | ||
86 | if (irq >= NR_IRQS) { | |
87 | printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq); | |
88 | WARN_ON(1); | |
89 | return -EINVAL; | |
90 | } | |
91 | ||
92 | if (!chip) | |
93 | chip = &no_irq_chip; | |
94 | ||
95 | desc = irq_desc + irq; | |
96 | spin_lock_irqsave(&desc->lock, flags); | |
97 | irq_chip_set_defaults(chip); | |
98 | desc->chip = chip; | |
dd87eb3a TG |
99 | spin_unlock_irqrestore(&desc->lock, flags); |
100 | ||
101 | return 0; | |
102 | } | |
103 | EXPORT_SYMBOL(set_irq_chip); | |
104 | ||
105 | /** | |
106 | * set_irq_type - set the irq type for an irq | |
107 | * @irq: irq number | |
108 | * @type: interrupt type - see include/linux/interrupt.h | |
109 | */ | |
110 | int set_irq_type(unsigned int irq, unsigned int type) | |
111 | { | |
112 | struct irq_desc *desc; | |
113 | unsigned long flags; | |
114 | int ret = -ENXIO; | |
115 | ||
116 | if (irq >= NR_IRQS) { | |
117 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); | |
118 | return -ENODEV; | |
119 | } | |
120 | ||
121 | desc = irq_desc + irq; | |
122 | if (desc->chip->set_type) { | |
123 | spin_lock_irqsave(&desc->lock, flags); | |
124 | ret = desc->chip->set_type(irq, type); | |
125 | spin_unlock_irqrestore(&desc->lock, flags); | |
126 | } | |
127 | return ret; | |
128 | } | |
129 | EXPORT_SYMBOL(set_irq_type); | |
130 | ||
131 | /** | |
132 | * set_irq_data - set irq type data for an irq | |
133 | * @irq: Interrupt number | |
134 | * @data: Pointer to interrupt specific data | |
135 | * | |
136 | * Set the hardware irq controller data for an irq | |
137 | */ | |
138 | int set_irq_data(unsigned int irq, void *data) | |
139 | { | |
140 | struct irq_desc *desc; | |
141 | unsigned long flags; | |
142 | ||
143 | if (irq >= NR_IRQS) { | |
144 | printk(KERN_ERR | |
145 | "Trying to install controller data for IRQ%d\n", irq); | |
146 | return -EINVAL; | |
147 | } | |
148 | ||
149 | desc = irq_desc + irq; | |
150 | spin_lock_irqsave(&desc->lock, flags); | |
151 | desc->handler_data = data; | |
152 | spin_unlock_irqrestore(&desc->lock, flags); | |
153 | return 0; | |
154 | } | |
155 | EXPORT_SYMBOL(set_irq_data); | |
156 | ||
157 | /** | |
158 | * set_irq_chip_data - set irq chip data for an irq | |
159 | * @irq: Interrupt number | |
160 | * @data: Pointer to chip specific data | |
161 | * | |
162 | * Set the hardware irq chip data for an irq | |
163 | */ | |
164 | int set_irq_chip_data(unsigned int irq, void *data) | |
165 | { | |
166 | struct irq_desc *desc = irq_desc + irq; | |
167 | unsigned long flags; | |
168 | ||
169 | if (irq >= NR_IRQS || !desc->chip) { | |
170 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | spin_lock_irqsave(&desc->lock, flags); | |
175 | desc->chip_data = data; | |
176 | spin_unlock_irqrestore(&desc->lock, flags); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | EXPORT_SYMBOL(set_irq_chip_data); | |
181 | ||
182 | /* | |
183 | * default enable function | |
184 | */ | |
185 | static void default_enable(unsigned int irq) | |
186 | { | |
187 | struct irq_desc *desc = irq_desc + irq; | |
188 | ||
189 | desc->chip->unmask(irq); | |
190 | desc->status &= ~IRQ_MASKED; | |
191 | } | |
192 | ||
193 | /* | |
194 | * default disable function | |
195 | */ | |
196 | static void default_disable(unsigned int irq) | |
197 | { | |
198 | struct irq_desc *desc = irq_desc + irq; | |
199 | ||
200 | if (!(desc->status & IRQ_DELAYED_DISABLE)) | |
2ff6fd8f | 201 | desc->chip->mask(irq); |
dd87eb3a TG |
202 | } |
203 | ||
204 | /* | |
205 | * default startup function | |
206 | */ | |
207 | static unsigned int default_startup(unsigned int irq) | |
208 | { | |
209 | irq_desc[irq].chip->enable(irq); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | /* | |
215 | * Fixup enable/disable function pointers | |
216 | */ | |
217 | void irq_chip_set_defaults(struct irq_chip *chip) | |
218 | { | |
219 | if (!chip->enable) | |
220 | chip->enable = default_enable; | |
221 | if (!chip->disable) | |
222 | chip->disable = default_disable; | |
223 | if (!chip->startup) | |
224 | chip->startup = default_startup; | |
225 | if (!chip->shutdown) | |
226 | chip->shutdown = chip->disable; | |
227 | if (!chip->name) | |
228 | chip->name = chip->typename; | |
229 | } | |
230 | ||
231 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
232 | { | |
233 | if (desc->chip->mask_ack) | |
234 | desc->chip->mask_ack(irq); | |
235 | else { | |
236 | desc->chip->mask(irq); | |
237 | desc->chip->ack(irq); | |
238 | } | |
239 | } | |
240 | ||
241 | /** | |
242 | * handle_simple_irq - Simple and software-decoded IRQs. | |
243 | * @irq: the interrupt number | |
244 | * @desc: the interrupt description structure for this irq | |
245 | * @regs: pointer to a register structure | |
246 | * | |
247 | * Simple interrupts are either sent from a demultiplexing interrupt | |
248 | * handler or come from hardware, where no interrupt hardware control | |
249 | * is necessary. | |
250 | * | |
251 | * Note: The caller is expected to handle the ack, clear, mask and | |
252 | * unmask issues if necessary. | |
253 | */ | |
254 | void fastcall | |
255 | handle_simple_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | |
256 | { | |
257 | struct irqaction *action; | |
258 | irqreturn_t action_ret; | |
259 | const unsigned int cpu = smp_processor_id(); | |
260 | ||
261 | spin_lock(&desc->lock); | |
262 | ||
263 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
264 | goto out_unlock; | |
265 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
266 | kstat_cpu(cpu).irqs[irq]++; | |
267 | ||
268 | action = desc->action; | |
269 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
270 | goto out_unlock; | |
271 | ||
272 | desc->status |= IRQ_INPROGRESS; | |
273 | spin_unlock(&desc->lock); | |
274 | ||
275 | action_ret = handle_IRQ_event(irq, regs, action); | |
276 | if (!noirqdebug) | |
277 | note_interrupt(irq, desc, action_ret, regs); | |
278 | ||
279 | spin_lock(&desc->lock); | |
280 | desc->status &= ~IRQ_INPROGRESS; | |
281 | out_unlock: | |
282 | spin_unlock(&desc->lock); | |
283 | } | |
284 | ||
285 | /** | |
286 | * handle_level_irq - Level type irq handler | |
287 | * @irq: the interrupt number | |
288 | * @desc: the interrupt description structure for this irq | |
289 | * @regs: pointer to a register structure | |
290 | * | |
291 | * Level type interrupts are active as long as the hardware line has | |
292 | * the active level. This may require to mask the interrupt and unmask | |
293 | * it after the associated handler has acknowledged the device, so the | |
294 | * interrupt line is back to inactive. | |
295 | */ | |
296 | void fastcall | |
297 | handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | |
298 | { | |
299 | unsigned int cpu = smp_processor_id(); | |
300 | struct irqaction *action; | |
301 | irqreturn_t action_ret; | |
302 | ||
303 | spin_lock(&desc->lock); | |
304 | mask_ack_irq(desc, irq); | |
305 | ||
306 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 307 | goto out_unlock; |
dd87eb3a TG |
308 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
309 | kstat_cpu(cpu).irqs[irq]++; | |
310 | ||
311 | /* | |
312 | * If its disabled or no action available | |
313 | * keep it masked and get out of here | |
314 | */ | |
315 | action = desc->action; | |
5a43a066 BH |
316 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
317 | desc->status |= IRQ_PENDING; | |
86998aa6 | 318 | goto out_unlock; |
5a43a066 | 319 | } |
dd87eb3a TG |
320 | |
321 | desc->status |= IRQ_INPROGRESS; | |
5a43a066 | 322 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
323 | spin_unlock(&desc->lock); |
324 | ||
325 | action_ret = handle_IRQ_event(irq, regs, action); | |
326 | if (!noirqdebug) | |
327 | note_interrupt(irq, desc, action_ret, regs); | |
328 | ||
329 | spin_lock(&desc->lock); | |
330 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
331 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
332 | desc->chip->unmask(irq); | |
86998aa6 | 333 | out_unlock: |
dd87eb3a TG |
334 | spin_unlock(&desc->lock); |
335 | } | |
336 | ||
337 | /** | |
47c2a3aa | 338 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
339 | * @irq: the interrupt number |
340 | * @desc: the interrupt description structure for this irq | |
341 | * @regs: pointer to a register structure | |
342 | * | |
47c2a3aa | 343 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
344 | * call when the interrupt has been serviced. This enables support |
345 | * for modern forms of interrupt handlers, which handle the flow | |
346 | * details in hardware, transparently. | |
347 | */ | |
348 | void fastcall | |
47c2a3aa | 349 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc, |
dd87eb3a TG |
350 | struct pt_regs *regs) |
351 | { | |
352 | unsigned int cpu = smp_processor_id(); | |
353 | struct irqaction *action; | |
354 | irqreturn_t action_ret; | |
355 | ||
356 | spin_lock(&desc->lock); | |
357 | ||
358 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
359 | goto out; | |
360 | ||
361 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
362 | kstat_cpu(cpu).irqs[irq]++; | |
363 | ||
364 | /* | |
365 | * If its disabled or no action available | |
366 | * keep it masked and get out of here | |
367 | */ | |
368 | action = desc->action; | |
98bb244b BH |
369 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
370 | desc->status |= IRQ_PENDING; | |
dd87eb3a | 371 | goto out; |
98bb244b | 372 | } |
dd87eb3a TG |
373 | |
374 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 375 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
376 | spin_unlock(&desc->lock); |
377 | ||
378 | action_ret = handle_IRQ_event(irq, regs, action); | |
379 | if (!noirqdebug) | |
380 | note_interrupt(irq, desc, action_ret, regs); | |
381 | ||
382 | spin_lock(&desc->lock); | |
383 | desc->status &= ~IRQ_INPROGRESS; | |
384 | out: | |
47c2a3aa | 385 | desc->chip->eoi(irq); |
dd87eb3a TG |
386 | |
387 | spin_unlock(&desc->lock); | |
388 | } | |
389 | ||
390 | /** | |
391 | * handle_edge_irq - edge type IRQ handler | |
392 | * @irq: the interrupt number | |
393 | * @desc: the interrupt description structure for this irq | |
394 | * @regs: pointer to a register structure | |
395 | * | |
396 | * Interrupt occures on the falling and/or rising edge of a hardware | |
397 | * signal. The occurence is latched into the irq controller hardware | |
398 | * and must be acked in order to be reenabled. After the ack another | |
399 | * interrupt can happen on the same source even before the first one | |
400 | * is handled by the assosiacted event handler. If this happens it | |
401 | * might be necessary to disable (mask) the interrupt depending on the | |
402 | * controller hardware. This requires to reenable the interrupt inside | |
403 | * of the loop which handles the interrupts which have arrived while | |
404 | * the handler was running. If all pending interrupts are handled, the | |
405 | * loop is left. | |
406 | */ | |
407 | void fastcall | |
408 | handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | |
409 | { | |
410 | const unsigned int cpu = smp_processor_id(); | |
411 | ||
412 | spin_lock(&desc->lock); | |
413 | ||
414 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
415 | ||
416 | /* | |
417 | * If we're currently running this IRQ, or its disabled, | |
418 | * we shouldn't process the IRQ. Mark it pending, handle | |
419 | * the necessary masking and go out | |
420 | */ | |
421 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
422 | !desc->action)) { | |
423 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
424 | mask_ack_irq(desc, irq); | |
425 | goto out_unlock; | |
426 | } | |
427 | ||
428 | kstat_cpu(cpu).irqs[irq]++; | |
429 | ||
430 | /* Start handling the irq */ | |
431 | desc->chip->ack(irq); | |
432 | ||
433 | /* Mark the IRQ currently in progress.*/ | |
434 | desc->status |= IRQ_INPROGRESS; | |
435 | ||
436 | do { | |
437 | struct irqaction *action = desc->action; | |
438 | irqreturn_t action_ret; | |
439 | ||
440 | if (unlikely(!action)) { | |
441 | desc->chip->mask(irq); | |
442 | goto out_unlock; | |
443 | } | |
444 | ||
445 | /* | |
446 | * When another irq arrived while we were handling | |
447 | * one, we could have masked the irq. | |
448 | * Renable it, if it was not disabled in meantime. | |
449 | */ | |
450 | if (unlikely((desc->status & | |
451 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
452 | (IRQ_PENDING | IRQ_MASKED))) { | |
453 | desc->chip->unmask(irq); | |
454 | desc->status &= ~IRQ_MASKED; | |
455 | } | |
456 | ||
457 | desc->status &= ~IRQ_PENDING; | |
458 | spin_unlock(&desc->lock); | |
459 | action_ret = handle_IRQ_event(irq, regs, action); | |
460 | if (!noirqdebug) | |
461 | note_interrupt(irq, desc, action_ret, regs); | |
462 | spin_lock(&desc->lock); | |
463 | ||
464 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
465 | ||
466 | desc->status &= ~IRQ_INPROGRESS; | |
467 | out_unlock: | |
468 | spin_unlock(&desc->lock); | |
469 | } | |
470 | ||
471 | #ifdef CONFIG_SMP | |
472 | /** | |
473 | * handle_percpu_IRQ - Per CPU local irq handler | |
474 | * @irq: the interrupt number | |
475 | * @desc: the interrupt description structure for this irq | |
476 | * @regs: pointer to a register structure | |
477 | * | |
478 | * Per CPU interrupts on SMP machines without locking requirements | |
479 | */ | |
480 | void fastcall | |
481 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | |
482 | { | |
483 | irqreturn_t action_ret; | |
484 | ||
485 | kstat_this_cpu.irqs[irq]++; | |
486 | ||
487 | if (desc->chip->ack) | |
488 | desc->chip->ack(irq); | |
489 | ||
490 | action_ret = handle_IRQ_event(irq, regs, desc->action); | |
491 | if (!noirqdebug) | |
492 | note_interrupt(irq, desc, action_ret, regs); | |
493 | ||
494 | if (desc->chip->eoi) | |
495 | desc->chip->eoi(irq); | |
496 | } | |
497 | ||
498 | #endif /* CONFIG_SMP */ | |
499 | ||
500 | void | |
501 | __set_irq_handler(unsigned int irq, | |
502 | void fastcall (*handle)(unsigned int, irq_desc_t *, | |
503 | struct pt_regs *), | |
504 | int is_chained) | |
505 | { | |
506 | struct irq_desc *desc; | |
507 | unsigned long flags; | |
508 | ||
509 | if (irq >= NR_IRQS) { | |
510 | printk(KERN_ERR | |
511 | "Trying to install type control for IRQ%d\n", irq); | |
512 | return; | |
513 | } | |
514 | ||
515 | desc = irq_desc + irq; | |
516 | ||
517 | if (!handle) | |
518 | handle = handle_bad_irq; | |
519 | ||
f8b5473f TG |
520 | if (desc->chip == &no_irq_chip) { |
521 | printk(KERN_WARNING "Trying to install %sinterrupt handler " | |
522 | "for IRQ%d\n", is_chained ? "chained " : " ", irq); | |
523 | /* | |
524 | * Some ARM implementations install a handler for really dumb | |
525 | * interrupt hardware without setting an irq_chip. This worked | |
526 | * with the ARM no_irq_chip but the check in setup_irq would | |
527 | * prevent us to setup the interrupt at all. Switch it to | |
528 | * dummy_irq_chip for easy transition. | |
529 | */ | |
530 | desc->chip = &dummy_irq_chip; | |
531 | } | |
dd87eb3a TG |
532 | |
533 | spin_lock_irqsave(&desc->lock, flags); | |
534 | ||
535 | /* Uninstall? */ | |
536 | if (handle == handle_bad_irq) { | |
537 | if (desc->chip != &no_irq_chip) { | |
538 | desc->chip->mask(irq); | |
539 | desc->chip->ack(irq); | |
540 | } | |
541 | desc->status |= IRQ_DISABLED; | |
542 | desc->depth = 1; | |
543 | } | |
544 | desc->handle_irq = handle; | |
545 | ||
546 | if (handle != handle_bad_irq && is_chained) { | |
547 | desc->status &= ~IRQ_DISABLED; | |
548 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
549 | desc->depth = 0; | |
550 | desc->chip->unmask(irq); | |
551 | } | |
552 | spin_unlock_irqrestore(&desc->lock, flags); | |
553 | } | |
554 | ||
555 | void | |
556 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
557 | void fastcall (*handle)(unsigned int, | |
558 | struct irq_desc *, | |
559 | struct pt_regs *)) | |
560 | { | |
561 | set_irq_chip(irq, chip); | |
562 | __set_irq_handler(irq, handle, 0); | |
563 | } | |
564 | ||
565 | /* | |
566 | * Get a descriptive string for the highlevel handler, for | |
567 | * /proc/interrupts output: | |
568 | */ | |
569 | const char * | |
570 | handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *, | |
571 | struct pt_regs *)) | |
572 | { | |
573 | if (handle == handle_level_irq) | |
47c2a3aa IM |
574 | return "level "; |
575 | if (handle == handle_fasteoi_irq) | |
576 | return "fasteoi"; | |
dd87eb3a | 577 | if (handle == handle_edge_irq) |
47c2a3aa | 578 | return "edge "; |
dd87eb3a | 579 | if (handle == handle_simple_irq) |
47c2a3aa | 580 | return "simple "; |
dd87eb3a TG |
581 | #ifdef CONFIG_SMP |
582 | if (handle == handle_percpu_irq) | |
47c2a3aa | 583 | return "percpu "; |
dd87eb3a TG |
584 | #endif |
585 | if (handle == handle_bad_irq) | |
47c2a3aa | 586 | return "bad "; |
dd87eb3a TG |
587 | |
588 | return NULL; | |
589 | } |