Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel_stat.h> | |
17 | ||
18 | #include "internals.h" | |
19 | ||
3a16d713 EB |
20 | /** |
21 | * dynamic_irq_init - initialize a dynamically allocated irq | |
22 | * @irq: irq number to initialize | |
23 | */ | |
24 | void dynamic_irq_init(unsigned int irq) | |
25 | { | |
26 | struct irq_desc *desc; | |
27 | unsigned long flags; | |
28 | ||
29 | if (irq >= NR_IRQS) { | |
30 | printk(KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); | |
31 | WARN_ON(1); | |
32 | return; | |
33 | } | |
34 | ||
35 | /* Ensure we don't have left over values from a previous use of this irq */ | |
36 | desc = irq_desc + irq; | |
37 | spin_lock_irqsave(&desc->lock, flags); | |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
5b912c10 | 42 | desc->msi_desc = NULL; |
3a16d713 EB |
43 | desc->handler_data = NULL; |
44 | desc->chip_data = NULL; | |
45 | desc->action = NULL; | |
46 | desc->irq_count = 0; | |
47 | desc->irqs_unhandled = 0; | |
48 | #ifdef CONFIG_SMP | |
49 | desc->affinity = CPU_MASK_ALL; | |
50 | #endif | |
51 | spin_unlock_irqrestore(&desc->lock, flags); | |
52 | } | |
53 | ||
54 | /** | |
55 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
56 | * @irq: irq number to initialize | |
57 | */ | |
58 | void dynamic_irq_cleanup(unsigned int irq) | |
59 | { | |
60 | struct irq_desc *desc; | |
61 | unsigned long flags; | |
62 | ||
63 | if (irq >= NR_IRQS) { | |
64 | printk(KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); | |
65 | WARN_ON(1); | |
66 | return; | |
67 | } | |
68 | ||
69 | desc = irq_desc + irq; | |
70 | spin_lock_irqsave(&desc->lock, flags); | |
1f80025e EB |
71 | if (desc->action) { |
72 | spin_unlock_irqrestore(&desc->lock, flags); | |
73 | printk(KERN_ERR "Destroying IRQ%d without calling free_irq\n", | |
74 | irq); | |
75 | WARN_ON(1); | |
76 | return; | |
77 | } | |
5b912c10 EB |
78 | desc->msi_desc = NULL; |
79 | desc->handler_data = NULL; | |
80 | desc->chip_data = NULL; | |
3a16d713 EB |
81 | desc->handle_irq = handle_bad_irq; |
82 | desc->chip = &no_irq_chip; | |
83 | spin_unlock_irqrestore(&desc->lock, flags); | |
84 | } | |
85 | ||
86 | ||
dd87eb3a TG |
87 | /** |
88 | * set_irq_chip - set the irq chip for an irq | |
89 | * @irq: irq number | |
90 | * @chip: pointer to irq chip description structure | |
91 | */ | |
92 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
93 | { | |
94 | struct irq_desc *desc; | |
95 | unsigned long flags; | |
96 | ||
97 | if (irq >= NR_IRQS) { | |
98 | printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq); | |
99 | WARN_ON(1); | |
100 | return -EINVAL; | |
101 | } | |
102 | ||
103 | if (!chip) | |
104 | chip = &no_irq_chip; | |
105 | ||
106 | desc = irq_desc + irq; | |
107 | spin_lock_irqsave(&desc->lock, flags); | |
108 | irq_chip_set_defaults(chip); | |
109 | desc->chip = chip; | |
dd87eb3a TG |
110 | spin_unlock_irqrestore(&desc->lock, flags); |
111 | ||
112 | return 0; | |
113 | } | |
114 | EXPORT_SYMBOL(set_irq_chip); | |
115 | ||
116 | /** | |
117 | * set_irq_type - set the irq type for an irq | |
118 | * @irq: irq number | |
119 | * @type: interrupt type - see include/linux/interrupt.h | |
120 | */ | |
121 | int set_irq_type(unsigned int irq, unsigned int type) | |
122 | { | |
123 | struct irq_desc *desc; | |
124 | unsigned long flags; | |
125 | int ret = -ENXIO; | |
126 | ||
127 | if (irq >= NR_IRQS) { | |
128 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); | |
129 | return -ENODEV; | |
130 | } | |
131 | ||
132 | desc = irq_desc + irq; | |
133 | if (desc->chip->set_type) { | |
134 | spin_lock_irqsave(&desc->lock, flags); | |
135 | ret = desc->chip->set_type(irq, type); | |
136 | spin_unlock_irqrestore(&desc->lock, flags); | |
137 | } | |
138 | return ret; | |
139 | } | |
140 | EXPORT_SYMBOL(set_irq_type); | |
141 | ||
142 | /** | |
143 | * set_irq_data - set irq type data for an irq | |
144 | * @irq: Interrupt number | |
145 | * @data: Pointer to interrupt specific data | |
146 | * | |
147 | * Set the hardware irq controller data for an irq | |
148 | */ | |
149 | int set_irq_data(unsigned int irq, void *data) | |
150 | { | |
151 | struct irq_desc *desc; | |
152 | unsigned long flags; | |
153 | ||
154 | if (irq >= NR_IRQS) { | |
155 | printk(KERN_ERR | |
156 | "Trying to install controller data for IRQ%d\n", irq); | |
157 | return -EINVAL; | |
158 | } | |
159 | ||
160 | desc = irq_desc + irq; | |
161 | spin_lock_irqsave(&desc->lock, flags); | |
162 | desc->handler_data = data; | |
163 | spin_unlock_irqrestore(&desc->lock, flags); | |
164 | return 0; | |
165 | } | |
166 | EXPORT_SYMBOL(set_irq_data); | |
167 | ||
5b912c10 EB |
168 | /** |
169 | * set_irq_data - set irq type data for an irq | |
170 | * @irq: Interrupt number | |
171 | * @data: Pointer to interrupt specific data | |
172 | * | |
173 | * Set the hardware irq controller data for an irq | |
174 | */ | |
175 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
176 | { | |
177 | struct irq_desc *desc; | |
178 | unsigned long flags; | |
179 | ||
180 | if (irq >= NR_IRQS) { | |
181 | printk(KERN_ERR | |
182 | "Trying to install msi data for IRQ%d\n", irq); | |
183 | return -EINVAL; | |
184 | } | |
185 | desc = irq_desc + irq; | |
186 | spin_lock_irqsave(&desc->lock, flags); | |
187 | desc->msi_desc = entry; | |
188 | spin_unlock_irqrestore(&desc->lock, flags); | |
189 | return 0; | |
190 | } | |
191 | ||
dd87eb3a TG |
192 | /** |
193 | * set_irq_chip_data - set irq chip data for an irq | |
194 | * @irq: Interrupt number | |
195 | * @data: Pointer to chip specific data | |
196 | * | |
197 | * Set the hardware irq chip data for an irq | |
198 | */ | |
199 | int set_irq_chip_data(unsigned int irq, void *data) | |
200 | { | |
201 | struct irq_desc *desc = irq_desc + irq; | |
202 | unsigned long flags; | |
203 | ||
204 | if (irq >= NR_IRQS || !desc->chip) { | |
205 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); | |
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | spin_lock_irqsave(&desc->lock, flags); | |
210 | desc->chip_data = data; | |
211 | spin_unlock_irqrestore(&desc->lock, flags); | |
212 | ||
213 | return 0; | |
214 | } | |
215 | EXPORT_SYMBOL(set_irq_chip_data); | |
216 | ||
217 | /* | |
218 | * default enable function | |
219 | */ | |
220 | static void default_enable(unsigned int irq) | |
221 | { | |
222 | struct irq_desc *desc = irq_desc + irq; | |
223 | ||
224 | desc->chip->unmask(irq); | |
225 | desc->status &= ~IRQ_MASKED; | |
226 | } | |
227 | ||
228 | /* | |
229 | * default disable function | |
230 | */ | |
231 | static void default_disable(unsigned int irq) | |
232 | { | |
233 | struct irq_desc *desc = irq_desc + irq; | |
234 | ||
235 | if (!(desc->status & IRQ_DELAYED_DISABLE)) | |
2ff6fd8f | 236 | desc->chip->mask(irq); |
dd87eb3a TG |
237 | } |
238 | ||
239 | /* | |
240 | * default startup function | |
241 | */ | |
242 | static unsigned int default_startup(unsigned int irq) | |
243 | { | |
244 | irq_desc[irq].chip->enable(irq); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | /* | |
250 | * Fixup enable/disable function pointers | |
251 | */ | |
252 | void irq_chip_set_defaults(struct irq_chip *chip) | |
253 | { | |
254 | if (!chip->enable) | |
255 | chip->enable = default_enable; | |
256 | if (!chip->disable) | |
257 | chip->disable = default_disable; | |
258 | if (!chip->startup) | |
259 | chip->startup = default_startup; | |
260 | if (!chip->shutdown) | |
261 | chip->shutdown = chip->disable; | |
262 | if (!chip->name) | |
263 | chip->name = chip->typename; | |
b86432b4 ZY |
264 | if (!chip->end) |
265 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
266 | } |
267 | ||
268 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
269 | { | |
270 | if (desc->chip->mask_ack) | |
271 | desc->chip->mask_ack(irq); | |
272 | else { | |
273 | desc->chip->mask(irq); | |
274 | desc->chip->ack(irq); | |
275 | } | |
276 | } | |
277 | ||
278 | /** | |
279 | * handle_simple_irq - Simple and software-decoded IRQs. | |
280 | * @irq: the interrupt number | |
281 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
282 | * |
283 | * Simple interrupts are either sent from a demultiplexing interrupt | |
284 | * handler or come from hardware, where no interrupt hardware control | |
285 | * is necessary. | |
286 | * | |
287 | * Note: The caller is expected to handle the ack, clear, mask and | |
288 | * unmask issues if necessary. | |
289 | */ | |
290 | void fastcall | |
7d12e780 | 291 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
292 | { |
293 | struct irqaction *action; | |
294 | irqreturn_t action_ret; | |
295 | const unsigned int cpu = smp_processor_id(); | |
296 | ||
297 | spin_lock(&desc->lock); | |
298 | ||
299 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
300 | goto out_unlock; | |
301 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
302 | kstat_cpu(cpu).irqs[irq]++; | |
303 | ||
304 | action = desc->action; | |
305 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
306 | goto out_unlock; | |
307 | ||
308 | desc->status |= IRQ_INPROGRESS; | |
309 | spin_unlock(&desc->lock); | |
310 | ||
7d12e780 | 311 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 312 | if (!noirqdebug) |
7d12e780 | 313 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
314 | |
315 | spin_lock(&desc->lock); | |
316 | desc->status &= ~IRQ_INPROGRESS; | |
317 | out_unlock: | |
318 | spin_unlock(&desc->lock); | |
319 | } | |
320 | ||
321 | /** | |
322 | * handle_level_irq - Level type irq handler | |
323 | * @irq: the interrupt number | |
324 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
325 | * |
326 | * Level type interrupts are active as long as the hardware line has | |
327 | * the active level. This may require to mask the interrupt and unmask | |
328 | * it after the associated handler has acknowledged the device, so the | |
329 | * interrupt line is back to inactive. | |
330 | */ | |
331 | void fastcall | |
7d12e780 | 332 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
333 | { |
334 | unsigned int cpu = smp_processor_id(); | |
335 | struct irqaction *action; | |
336 | irqreturn_t action_ret; | |
337 | ||
338 | spin_lock(&desc->lock); | |
339 | mask_ack_irq(desc, irq); | |
340 | ||
341 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 342 | goto out_unlock; |
dd87eb3a TG |
343 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
344 | kstat_cpu(cpu).irqs[irq]++; | |
345 | ||
346 | /* | |
347 | * If its disabled or no action available | |
348 | * keep it masked and get out of here | |
349 | */ | |
350 | action = desc->action; | |
5a43a066 BH |
351 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
352 | desc->status |= IRQ_PENDING; | |
86998aa6 | 353 | goto out_unlock; |
5a43a066 | 354 | } |
dd87eb3a TG |
355 | |
356 | desc->status |= IRQ_INPROGRESS; | |
5a43a066 | 357 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
358 | spin_unlock(&desc->lock); |
359 | ||
7d12e780 | 360 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 361 | if (!noirqdebug) |
7d12e780 | 362 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
363 | |
364 | spin_lock(&desc->lock); | |
365 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
366 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
367 | desc->chip->unmask(irq); | |
86998aa6 | 368 | out_unlock: |
dd87eb3a TG |
369 | spin_unlock(&desc->lock); |
370 | } | |
371 | ||
372 | /** | |
47c2a3aa | 373 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
374 | * @irq: the interrupt number |
375 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 376 | * |
47c2a3aa | 377 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
378 | * call when the interrupt has been serviced. This enables support |
379 | * for modern forms of interrupt handlers, which handle the flow | |
380 | * details in hardware, transparently. | |
381 | */ | |
382 | void fastcall | |
7d12e780 | 383 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
384 | { |
385 | unsigned int cpu = smp_processor_id(); | |
386 | struct irqaction *action; | |
387 | irqreturn_t action_ret; | |
388 | ||
389 | spin_lock(&desc->lock); | |
390 | ||
391 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
392 | goto out; | |
393 | ||
394 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
395 | kstat_cpu(cpu).irqs[irq]++; | |
396 | ||
397 | /* | |
398 | * If its disabled or no action available | |
399 | * keep it masked and get out of here | |
400 | */ | |
401 | action = desc->action; | |
98bb244b BH |
402 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
403 | desc->status |= IRQ_PENDING; | |
dd87eb3a | 404 | goto out; |
98bb244b | 405 | } |
dd87eb3a TG |
406 | |
407 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 408 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
409 | spin_unlock(&desc->lock); |
410 | ||
7d12e780 | 411 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 412 | if (!noirqdebug) |
7d12e780 | 413 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
414 | |
415 | spin_lock(&desc->lock); | |
416 | desc->status &= ~IRQ_INPROGRESS; | |
417 | out: | |
47c2a3aa | 418 | desc->chip->eoi(irq); |
dd87eb3a TG |
419 | |
420 | spin_unlock(&desc->lock); | |
421 | } | |
422 | ||
423 | /** | |
424 | * handle_edge_irq - edge type IRQ handler | |
425 | * @irq: the interrupt number | |
426 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
427 | * |
428 | * Interrupt occures on the falling and/or rising edge of a hardware | |
429 | * signal. The occurence is latched into the irq controller hardware | |
430 | * and must be acked in order to be reenabled. After the ack another | |
431 | * interrupt can happen on the same source even before the first one | |
432 | * is handled by the assosiacted event handler. If this happens it | |
433 | * might be necessary to disable (mask) the interrupt depending on the | |
434 | * controller hardware. This requires to reenable the interrupt inside | |
435 | * of the loop which handles the interrupts which have arrived while | |
436 | * the handler was running. If all pending interrupts are handled, the | |
437 | * loop is left. | |
438 | */ | |
439 | void fastcall | |
7d12e780 | 440 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
441 | { |
442 | const unsigned int cpu = smp_processor_id(); | |
443 | ||
444 | spin_lock(&desc->lock); | |
445 | ||
446 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
447 | ||
448 | /* | |
449 | * If we're currently running this IRQ, or its disabled, | |
450 | * we shouldn't process the IRQ. Mark it pending, handle | |
451 | * the necessary masking and go out | |
452 | */ | |
453 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
454 | !desc->action)) { | |
455 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
456 | mask_ack_irq(desc, irq); | |
457 | goto out_unlock; | |
458 | } | |
459 | ||
460 | kstat_cpu(cpu).irqs[irq]++; | |
461 | ||
462 | /* Start handling the irq */ | |
463 | desc->chip->ack(irq); | |
464 | ||
465 | /* Mark the IRQ currently in progress.*/ | |
466 | desc->status |= IRQ_INPROGRESS; | |
467 | ||
468 | do { | |
469 | struct irqaction *action = desc->action; | |
470 | irqreturn_t action_ret; | |
471 | ||
472 | if (unlikely(!action)) { | |
473 | desc->chip->mask(irq); | |
474 | goto out_unlock; | |
475 | } | |
476 | ||
477 | /* | |
478 | * When another irq arrived while we were handling | |
479 | * one, we could have masked the irq. | |
480 | * Renable it, if it was not disabled in meantime. | |
481 | */ | |
482 | if (unlikely((desc->status & | |
483 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
484 | (IRQ_PENDING | IRQ_MASKED))) { | |
485 | desc->chip->unmask(irq); | |
486 | desc->status &= ~IRQ_MASKED; | |
487 | } | |
488 | ||
489 | desc->status &= ~IRQ_PENDING; | |
490 | spin_unlock(&desc->lock); | |
7d12e780 | 491 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 492 | if (!noirqdebug) |
7d12e780 | 493 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
494 | spin_lock(&desc->lock); |
495 | ||
496 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
497 | ||
498 | desc->status &= ~IRQ_INPROGRESS; | |
499 | out_unlock: | |
500 | spin_unlock(&desc->lock); | |
501 | } | |
502 | ||
503 | #ifdef CONFIG_SMP | |
504 | /** | |
505 | * handle_percpu_IRQ - Per CPU local irq handler | |
506 | * @irq: the interrupt number | |
507 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
508 | * |
509 | * Per CPU interrupts on SMP machines without locking requirements | |
510 | */ | |
511 | void fastcall | |
7d12e780 | 512 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
513 | { |
514 | irqreturn_t action_ret; | |
515 | ||
516 | kstat_this_cpu.irqs[irq]++; | |
517 | ||
518 | if (desc->chip->ack) | |
519 | desc->chip->ack(irq); | |
520 | ||
7d12e780 | 521 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 522 | if (!noirqdebug) |
7d12e780 | 523 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
524 | |
525 | if (desc->chip->eoi) | |
526 | desc->chip->eoi(irq); | |
527 | } | |
528 | ||
529 | #endif /* CONFIG_SMP */ | |
530 | ||
531 | void | |
a460e745 IM |
532 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
533 | const char *name) | |
dd87eb3a TG |
534 | { |
535 | struct irq_desc *desc; | |
536 | unsigned long flags; | |
537 | ||
538 | if (irq >= NR_IRQS) { | |
539 | printk(KERN_ERR | |
540 | "Trying to install type control for IRQ%d\n", irq); | |
541 | return; | |
542 | } | |
543 | ||
544 | desc = irq_desc + irq; | |
545 | ||
546 | if (!handle) | |
547 | handle = handle_bad_irq; | |
9d7ac8be | 548 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 549 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 550 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
551 | /* |
552 | * Some ARM implementations install a handler for really dumb | |
553 | * interrupt hardware without setting an irq_chip. This worked | |
554 | * with the ARM no_irq_chip but the check in setup_irq would | |
555 | * prevent us to setup the interrupt at all. Switch it to | |
556 | * dummy_irq_chip for easy transition. | |
557 | */ | |
558 | desc->chip = &dummy_irq_chip; | |
559 | } | |
dd87eb3a TG |
560 | |
561 | spin_lock_irqsave(&desc->lock, flags); | |
562 | ||
563 | /* Uninstall? */ | |
564 | if (handle == handle_bad_irq) { | |
565 | if (desc->chip != &no_irq_chip) { | |
566 | desc->chip->mask(irq); | |
567 | desc->chip->ack(irq); | |
568 | } | |
569 | desc->status |= IRQ_DISABLED; | |
570 | desc->depth = 1; | |
571 | } | |
572 | desc->handle_irq = handle; | |
a460e745 | 573 | desc->name = name; |
dd87eb3a TG |
574 | |
575 | if (handle != handle_bad_irq && is_chained) { | |
576 | desc->status &= ~IRQ_DISABLED; | |
577 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
578 | desc->depth = 0; | |
579 | desc->chip->unmask(irq); | |
580 | } | |
581 | spin_unlock_irqrestore(&desc->lock, flags); | |
582 | } | |
583 | ||
584 | void | |
585 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 586 | irq_flow_handler_t handle) |
dd87eb3a TG |
587 | { |
588 | set_irq_chip(irq, chip); | |
a460e745 | 589 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
590 | } |
591 | ||
a460e745 IM |
592 | void |
593 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
594 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 595 | { |
a460e745 IM |
596 | set_irq_chip(irq, chip); |
597 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 598 | } |