Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
f069686e SR |
19 | #include <trace/events/irq.h> |
20 | ||
dd87eb3a TG |
21 | #include "internals.h" |
22 | ||
23 | /** | |
a0cd9ca2 | 24 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
25 | * @irq: irq number |
26 | * @chip: pointer to irq chip description structure | |
27 | */ | |
a0cd9ca2 | 28 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 29 | { |
dd87eb3a | 30 | unsigned long flags; |
31d9d9b6 | 31 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 32 | |
02725e74 | 33 | if (!desc) |
dd87eb3a | 34 | return -EINVAL; |
dd87eb3a TG |
35 | |
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
6b8ff312 | 39 | desc->irq_data.chip = chip; |
02725e74 | 40 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
41 | /* |
42 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
f63b6a05 | 43 | * allocated_irqs. |
d72274e5 | 44 | */ |
f63b6a05 | 45 | irq_mark_irq(irq); |
dd87eb3a TG |
46 | return 0; |
47 | } | |
a0cd9ca2 | 48 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
49 | |
50 | /** | |
a0cd9ca2 | 51 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 52 | * @irq: irq number |
0c5d1eb7 | 53 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 54 | */ |
a0cd9ca2 | 55 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 56 | { |
dd87eb3a | 57 | unsigned long flags; |
31d9d9b6 | 58 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 | 59 | int ret = 0; |
dd87eb3a | 60 | |
02725e74 TG |
61 | if (!desc) |
62 | return -EINVAL; | |
dd87eb3a | 63 | |
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
a09b659c | 65 | ret = __irq_set_trigger(desc, irq, type); |
02725e74 | 66 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a TG |
67 | return ret; |
68 | } | |
a0cd9ca2 | 69 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
70 | |
71 | /** | |
a0cd9ca2 | 72 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
73 | * @irq: Interrupt number |
74 | * @data: Pointer to interrupt specific data | |
75 | * | |
76 | * Set the hardware irq controller data for an irq | |
77 | */ | |
a0cd9ca2 | 78 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 79 | { |
dd87eb3a | 80 | unsigned long flags; |
31d9d9b6 | 81 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 82 | |
02725e74 | 83 | if (!desc) |
dd87eb3a | 84 | return -EINVAL; |
6b8ff312 | 85 | desc->irq_data.handler_data = data; |
02725e74 | 86 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
87 | return 0; |
88 | } | |
a0cd9ca2 | 89 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 90 | |
5b912c10 | 91 | /** |
51906e77 AG |
92 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
93 | * @irq_base: Interrupt number base | |
94 | * @irq_offset: Interrupt number offset | |
95 | * @entry: Pointer to MSI descriptor data | |
5b912c10 | 96 | * |
51906e77 | 97 | * Set the MSI descriptor entry for an irq at offset |
5b912c10 | 98 | */ |
51906e77 AG |
99 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
100 | struct msi_desc *entry) | |
5b912c10 | 101 | { |
5b912c10 | 102 | unsigned long flags; |
51906e77 | 103 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
5b912c10 | 104 | |
02725e74 | 105 | if (!desc) |
5b912c10 | 106 | return -EINVAL; |
6b8ff312 | 107 | desc->irq_data.msi_desc = entry; |
51906e77 AG |
108 | if (entry && !irq_offset) |
109 | entry->irq = irq_base; | |
02725e74 | 110 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
111 | return 0; |
112 | } | |
113 | ||
51906e77 AG |
114 | /** |
115 | * irq_set_msi_desc - set MSI descriptor data for an irq | |
116 | * @irq: Interrupt number | |
117 | * @entry: Pointer to MSI descriptor data | |
118 | * | |
119 | * Set the MSI descriptor entry for an irq | |
120 | */ | |
121 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | |
122 | { | |
123 | return irq_set_msi_desc_off(irq, 0, entry); | |
124 | } | |
125 | ||
dd87eb3a | 126 | /** |
a0cd9ca2 | 127 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
128 | * @irq: Interrupt number |
129 | * @data: Pointer to chip specific data | |
130 | * | |
131 | * Set the hardware irq chip data for an irq | |
132 | */ | |
a0cd9ca2 | 133 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 134 | { |
dd87eb3a | 135 | unsigned long flags; |
31d9d9b6 | 136 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 137 | |
02725e74 | 138 | if (!desc) |
dd87eb3a | 139 | return -EINVAL; |
6b8ff312 | 140 | desc->irq_data.chip_data = data; |
02725e74 | 141 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
142 | return 0; |
143 | } | |
a0cd9ca2 | 144 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 145 | |
f303a6dd TG |
146 | struct irq_data *irq_get_irq_data(unsigned int irq) |
147 | { | |
148 | struct irq_desc *desc = irq_to_desc(irq); | |
149 | ||
150 | return desc ? &desc->irq_data : NULL; | |
151 | } | |
152 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
153 | ||
c1594b77 TG |
154 | static void irq_state_clr_disabled(struct irq_desc *desc) |
155 | { | |
801a0e9a | 156 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
157 | } |
158 | ||
159 | static void irq_state_set_disabled(struct irq_desc *desc) | |
160 | { | |
801a0e9a | 161 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
162 | } |
163 | ||
6e40262e TG |
164 | static void irq_state_clr_masked(struct irq_desc *desc) |
165 | { | |
32f4125e | 166 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
167 | } |
168 | ||
169 | static void irq_state_set_masked(struct irq_desc *desc) | |
170 | { | |
32f4125e | 171 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
172 | } |
173 | ||
b4bc724e | 174 | int irq_startup(struct irq_desc *desc, bool resend) |
46999238 | 175 | { |
b4bc724e TG |
176 | int ret = 0; |
177 | ||
c1594b77 | 178 | irq_state_clr_disabled(desc); |
46999238 TG |
179 | desc->depth = 0; |
180 | ||
3aae994f | 181 | if (desc->irq_data.chip->irq_startup) { |
b4bc724e | 182 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
6e40262e | 183 | irq_state_clr_masked(desc); |
b4bc724e TG |
184 | } else { |
185 | irq_enable(desc); | |
3aae994f | 186 | } |
b4bc724e TG |
187 | if (resend) |
188 | check_irq_resend(desc, desc->irq_data.irq); | |
189 | return ret; | |
46999238 TG |
190 | } |
191 | ||
192 | void irq_shutdown(struct irq_desc *desc) | |
193 | { | |
c1594b77 | 194 | irq_state_set_disabled(desc); |
46999238 | 195 | desc->depth = 1; |
50f7c032 TG |
196 | if (desc->irq_data.chip->irq_shutdown) |
197 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
ed585a65 | 198 | else if (desc->irq_data.chip->irq_disable) |
50f7c032 TG |
199 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
200 | else | |
201 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 202 | irq_state_set_masked(desc); |
46999238 TG |
203 | } |
204 | ||
87923470 TG |
205 | void irq_enable(struct irq_desc *desc) |
206 | { | |
c1594b77 | 207 | irq_state_clr_disabled(desc); |
50f7c032 TG |
208 | if (desc->irq_data.chip->irq_enable) |
209 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
210 | else | |
211 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 212 | irq_state_clr_masked(desc); |
dd87eb3a TG |
213 | } |
214 | ||
d671a605 | 215 | /** |
f788e7bf | 216 | * irq_disable - Mark interrupt disabled |
d671a605 AF |
217 | * @desc: irq descriptor which should be disabled |
218 | * | |
219 | * If the chip does not implement the irq_disable callback, we | |
220 | * use a lazy disable approach. That means we mark the interrupt | |
221 | * disabled, but leave the hardware unmasked. That's an | |
222 | * optimization because we avoid the hardware access for the | |
223 | * common case where no interrupt happens after we marked it | |
224 | * disabled. If an interrupt happens, then the interrupt flow | |
225 | * handler masks the line at the hardware level and marks it | |
226 | * pending. | |
227 | */ | |
50f7c032 | 228 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 229 | { |
c1594b77 | 230 | irq_state_set_disabled(desc); |
50f7c032 TG |
231 | if (desc->irq_data.chip->irq_disable) { |
232 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 233 | irq_state_set_masked(desc); |
50f7c032 | 234 | } |
89d694b9 TG |
235 | } |
236 | ||
31d9d9b6 MZ |
237 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
238 | { | |
239 | if (desc->irq_data.chip->irq_enable) | |
240 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
241 | else | |
242 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
243 | cpumask_set_cpu(cpu, desc->percpu_enabled); | |
244 | } | |
245 | ||
246 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | |
247 | { | |
248 | if (desc->irq_data.chip->irq_disable) | |
249 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
250 | else | |
251 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
252 | cpumask_clear_cpu(cpu, desc->percpu_enabled); | |
253 | } | |
254 | ||
9205e31d | 255 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 256 | { |
9205e31d TG |
257 | if (desc->irq_data.chip->irq_mask_ack) |
258 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 259 | else { |
e2c0f8ff | 260 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
261 | if (desc->irq_data.chip->irq_ack) |
262 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 263 | } |
6e40262e | 264 | irq_state_set_masked(desc); |
0b1adaa0 TG |
265 | } |
266 | ||
d4d5e089 | 267 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 268 | { |
e2c0f8ff TG |
269 | if (desc->irq_data.chip->irq_mask) { |
270 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 271 | irq_state_set_masked(desc); |
0b1adaa0 TG |
272 | } |
273 | } | |
274 | ||
d4d5e089 | 275 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 276 | { |
0eda58b7 TG |
277 | if (desc->irq_data.chip->irq_unmask) { |
278 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 279 | irq_state_clr_masked(desc); |
0b1adaa0 | 280 | } |
dd87eb3a TG |
281 | } |
282 | ||
328a4978 TG |
283 | void unmask_threaded_irq(struct irq_desc *desc) |
284 | { | |
285 | struct irq_chip *chip = desc->irq_data.chip; | |
286 | ||
287 | if (chip->flags & IRQCHIP_EOI_THREADED) | |
288 | chip->irq_eoi(&desc->irq_data); | |
289 | ||
290 | if (chip->irq_unmask) { | |
291 | chip->irq_unmask(&desc->irq_data); | |
292 | irq_state_clr_masked(desc); | |
293 | } | |
294 | } | |
295 | ||
399b5da2 TG |
296 | /* |
297 | * handle_nested_irq - Handle a nested irq from a irq thread | |
298 | * @irq: the interrupt number | |
299 | * | |
300 | * Handle interrupts which are nested into a threaded interrupt | |
301 | * handler. The handler function is called inside the calling | |
302 | * threads context. | |
303 | */ | |
304 | void handle_nested_irq(unsigned int irq) | |
305 | { | |
306 | struct irq_desc *desc = irq_to_desc(irq); | |
307 | struct irqaction *action; | |
308 | irqreturn_t action_ret; | |
309 | ||
310 | might_sleep(); | |
311 | ||
239007b8 | 312 | raw_spin_lock_irq(&desc->lock); |
399b5da2 | 313 | |
293a7a0a | 314 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
399b5da2 TG |
315 | kstat_incr_irqs_this_cpu(irq, desc); |
316 | ||
317 | action = desc->action; | |
23812b9d NJ |
318 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
319 | desc->istate |= IRQS_PENDING; | |
399b5da2 | 320 | goto out_unlock; |
23812b9d | 321 | } |
399b5da2 | 322 | |
32f4125e | 323 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 324 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
325 | |
326 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
327 | if (!noirqdebug) | |
328 | note_interrupt(irq, desc, action_ret); | |
329 | ||
239007b8 | 330 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 331 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
332 | |
333 | out_unlock: | |
239007b8 | 334 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
335 | } |
336 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
337 | ||
fe200ae4 TG |
338 | static bool irq_check_poll(struct irq_desc *desc) |
339 | { | |
6954b75b | 340 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
341 | return false; |
342 | return irq_wait_for_poll(desc); | |
343 | } | |
344 | ||
dd87eb3a TG |
345 | /** |
346 | * handle_simple_irq - Simple and software-decoded IRQs. | |
347 | * @irq: the interrupt number | |
348 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
349 | * |
350 | * Simple interrupts are either sent from a demultiplexing interrupt | |
351 | * handler or come from hardware, where no interrupt hardware control | |
352 | * is necessary. | |
353 | * | |
354 | * Note: The caller is expected to handle the ack, clear, mask and | |
355 | * unmask issues if necessary. | |
356 | */ | |
7ad5b3a5 | 357 | void |
7d12e780 | 358 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 359 | { |
239007b8 | 360 | raw_spin_lock(&desc->lock); |
dd87eb3a | 361 | |
32f4125e | 362 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
363 | if (!irq_check_poll(desc)) |
364 | goto out_unlock; | |
365 | ||
163ef309 | 366 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 367 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 368 | |
23812b9d NJ |
369 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
370 | desc->istate |= IRQS_PENDING; | |
dd87eb3a | 371 | goto out_unlock; |
23812b9d | 372 | } |
dd87eb3a | 373 | |
107781e7 | 374 | handle_irq_event(desc); |
dd87eb3a | 375 | |
dd87eb3a | 376 | out_unlock: |
239007b8 | 377 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 378 | } |
edf76f83 | 379 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
dd87eb3a | 380 | |
ac563761 TG |
381 | /* |
382 | * Called unconditionally from handle_level_irq() and only for oneshot | |
383 | * interrupts from handle_fasteoi_irq() | |
384 | */ | |
385 | static void cond_unmask_irq(struct irq_desc *desc) | |
386 | { | |
387 | /* | |
388 | * We need to unmask in the following cases: | |
389 | * - Standard level irq (IRQF_ONESHOT is not set) | |
390 | * - Oneshot irq which did not wake the thread (caused by a | |
391 | * spurious interrupt or a primary handler handling it | |
392 | * completely). | |
393 | */ | |
394 | if (!irqd_irq_disabled(&desc->irq_data) && | |
395 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | |
396 | unmask_irq(desc); | |
397 | } | |
398 | ||
dd87eb3a TG |
399 | /** |
400 | * handle_level_irq - Level type irq handler | |
401 | * @irq: the interrupt number | |
402 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
403 | * |
404 | * Level type interrupts are active as long as the hardware line has | |
405 | * the active level. This may require to mask the interrupt and unmask | |
406 | * it after the associated handler has acknowledged the device, so the | |
407 | * interrupt line is back to inactive. | |
408 | */ | |
7ad5b3a5 | 409 | void |
7d12e780 | 410 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 411 | { |
239007b8 | 412 | raw_spin_lock(&desc->lock); |
9205e31d | 413 | mask_ack_irq(desc); |
dd87eb3a | 414 | |
32f4125e | 415 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
416 | if (!irq_check_poll(desc)) |
417 | goto out_unlock; | |
418 | ||
163ef309 | 419 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 420 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
421 | |
422 | /* | |
423 | * If its disabled or no action available | |
424 | * keep it masked and get out of here | |
425 | */ | |
d4dc0f90 TG |
426 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
427 | desc->istate |= IRQS_PENDING; | |
86998aa6 | 428 | goto out_unlock; |
d4dc0f90 | 429 | } |
dd87eb3a | 430 | |
1529866c | 431 | handle_irq_event(desc); |
b25c340c | 432 | |
ac563761 TG |
433 | cond_unmask_irq(desc); |
434 | ||
86998aa6 | 435 | out_unlock: |
239007b8 | 436 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 437 | } |
14819ea1 | 438 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 439 | |
78129576 TG |
440 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
441 | static inline void preflow_handler(struct irq_desc *desc) | |
442 | { | |
443 | if (desc->preflow_handler) | |
444 | desc->preflow_handler(&desc->irq_data); | |
445 | } | |
446 | #else | |
447 | static inline void preflow_handler(struct irq_desc *desc) { } | |
448 | #endif | |
449 | ||
328a4978 TG |
450 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
451 | { | |
452 | if (!(desc->istate & IRQS_ONESHOT)) { | |
453 | chip->irq_eoi(&desc->irq_data); | |
454 | return; | |
455 | } | |
456 | /* | |
457 | * We need to unmask in the following cases: | |
458 | * - Oneshot irq which did not wake the thread (caused by a | |
459 | * spurious interrupt or a primary handler handling it | |
460 | * completely). | |
461 | */ | |
462 | if (!irqd_irq_disabled(&desc->irq_data) && | |
463 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { | |
464 | chip->irq_eoi(&desc->irq_data); | |
465 | unmask_irq(desc); | |
466 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { | |
467 | chip->irq_eoi(&desc->irq_data); | |
468 | } | |
469 | } | |
470 | ||
dd87eb3a | 471 | /** |
47c2a3aa | 472 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
473 | * @irq: the interrupt number |
474 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 475 | * |
47c2a3aa | 476 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
477 | * call when the interrupt has been serviced. This enables support |
478 | * for modern forms of interrupt handlers, which handle the flow | |
479 | * details in hardware, transparently. | |
480 | */ | |
7ad5b3a5 | 481 | void |
7d12e780 | 482 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 483 | { |
328a4978 TG |
484 | struct irq_chip *chip = desc->irq_data.chip; |
485 | ||
239007b8 | 486 | raw_spin_lock(&desc->lock); |
dd87eb3a | 487 | |
32f4125e | 488 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
489 | if (!irq_check_poll(desc)) |
490 | goto out; | |
dd87eb3a | 491 | |
163ef309 | 492 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 493 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
494 | |
495 | /* | |
496 | * If its disabled or no action available | |
76d21601 | 497 | * then mask it and get out of here: |
dd87eb3a | 498 | */ |
32f4125e | 499 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 500 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 501 | mask_irq(desc); |
dd87eb3a | 502 | goto out; |
98bb244b | 503 | } |
c69e3758 TG |
504 | |
505 | if (desc->istate & IRQS_ONESHOT) | |
506 | mask_irq(desc); | |
507 | ||
78129576 | 508 | preflow_handler(desc); |
a7ae4de5 | 509 | handle_irq_event(desc); |
77694b40 | 510 | |
328a4978 | 511 | cond_unmask_eoi_irq(desc, chip); |
ac563761 | 512 | |
239007b8 | 513 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
514 | return; |
515 | out: | |
328a4978 TG |
516 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
517 | chip->irq_eoi(&desc->irq_data); | |
518 | raw_spin_unlock(&desc->lock); | |
dd87eb3a TG |
519 | } |
520 | ||
521 | /** | |
522 | * handle_edge_irq - edge type IRQ handler | |
523 | * @irq: the interrupt number | |
524 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
525 | * |
526 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 527 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
528 | * and must be acked in order to be reenabled. After the ack another |
529 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 530 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
531 | * might be necessary to disable (mask) the interrupt depending on the |
532 | * controller hardware. This requires to reenable the interrupt inside | |
533 | * of the loop which handles the interrupts which have arrived while | |
534 | * the handler was running. If all pending interrupts are handled, the | |
535 | * loop is left. | |
536 | */ | |
7ad5b3a5 | 537 | void |
7d12e780 | 538 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 539 | { |
239007b8 | 540 | raw_spin_lock(&desc->lock); |
dd87eb3a | 541 | |
163ef309 | 542 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
c3d7acd0 | 543 | |
dd87eb3a | 544 | /* |
c3d7acd0 TG |
545 | * If the handler is currently running, mark it pending, |
546 | * handle the necessary masking and go out | |
dd87eb3a | 547 | */ |
c3d7acd0 | 548 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
fe200ae4 | 549 | if (!irq_check_poll(desc)) { |
2a0d6fb3 | 550 | desc->istate |= IRQS_PENDING; |
fe200ae4 TG |
551 | mask_ack_irq(desc); |
552 | goto out_unlock; | |
553 | } | |
dd87eb3a | 554 | } |
c3d7acd0 TG |
555 | |
556 | /* | |
557 | * If its disabled or no action available then mask it and get | |
558 | * out of here. | |
559 | */ | |
560 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { | |
561 | desc->istate |= IRQS_PENDING; | |
562 | mask_ack_irq(desc); | |
563 | goto out_unlock; | |
564 | } | |
565 | ||
d6c88a50 | 566 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
567 | |
568 | /* Start handling the irq */ | |
22a49163 | 569 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 570 | |
dd87eb3a | 571 | do { |
a60a5dc2 | 572 | if (unlikely(!desc->action)) { |
e2c0f8ff | 573 | mask_irq(desc); |
dd87eb3a TG |
574 | goto out_unlock; |
575 | } | |
576 | ||
577 | /* | |
578 | * When another irq arrived while we were handling | |
579 | * one, we could have masked the irq. | |
580 | * Renable it, if it was not disabled in meantime. | |
581 | */ | |
2a0d6fb3 | 582 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
583 | if (!irqd_irq_disabled(&desc->irq_data) && |
584 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 585 | unmask_irq(desc); |
dd87eb3a TG |
586 | } |
587 | ||
a60a5dc2 | 588 | handle_irq_event(desc); |
dd87eb3a | 589 | |
2a0d6fb3 | 590 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 591 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 592 | |
dd87eb3a | 593 | out_unlock: |
239007b8 | 594 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 595 | } |
3911ff30 | 596 | EXPORT_SYMBOL(handle_edge_irq); |
dd87eb3a | 597 | |
0521c8fb TG |
598 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
599 | /** | |
600 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
601 | * @irq: the interrupt number | |
602 | * @desc: the interrupt description structure for this irq | |
603 | * | |
604 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
605 | * mask/unmask logic. | |
606 | */ | |
607 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | |
608 | { | |
609 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
610 | ||
611 | raw_spin_lock(&desc->lock); | |
612 | ||
613 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
c3d7acd0 | 614 | |
0521c8fb | 615 | /* |
c3d7acd0 TG |
616 | * If the handler is currently running, mark it pending, |
617 | * handle the necessary masking and go out | |
0521c8fb | 618 | */ |
c3d7acd0 | 619 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0521c8fb TG |
620 | if (!irq_check_poll(desc)) { |
621 | desc->istate |= IRQS_PENDING; | |
622 | goto out_eoi; | |
623 | } | |
624 | } | |
c3d7acd0 TG |
625 | |
626 | /* | |
627 | * If its disabled or no action available then mask it and get | |
628 | * out of here. | |
629 | */ | |
630 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { | |
631 | desc->istate |= IRQS_PENDING; | |
632 | goto out_eoi; | |
633 | } | |
634 | ||
0521c8fb TG |
635 | kstat_incr_irqs_this_cpu(irq, desc); |
636 | ||
637 | do { | |
638 | if (unlikely(!desc->action)) | |
639 | goto out_eoi; | |
640 | ||
641 | handle_irq_event(desc); | |
642 | ||
643 | } while ((desc->istate & IRQS_PENDING) && | |
644 | !irqd_irq_disabled(&desc->irq_data)); | |
645 | ||
ac0e0447 | 646 | out_eoi: |
0521c8fb TG |
647 | chip->irq_eoi(&desc->irq_data); |
648 | raw_spin_unlock(&desc->lock); | |
649 | } | |
650 | #endif | |
651 | ||
dd87eb3a | 652 | /** |
24b26d42 | 653 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
654 | * @irq: the interrupt number |
655 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
656 | * |
657 | * Per CPU interrupts on SMP machines without locking requirements | |
658 | */ | |
7ad5b3a5 | 659 | void |
7d12e780 | 660 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 661 | { |
35e857cb | 662 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 663 | |
d6c88a50 | 664 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 665 | |
849f061c TG |
666 | if (chip->irq_ack) |
667 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 668 | |
849f061c | 669 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 670 | |
849f061c TG |
671 | if (chip->irq_eoi) |
672 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
673 | } |
674 | ||
31d9d9b6 MZ |
675 | /** |
676 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | |
677 | * @irq: the interrupt number | |
678 | * @desc: the interrupt description structure for this irq | |
679 | * | |
680 | * Per CPU interrupts on SMP machines without locking requirements. Same as | |
681 | * handle_percpu_irq() above but with the following extras: | |
682 | * | |
683 | * action->percpu_dev_id is a pointer to percpu variables which | |
684 | * contain the real device id for the cpu on which this handler is | |
685 | * called | |
686 | */ | |
687 | void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) | |
688 | { | |
689 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
690 | struct irqaction *action = desc->action; | |
691 | void *dev_id = __this_cpu_ptr(action->percpu_dev_id); | |
692 | irqreturn_t res; | |
693 | ||
694 | kstat_incr_irqs_this_cpu(irq, desc); | |
695 | ||
696 | if (chip->irq_ack) | |
697 | chip->irq_ack(&desc->irq_data); | |
698 | ||
699 | trace_irq_handler_entry(irq, action); | |
700 | res = action->handler(irq, dev_id); | |
701 | trace_irq_handler_exit(irq, action, res); | |
702 | ||
703 | if (chip->irq_eoi) | |
704 | chip->irq_eoi(&desc->irq_data); | |
705 | } | |
706 | ||
dd87eb3a | 707 | void |
3836ca08 | 708 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 709 | const char *name) |
dd87eb3a | 710 | { |
dd87eb3a | 711 | unsigned long flags; |
31d9d9b6 | 712 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
dd87eb3a | 713 | |
02725e74 | 714 | if (!desc) |
dd87eb3a | 715 | return; |
dd87eb3a | 716 | |
091738a2 | 717 | if (!handle) { |
dd87eb3a | 718 | handle = handle_bad_irq; |
091738a2 TG |
719 | } else { |
720 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | |
02725e74 | 721 | goto out; |
f8b5473f | 722 | } |
dd87eb3a | 723 | |
dd87eb3a TG |
724 | /* Uninstall? */ |
725 | if (handle == handle_bad_irq) { | |
6b8ff312 | 726 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 727 | mask_ack_irq(desc); |
801a0e9a | 728 | irq_state_set_disabled(desc); |
dd87eb3a TG |
729 | desc->depth = 1; |
730 | } | |
731 | desc->handle_irq = handle; | |
a460e745 | 732 | desc->name = name; |
dd87eb3a TG |
733 | |
734 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
735 | irq_settings_set_noprobe(desc); |
736 | irq_settings_set_norequest(desc); | |
7f1b1244 | 737 | irq_settings_set_nothread(desc); |
b4bc724e | 738 | irq_startup(desc, true); |
dd87eb3a | 739 | } |
02725e74 TG |
740 | out: |
741 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a | 742 | } |
3836ca08 | 743 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a TG |
744 | |
745 | void | |
3836ca08 | 746 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 747 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 748 | { |
35e857cb | 749 | irq_set_chip(irq, chip); |
3836ca08 | 750 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 751 | } |
b3ae66f2 | 752 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
46f4f8f6 | 753 | |
44247184 | 754 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 755 | { |
46f4f8f6 | 756 | unsigned long flags; |
31d9d9b6 | 757 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
46f4f8f6 | 758 | |
44247184 | 759 | if (!desc) |
46f4f8f6 | 760 | return; |
a005677b TG |
761 | irq_settings_clr_and_set(desc, clr, set); |
762 | ||
876dbd4c | 763 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 764 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
765 | if (irq_settings_has_no_balance_set(desc)) |
766 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
767 | if (irq_settings_is_per_cpu(desc)) | |
768 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
769 | if (irq_settings_can_move_pcntxt(desc)) |
770 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
771 | if (irq_settings_is_level(desc)) |
772 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 773 | |
876dbd4c TG |
774 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
775 | ||
02725e74 | 776 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 777 | } |
edf76f83 | 778 | EXPORT_SYMBOL_GPL(irq_modify_status); |
0fdb4b25 DD |
779 | |
780 | /** | |
781 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
782 | * | |
783 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
784 | * for each. | |
785 | */ | |
786 | void irq_cpu_online(void) | |
787 | { | |
788 | struct irq_desc *desc; | |
789 | struct irq_chip *chip; | |
790 | unsigned long flags; | |
791 | unsigned int irq; | |
792 | ||
793 | for_each_active_irq(irq) { | |
794 | desc = irq_to_desc(irq); | |
795 | if (!desc) | |
796 | continue; | |
797 | ||
798 | raw_spin_lock_irqsave(&desc->lock, flags); | |
799 | ||
800 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
801 | if (chip && chip->irq_cpu_online && |
802 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 803 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
804 | chip->irq_cpu_online(&desc->irq_data); |
805 | ||
806 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
807 | } | |
808 | } | |
809 | ||
810 | /** | |
811 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
812 | * | |
813 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
814 | * for each. | |
815 | */ | |
816 | void irq_cpu_offline(void) | |
817 | { | |
818 | struct irq_desc *desc; | |
819 | struct irq_chip *chip; | |
820 | unsigned long flags; | |
821 | unsigned int irq; | |
822 | ||
823 | for_each_active_irq(irq) { | |
824 | desc = irq_to_desc(irq); | |
825 | if (!desc) | |
826 | continue; | |
827 | ||
828 | raw_spin_lock_irqsave(&desc->lock, flags); | |
829 | ||
830 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
831 | if (chip && chip->irq_cpu_offline && |
832 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 833 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
834 | chip->irq_cpu_offline(&desc->irq_data); |
835 | ||
836 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
837 | } | |
838 | } |