Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
f8264e34 | 18 | #include <linux/irqdomain.h> |
dd87eb3a | 19 | |
f069686e SR |
20 | #include <trace/events/irq.h> |
21 | ||
dd87eb3a TG |
22 | #include "internals.h" |
23 | ||
e509bd7d MW |
24 | static irqreturn_t bad_chained_irq(int irq, void *dev_id) |
25 | { | |
26 | WARN_ONCE(1, "Chained irq %d should not call an action\n", irq); | |
27 | return IRQ_NONE; | |
28 | } | |
29 | ||
30 | /* | |
31 | * Chained handlers should never call action on their IRQ. This default | |
32 | * action will emit warning if such thing happens. | |
33 | */ | |
34 | struct irqaction chained_action = { | |
35 | .handler = bad_chained_irq, | |
36 | }; | |
37 | ||
dd87eb3a | 38 | /** |
a0cd9ca2 | 39 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
40 | * @irq: irq number |
41 | * @chip: pointer to irq chip description structure | |
42 | */ | |
a0cd9ca2 | 43 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 44 | { |
dd87eb3a | 45 | unsigned long flags; |
31d9d9b6 | 46 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 47 | |
02725e74 | 48 | if (!desc) |
dd87eb3a | 49 | return -EINVAL; |
dd87eb3a TG |
50 | |
51 | if (!chip) | |
52 | chip = &no_irq_chip; | |
53 | ||
6b8ff312 | 54 | desc->irq_data.chip = chip; |
02725e74 | 55 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
56 | /* |
57 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
f63b6a05 | 58 | * allocated_irqs. |
d72274e5 | 59 | */ |
f63b6a05 | 60 | irq_mark_irq(irq); |
dd87eb3a TG |
61 | return 0; |
62 | } | |
a0cd9ca2 | 63 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
64 | |
65 | /** | |
a0cd9ca2 | 66 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 67 | * @irq: irq number |
0c5d1eb7 | 68 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 69 | */ |
a0cd9ca2 | 70 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 71 | { |
dd87eb3a | 72 | unsigned long flags; |
31d9d9b6 | 73 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 | 74 | int ret = 0; |
dd87eb3a | 75 | |
02725e74 TG |
76 | if (!desc) |
77 | return -EINVAL; | |
dd87eb3a | 78 | |
f2b662da | 79 | type &= IRQ_TYPE_SENSE_MASK; |
a1ff541a | 80 | ret = __irq_set_trigger(desc, type); |
02725e74 | 81 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a TG |
82 | return ret; |
83 | } | |
a0cd9ca2 | 84 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
85 | |
86 | /** | |
a0cd9ca2 | 87 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
88 | * @irq: Interrupt number |
89 | * @data: Pointer to interrupt specific data | |
90 | * | |
91 | * Set the hardware irq controller data for an irq | |
92 | */ | |
a0cd9ca2 | 93 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 94 | { |
dd87eb3a | 95 | unsigned long flags; |
31d9d9b6 | 96 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 97 | |
02725e74 | 98 | if (!desc) |
dd87eb3a | 99 | return -EINVAL; |
af7080e0 | 100 | desc->irq_common_data.handler_data = data; |
02725e74 | 101 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
102 | return 0; |
103 | } | |
a0cd9ca2 | 104 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 105 | |
5b912c10 | 106 | /** |
51906e77 AG |
107 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
108 | * @irq_base: Interrupt number base | |
109 | * @irq_offset: Interrupt number offset | |
110 | * @entry: Pointer to MSI descriptor data | |
5b912c10 | 111 | * |
51906e77 | 112 | * Set the MSI descriptor entry for an irq at offset |
5b912c10 | 113 | */ |
51906e77 AG |
114 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
115 | struct msi_desc *entry) | |
5b912c10 | 116 | { |
5b912c10 | 117 | unsigned long flags; |
51906e77 | 118 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
5b912c10 | 119 | |
02725e74 | 120 | if (!desc) |
5b912c10 | 121 | return -EINVAL; |
b237721c | 122 | desc->irq_common_data.msi_desc = entry; |
51906e77 AG |
123 | if (entry && !irq_offset) |
124 | entry->irq = irq_base; | |
02725e74 | 125 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
126 | return 0; |
127 | } | |
128 | ||
51906e77 AG |
129 | /** |
130 | * irq_set_msi_desc - set MSI descriptor data for an irq | |
131 | * @irq: Interrupt number | |
132 | * @entry: Pointer to MSI descriptor data | |
133 | * | |
134 | * Set the MSI descriptor entry for an irq | |
135 | */ | |
136 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | |
137 | { | |
138 | return irq_set_msi_desc_off(irq, 0, entry); | |
139 | } | |
140 | ||
dd87eb3a | 141 | /** |
a0cd9ca2 | 142 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
143 | * @irq: Interrupt number |
144 | * @data: Pointer to chip specific data | |
145 | * | |
146 | * Set the hardware irq chip data for an irq | |
147 | */ | |
a0cd9ca2 | 148 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 149 | { |
dd87eb3a | 150 | unsigned long flags; |
31d9d9b6 | 151 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 152 | |
02725e74 | 153 | if (!desc) |
dd87eb3a | 154 | return -EINVAL; |
6b8ff312 | 155 | desc->irq_data.chip_data = data; |
02725e74 | 156 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
157 | return 0; |
158 | } | |
a0cd9ca2 | 159 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 160 | |
f303a6dd TG |
161 | struct irq_data *irq_get_irq_data(unsigned int irq) |
162 | { | |
163 | struct irq_desc *desc = irq_to_desc(irq); | |
164 | ||
165 | return desc ? &desc->irq_data : NULL; | |
166 | } | |
167 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
168 | ||
c1594b77 TG |
169 | static void irq_state_clr_disabled(struct irq_desc *desc) |
170 | { | |
801a0e9a | 171 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
172 | } |
173 | ||
174 | static void irq_state_set_disabled(struct irq_desc *desc) | |
175 | { | |
801a0e9a | 176 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
177 | } |
178 | ||
6e40262e TG |
179 | static void irq_state_clr_masked(struct irq_desc *desc) |
180 | { | |
32f4125e | 181 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
182 | } |
183 | ||
184 | static void irq_state_set_masked(struct irq_desc *desc) | |
185 | { | |
32f4125e | 186 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
187 | } |
188 | ||
b4bc724e | 189 | int irq_startup(struct irq_desc *desc, bool resend) |
46999238 | 190 | { |
b4bc724e TG |
191 | int ret = 0; |
192 | ||
c1594b77 | 193 | irq_state_clr_disabled(desc); |
46999238 TG |
194 | desc->depth = 0; |
195 | ||
f8264e34 | 196 | irq_domain_activate_irq(&desc->irq_data); |
3aae994f | 197 | if (desc->irq_data.chip->irq_startup) { |
b4bc724e | 198 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
6e40262e | 199 | irq_state_clr_masked(desc); |
b4bc724e TG |
200 | } else { |
201 | irq_enable(desc); | |
3aae994f | 202 | } |
b4bc724e | 203 | if (resend) |
0798abeb | 204 | check_irq_resend(desc); |
b4bc724e | 205 | return ret; |
46999238 TG |
206 | } |
207 | ||
208 | void irq_shutdown(struct irq_desc *desc) | |
209 | { | |
c1594b77 | 210 | irq_state_set_disabled(desc); |
46999238 | 211 | desc->depth = 1; |
50f7c032 TG |
212 | if (desc->irq_data.chip->irq_shutdown) |
213 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
ed585a65 | 214 | else if (desc->irq_data.chip->irq_disable) |
50f7c032 TG |
215 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
216 | else | |
217 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
f8264e34 | 218 | irq_domain_deactivate_irq(&desc->irq_data); |
6e40262e | 219 | irq_state_set_masked(desc); |
46999238 TG |
220 | } |
221 | ||
87923470 TG |
222 | void irq_enable(struct irq_desc *desc) |
223 | { | |
c1594b77 | 224 | irq_state_clr_disabled(desc); |
50f7c032 TG |
225 | if (desc->irq_data.chip->irq_enable) |
226 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
227 | else | |
228 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 229 | irq_state_clr_masked(desc); |
dd87eb3a TG |
230 | } |
231 | ||
d671a605 | 232 | /** |
f788e7bf | 233 | * irq_disable - Mark interrupt disabled |
d671a605 AF |
234 | * @desc: irq descriptor which should be disabled |
235 | * | |
236 | * If the chip does not implement the irq_disable callback, we | |
237 | * use a lazy disable approach. That means we mark the interrupt | |
238 | * disabled, but leave the hardware unmasked. That's an | |
239 | * optimization because we avoid the hardware access for the | |
240 | * common case where no interrupt happens after we marked it | |
241 | * disabled. If an interrupt happens, then the interrupt flow | |
242 | * handler masks the line at the hardware level and marks it | |
243 | * pending. | |
244 | */ | |
50f7c032 | 245 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 246 | { |
c1594b77 | 247 | irq_state_set_disabled(desc); |
50f7c032 TG |
248 | if (desc->irq_data.chip->irq_disable) { |
249 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 250 | irq_state_set_masked(desc); |
50f7c032 | 251 | } |
89d694b9 TG |
252 | } |
253 | ||
31d9d9b6 MZ |
254 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
255 | { | |
256 | if (desc->irq_data.chip->irq_enable) | |
257 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
258 | else | |
259 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
260 | cpumask_set_cpu(cpu, desc->percpu_enabled); | |
261 | } | |
262 | ||
263 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | |
264 | { | |
265 | if (desc->irq_data.chip->irq_disable) | |
266 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
267 | else | |
268 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
269 | cpumask_clear_cpu(cpu, desc->percpu_enabled); | |
270 | } | |
271 | ||
9205e31d | 272 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 273 | { |
9205e31d TG |
274 | if (desc->irq_data.chip->irq_mask_ack) |
275 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 276 | else { |
e2c0f8ff | 277 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
278 | if (desc->irq_data.chip->irq_ack) |
279 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 280 | } |
6e40262e | 281 | irq_state_set_masked(desc); |
0b1adaa0 TG |
282 | } |
283 | ||
d4d5e089 | 284 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 285 | { |
e2c0f8ff TG |
286 | if (desc->irq_data.chip->irq_mask) { |
287 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 288 | irq_state_set_masked(desc); |
0b1adaa0 TG |
289 | } |
290 | } | |
291 | ||
d4d5e089 | 292 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 293 | { |
0eda58b7 TG |
294 | if (desc->irq_data.chip->irq_unmask) { |
295 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 296 | irq_state_clr_masked(desc); |
0b1adaa0 | 297 | } |
dd87eb3a TG |
298 | } |
299 | ||
328a4978 TG |
300 | void unmask_threaded_irq(struct irq_desc *desc) |
301 | { | |
302 | struct irq_chip *chip = desc->irq_data.chip; | |
303 | ||
304 | if (chip->flags & IRQCHIP_EOI_THREADED) | |
305 | chip->irq_eoi(&desc->irq_data); | |
306 | ||
307 | if (chip->irq_unmask) { | |
308 | chip->irq_unmask(&desc->irq_data); | |
309 | irq_state_clr_masked(desc); | |
310 | } | |
311 | } | |
312 | ||
399b5da2 TG |
313 | /* |
314 | * handle_nested_irq - Handle a nested irq from a irq thread | |
315 | * @irq: the interrupt number | |
316 | * | |
317 | * Handle interrupts which are nested into a threaded interrupt | |
318 | * handler. The handler function is called inside the calling | |
319 | * threads context. | |
320 | */ | |
321 | void handle_nested_irq(unsigned int irq) | |
322 | { | |
323 | struct irq_desc *desc = irq_to_desc(irq); | |
324 | struct irqaction *action; | |
325 | irqreturn_t action_ret; | |
326 | ||
327 | might_sleep(); | |
328 | ||
239007b8 | 329 | raw_spin_lock_irq(&desc->lock); |
399b5da2 | 330 | |
293a7a0a | 331 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
b51bf95c | 332 | kstat_incr_irqs_this_cpu(desc); |
399b5da2 TG |
333 | |
334 | action = desc->action; | |
23812b9d NJ |
335 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
336 | desc->istate |= IRQS_PENDING; | |
399b5da2 | 337 | goto out_unlock; |
23812b9d | 338 | } |
399b5da2 | 339 | |
32f4125e | 340 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 341 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
342 | |
343 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
344 | if (!noirqdebug) | |
0dcdbc97 | 345 | note_interrupt(desc, action_ret); |
399b5da2 | 346 | |
239007b8 | 347 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 348 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
349 | |
350 | out_unlock: | |
239007b8 | 351 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
352 | } |
353 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
354 | ||
fe200ae4 TG |
355 | static bool irq_check_poll(struct irq_desc *desc) |
356 | { | |
6954b75b | 357 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
358 | return false; |
359 | return irq_wait_for_poll(desc); | |
360 | } | |
361 | ||
c7bd3ec0 TG |
362 | static bool irq_may_run(struct irq_desc *desc) |
363 | { | |
9ce7a258 TG |
364 | unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; |
365 | ||
366 | /* | |
367 | * If the interrupt is not in progress and is not an armed | |
368 | * wakeup interrupt, proceed. | |
369 | */ | |
370 | if (!irqd_has_set(&desc->irq_data, mask)) | |
c7bd3ec0 | 371 | return true; |
9ce7a258 TG |
372 | |
373 | /* | |
374 | * If the interrupt is an armed wakeup source, mark it pending | |
375 | * and suspended, disable it and notify the pm core about the | |
376 | * event. | |
377 | */ | |
378 | if (irq_pm_check_wakeup(desc)) | |
379 | return false; | |
380 | ||
381 | /* | |
382 | * Handle a potential concurrent poll on a different core. | |
383 | */ | |
c7bd3ec0 TG |
384 | return irq_check_poll(desc); |
385 | } | |
386 | ||
dd87eb3a TG |
387 | /** |
388 | * handle_simple_irq - Simple and software-decoded IRQs. | |
dd87eb3a | 389 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
390 | * |
391 | * Simple interrupts are either sent from a demultiplexing interrupt | |
392 | * handler or come from hardware, where no interrupt hardware control | |
393 | * is necessary. | |
394 | * | |
395 | * Note: The caller is expected to handle the ack, clear, mask and | |
396 | * unmask issues if necessary. | |
397 | */ | |
bd0b9ac4 | 398 | void handle_simple_irq(struct irq_desc *desc) |
dd87eb3a | 399 | { |
239007b8 | 400 | raw_spin_lock(&desc->lock); |
dd87eb3a | 401 | |
c7bd3ec0 TG |
402 | if (!irq_may_run(desc)) |
403 | goto out_unlock; | |
fe200ae4 | 404 | |
163ef309 | 405 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
b51bf95c | 406 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a | 407 | |
23812b9d NJ |
408 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
409 | desc->istate |= IRQS_PENDING; | |
dd87eb3a | 410 | goto out_unlock; |
23812b9d | 411 | } |
dd87eb3a | 412 | |
107781e7 | 413 | handle_irq_event(desc); |
dd87eb3a | 414 | |
dd87eb3a | 415 | out_unlock: |
239007b8 | 416 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 417 | } |
edf76f83 | 418 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
dd87eb3a | 419 | |
ac563761 TG |
420 | /* |
421 | * Called unconditionally from handle_level_irq() and only for oneshot | |
422 | * interrupts from handle_fasteoi_irq() | |
423 | */ | |
424 | static void cond_unmask_irq(struct irq_desc *desc) | |
425 | { | |
426 | /* | |
427 | * We need to unmask in the following cases: | |
428 | * - Standard level irq (IRQF_ONESHOT is not set) | |
429 | * - Oneshot irq which did not wake the thread (caused by a | |
430 | * spurious interrupt or a primary handler handling it | |
431 | * completely). | |
432 | */ | |
433 | if (!irqd_irq_disabled(&desc->irq_data) && | |
434 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | |
435 | unmask_irq(desc); | |
436 | } | |
437 | ||
dd87eb3a TG |
438 | /** |
439 | * handle_level_irq - Level type irq handler | |
dd87eb3a | 440 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
441 | * |
442 | * Level type interrupts are active as long as the hardware line has | |
443 | * the active level. This may require to mask the interrupt and unmask | |
444 | * it after the associated handler has acknowledged the device, so the | |
445 | * interrupt line is back to inactive. | |
446 | */ | |
bd0b9ac4 | 447 | void handle_level_irq(struct irq_desc *desc) |
dd87eb3a | 448 | { |
239007b8 | 449 | raw_spin_lock(&desc->lock); |
9205e31d | 450 | mask_ack_irq(desc); |
dd87eb3a | 451 | |
c7bd3ec0 TG |
452 | if (!irq_may_run(desc)) |
453 | goto out_unlock; | |
fe200ae4 | 454 | |
163ef309 | 455 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
b51bf95c | 456 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a TG |
457 | |
458 | /* | |
459 | * If its disabled or no action available | |
460 | * keep it masked and get out of here | |
461 | */ | |
d4dc0f90 TG |
462 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
463 | desc->istate |= IRQS_PENDING; | |
86998aa6 | 464 | goto out_unlock; |
d4dc0f90 | 465 | } |
dd87eb3a | 466 | |
1529866c | 467 | handle_irq_event(desc); |
b25c340c | 468 | |
ac563761 TG |
469 | cond_unmask_irq(desc); |
470 | ||
86998aa6 | 471 | out_unlock: |
239007b8 | 472 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 473 | } |
14819ea1 | 474 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 475 | |
78129576 TG |
476 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
477 | static inline void preflow_handler(struct irq_desc *desc) | |
478 | { | |
479 | if (desc->preflow_handler) | |
480 | desc->preflow_handler(&desc->irq_data); | |
481 | } | |
482 | #else | |
483 | static inline void preflow_handler(struct irq_desc *desc) { } | |
484 | #endif | |
485 | ||
328a4978 TG |
486 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
487 | { | |
488 | if (!(desc->istate & IRQS_ONESHOT)) { | |
489 | chip->irq_eoi(&desc->irq_data); | |
490 | return; | |
491 | } | |
492 | /* | |
493 | * We need to unmask in the following cases: | |
494 | * - Oneshot irq which did not wake the thread (caused by a | |
495 | * spurious interrupt or a primary handler handling it | |
496 | * completely). | |
497 | */ | |
498 | if (!irqd_irq_disabled(&desc->irq_data) && | |
499 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { | |
500 | chip->irq_eoi(&desc->irq_data); | |
501 | unmask_irq(desc); | |
502 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { | |
503 | chip->irq_eoi(&desc->irq_data); | |
504 | } | |
505 | } | |
506 | ||
dd87eb3a | 507 | /** |
47c2a3aa | 508 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a | 509 | * @desc: the interrupt description structure for this irq |
dd87eb3a | 510 | * |
47c2a3aa | 511 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
512 | * call when the interrupt has been serviced. This enables support |
513 | * for modern forms of interrupt handlers, which handle the flow | |
514 | * details in hardware, transparently. | |
515 | */ | |
bd0b9ac4 | 516 | void handle_fasteoi_irq(struct irq_desc *desc) |
dd87eb3a | 517 | { |
328a4978 TG |
518 | struct irq_chip *chip = desc->irq_data.chip; |
519 | ||
239007b8 | 520 | raw_spin_lock(&desc->lock); |
dd87eb3a | 521 | |
c7bd3ec0 TG |
522 | if (!irq_may_run(desc)) |
523 | goto out; | |
dd87eb3a | 524 | |
163ef309 | 525 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
b51bf95c | 526 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a TG |
527 | |
528 | /* | |
529 | * If its disabled or no action available | |
76d21601 | 530 | * then mask it and get out of here: |
dd87eb3a | 531 | */ |
32f4125e | 532 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 533 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 534 | mask_irq(desc); |
dd87eb3a | 535 | goto out; |
98bb244b | 536 | } |
c69e3758 TG |
537 | |
538 | if (desc->istate & IRQS_ONESHOT) | |
539 | mask_irq(desc); | |
540 | ||
78129576 | 541 | preflow_handler(desc); |
a7ae4de5 | 542 | handle_irq_event(desc); |
77694b40 | 543 | |
328a4978 | 544 | cond_unmask_eoi_irq(desc, chip); |
ac563761 | 545 | |
239007b8 | 546 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
547 | return; |
548 | out: | |
328a4978 TG |
549 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
550 | chip->irq_eoi(&desc->irq_data); | |
551 | raw_spin_unlock(&desc->lock); | |
dd87eb3a | 552 | } |
7cad45ee | 553 | EXPORT_SYMBOL_GPL(handle_fasteoi_irq); |
dd87eb3a TG |
554 | |
555 | /** | |
556 | * handle_edge_irq - edge type IRQ handler | |
dd87eb3a | 557 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
558 | * |
559 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 560 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
561 | * and must be acked in order to be reenabled. After the ack another |
562 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 563 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
564 | * might be necessary to disable (mask) the interrupt depending on the |
565 | * controller hardware. This requires to reenable the interrupt inside | |
566 | * of the loop which handles the interrupts which have arrived while | |
567 | * the handler was running. If all pending interrupts are handled, the | |
568 | * loop is left. | |
569 | */ | |
bd0b9ac4 | 570 | void handle_edge_irq(struct irq_desc *desc) |
dd87eb3a | 571 | { |
239007b8 | 572 | raw_spin_lock(&desc->lock); |
dd87eb3a | 573 | |
163ef309 | 574 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
c3d7acd0 | 575 | |
c7bd3ec0 TG |
576 | if (!irq_may_run(desc)) { |
577 | desc->istate |= IRQS_PENDING; | |
578 | mask_ack_irq(desc); | |
579 | goto out_unlock; | |
dd87eb3a | 580 | } |
c3d7acd0 | 581 | |
dd87eb3a | 582 | /* |
c3d7acd0 TG |
583 | * If its disabled or no action available then mask it and get |
584 | * out of here. | |
dd87eb3a | 585 | */ |
c3d7acd0 TG |
586 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
587 | desc->istate |= IRQS_PENDING; | |
588 | mask_ack_irq(desc); | |
589 | goto out_unlock; | |
dd87eb3a | 590 | } |
c3d7acd0 | 591 | |
b51bf95c | 592 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a TG |
593 | |
594 | /* Start handling the irq */ | |
22a49163 | 595 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 596 | |
dd87eb3a | 597 | do { |
a60a5dc2 | 598 | if (unlikely(!desc->action)) { |
e2c0f8ff | 599 | mask_irq(desc); |
dd87eb3a TG |
600 | goto out_unlock; |
601 | } | |
602 | ||
603 | /* | |
604 | * When another irq arrived while we were handling | |
605 | * one, we could have masked the irq. | |
606 | * Renable it, if it was not disabled in meantime. | |
607 | */ | |
2a0d6fb3 | 608 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
609 | if (!irqd_irq_disabled(&desc->irq_data) && |
610 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 611 | unmask_irq(desc); |
dd87eb3a TG |
612 | } |
613 | ||
a60a5dc2 | 614 | handle_irq_event(desc); |
dd87eb3a | 615 | |
2a0d6fb3 | 616 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 617 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 618 | |
dd87eb3a | 619 | out_unlock: |
239007b8 | 620 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 621 | } |
3911ff30 | 622 | EXPORT_SYMBOL(handle_edge_irq); |
dd87eb3a | 623 | |
0521c8fb TG |
624 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
625 | /** | |
626 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
0521c8fb TG |
627 | * @desc: the interrupt description structure for this irq |
628 | * | |
629 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
630 | * mask/unmask logic. | |
631 | */ | |
bd0b9ac4 | 632 | void handle_edge_eoi_irq(struct irq_desc *desc) |
0521c8fb TG |
633 | { |
634 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
635 | ||
636 | raw_spin_lock(&desc->lock); | |
637 | ||
638 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
c3d7acd0 | 639 | |
c7bd3ec0 TG |
640 | if (!irq_may_run(desc)) { |
641 | desc->istate |= IRQS_PENDING; | |
642 | goto out_eoi; | |
0521c8fb | 643 | } |
c3d7acd0 | 644 | |
0521c8fb | 645 | /* |
c3d7acd0 TG |
646 | * If its disabled or no action available then mask it and get |
647 | * out of here. | |
0521c8fb | 648 | */ |
c3d7acd0 TG |
649 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
650 | desc->istate |= IRQS_PENDING; | |
651 | goto out_eoi; | |
0521c8fb | 652 | } |
c3d7acd0 | 653 | |
b51bf95c | 654 | kstat_incr_irqs_this_cpu(desc); |
0521c8fb TG |
655 | |
656 | do { | |
657 | if (unlikely(!desc->action)) | |
658 | goto out_eoi; | |
659 | ||
660 | handle_irq_event(desc); | |
661 | ||
662 | } while ((desc->istate & IRQS_PENDING) && | |
663 | !irqd_irq_disabled(&desc->irq_data)); | |
664 | ||
ac0e0447 | 665 | out_eoi: |
0521c8fb TG |
666 | chip->irq_eoi(&desc->irq_data); |
667 | raw_spin_unlock(&desc->lock); | |
668 | } | |
669 | #endif | |
670 | ||
dd87eb3a | 671 | /** |
24b26d42 | 672 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a | 673 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
674 | * |
675 | * Per CPU interrupts on SMP machines without locking requirements | |
676 | */ | |
bd0b9ac4 | 677 | void handle_percpu_irq(struct irq_desc *desc) |
dd87eb3a | 678 | { |
35e857cb | 679 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 680 | |
b51bf95c | 681 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a | 682 | |
849f061c TG |
683 | if (chip->irq_ack) |
684 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 685 | |
71f64340 | 686 | handle_irq_event_percpu(desc); |
dd87eb3a | 687 | |
849f061c TG |
688 | if (chip->irq_eoi) |
689 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
690 | } |
691 | ||
31d9d9b6 MZ |
692 | /** |
693 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | |
31d9d9b6 MZ |
694 | * @desc: the interrupt description structure for this irq |
695 | * | |
696 | * Per CPU interrupts on SMP machines without locking requirements. Same as | |
697 | * handle_percpu_irq() above but with the following extras: | |
698 | * | |
699 | * action->percpu_dev_id is a pointer to percpu variables which | |
700 | * contain the real device id for the cpu on which this handler is | |
701 | * called | |
702 | */ | |
bd0b9ac4 | 703 | void handle_percpu_devid_irq(struct irq_desc *desc) |
31d9d9b6 MZ |
704 | { |
705 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
706 | struct irqaction *action = desc->action; | |
532d0d06 | 707 | void *dev_id = raw_cpu_ptr(action->percpu_dev_id); |
bd0b9ac4 | 708 | unsigned int irq = irq_desc_get_irq(desc); |
31d9d9b6 MZ |
709 | irqreturn_t res; |
710 | ||
b51bf95c | 711 | kstat_incr_irqs_this_cpu(desc); |
31d9d9b6 MZ |
712 | |
713 | if (chip->irq_ack) | |
714 | chip->irq_ack(&desc->irq_data); | |
715 | ||
716 | trace_irq_handler_entry(irq, action); | |
717 | res = action->handler(irq, dev_id); | |
718 | trace_irq_handler_exit(irq, action, res); | |
719 | ||
720 | if (chip->irq_eoi) | |
721 | chip->irq_eoi(&desc->irq_data); | |
722 | } | |
723 | ||
dd87eb3a | 724 | void |
3b0f95be RK |
725 | __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle, |
726 | int is_chained, const char *name) | |
dd87eb3a | 727 | { |
091738a2 | 728 | if (!handle) { |
dd87eb3a | 729 | handle = handle_bad_irq; |
091738a2 | 730 | } else { |
f86eff22 MZ |
731 | struct irq_data *irq_data = &desc->irq_data; |
732 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
733 | /* | |
734 | * With hierarchical domains we might run into a | |
735 | * situation where the outermost chip is not yet set | |
736 | * up, but the inner chips are there. Instead of | |
737 | * bailing we install the handler, but obviously we | |
738 | * cannot enable/startup the interrupt at this point. | |
739 | */ | |
740 | while (irq_data) { | |
741 | if (irq_data->chip != &no_irq_chip) | |
742 | break; | |
743 | /* | |
744 | * Bail out if the outer chip is not set up | |
745 | * and the interrrupt supposed to be started | |
746 | * right away. | |
747 | */ | |
748 | if (WARN_ON(is_chained)) | |
3b0f95be | 749 | return; |
f86eff22 MZ |
750 | /* Try the parent */ |
751 | irq_data = irq_data->parent_data; | |
752 | } | |
753 | #endif | |
754 | if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip)) | |
3b0f95be | 755 | return; |
f8b5473f | 756 | } |
dd87eb3a | 757 | |
dd87eb3a TG |
758 | /* Uninstall? */ |
759 | if (handle == handle_bad_irq) { | |
6b8ff312 | 760 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 761 | mask_ack_irq(desc); |
801a0e9a | 762 | irq_state_set_disabled(desc); |
e509bd7d MW |
763 | if (is_chained) |
764 | desc->action = NULL; | |
dd87eb3a TG |
765 | desc->depth = 1; |
766 | } | |
767 | desc->handle_irq = handle; | |
a460e745 | 768 | desc->name = name; |
dd87eb3a TG |
769 | |
770 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
771 | irq_settings_set_noprobe(desc); |
772 | irq_settings_set_norequest(desc); | |
7f1b1244 | 773 | irq_settings_set_nothread(desc); |
e509bd7d | 774 | desc->action = &chained_action; |
b4bc724e | 775 | irq_startup(desc, true); |
dd87eb3a | 776 | } |
3b0f95be RK |
777 | } |
778 | ||
779 | void | |
780 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | |
781 | const char *name) | |
782 | { | |
783 | unsigned long flags; | |
784 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
785 | ||
786 | if (!desc) | |
787 | return; | |
788 | ||
789 | __irq_do_set_handler(desc, handle, is_chained, name); | |
02725e74 | 790 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a | 791 | } |
3836ca08 | 792 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a | 793 | |
3b0f95be RK |
794 | void |
795 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
796 | void *data) | |
797 | { | |
798 | unsigned long flags; | |
799 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
800 | ||
801 | if (!desc) | |
802 | return; | |
803 | ||
804 | __irq_do_set_handler(desc, handle, 1, NULL); | |
af7080e0 | 805 | desc->irq_common_data.handler_data = data; |
3b0f95be RK |
806 | |
807 | irq_put_desc_busunlock(desc, flags); | |
808 | } | |
809 | EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data); | |
810 | ||
dd87eb3a | 811 | void |
3836ca08 | 812 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 813 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 814 | { |
35e857cb | 815 | irq_set_chip(irq, chip); |
3836ca08 | 816 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 817 | } |
b3ae66f2 | 818 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
46f4f8f6 | 819 | |
44247184 | 820 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 821 | { |
46f4f8f6 | 822 | unsigned long flags; |
31d9d9b6 | 823 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
46f4f8f6 | 824 | |
44247184 | 825 | if (!desc) |
46f4f8f6 | 826 | return; |
a005677b TG |
827 | irq_settings_clr_and_set(desc, clr, set); |
828 | ||
876dbd4c | 829 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 830 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
831 | if (irq_settings_has_no_balance_set(desc)) |
832 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
833 | if (irq_settings_is_per_cpu(desc)) | |
834 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
835 | if (irq_settings_can_move_pcntxt(desc)) |
836 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
837 | if (irq_settings_is_level(desc)) |
838 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 839 | |
876dbd4c TG |
840 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
841 | ||
02725e74 | 842 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 843 | } |
edf76f83 | 844 | EXPORT_SYMBOL_GPL(irq_modify_status); |
0fdb4b25 DD |
845 | |
846 | /** | |
847 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
848 | * | |
849 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
850 | * for each. | |
851 | */ | |
852 | void irq_cpu_online(void) | |
853 | { | |
854 | struct irq_desc *desc; | |
855 | struct irq_chip *chip; | |
856 | unsigned long flags; | |
857 | unsigned int irq; | |
858 | ||
859 | for_each_active_irq(irq) { | |
860 | desc = irq_to_desc(irq); | |
861 | if (!desc) | |
862 | continue; | |
863 | ||
864 | raw_spin_lock_irqsave(&desc->lock, flags); | |
865 | ||
866 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
867 | if (chip && chip->irq_cpu_online && |
868 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 869 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
870 | chip->irq_cpu_online(&desc->irq_data); |
871 | ||
872 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
873 | } | |
874 | } | |
875 | ||
876 | /** | |
877 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
878 | * | |
879 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
880 | * for each. | |
881 | */ | |
882 | void irq_cpu_offline(void) | |
883 | { | |
884 | struct irq_desc *desc; | |
885 | struct irq_chip *chip; | |
886 | unsigned long flags; | |
887 | unsigned int irq; | |
888 | ||
889 | for_each_active_irq(irq) { | |
890 | desc = irq_to_desc(irq); | |
891 | if (!desc) | |
892 | continue; | |
893 | ||
894 | raw_spin_lock_irqsave(&desc->lock, flags); | |
895 | ||
896 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
897 | if (chip && chip->irq_cpu_offline && |
898 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 899 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
900 | chip->irq_cpu_offline(&desc->irq_data); |
901 | ||
902 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
903 | } | |
904 | } | |
85f08c17 JL |
905 | |
906 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
3cfeffc2 SA |
907 | /** |
908 | * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if | |
909 | * NULL) | |
910 | * @data: Pointer to interrupt specific data | |
911 | */ | |
912 | void irq_chip_enable_parent(struct irq_data *data) | |
913 | { | |
914 | data = data->parent_data; | |
915 | if (data->chip->irq_enable) | |
916 | data->chip->irq_enable(data); | |
917 | else | |
918 | data->chip->irq_unmask(data); | |
919 | } | |
920 | ||
921 | /** | |
922 | * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if | |
923 | * NULL) | |
924 | * @data: Pointer to interrupt specific data | |
925 | */ | |
926 | void irq_chip_disable_parent(struct irq_data *data) | |
927 | { | |
928 | data = data->parent_data; | |
929 | if (data->chip->irq_disable) | |
930 | data->chip->irq_disable(data); | |
931 | else | |
932 | data->chip->irq_mask(data); | |
933 | } | |
934 | ||
85f08c17 JL |
935 | /** |
936 | * irq_chip_ack_parent - Acknowledge the parent interrupt | |
937 | * @data: Pointer to interrupt specific data | |
938 | */ | |
939 | void irq_chip_ack_parent(struct irq_data *data) | |
940 | { | |
941 | data = data->parent_data; | |
942 | data->chip->irq_ack(data); | |
943 | } | |
944 | ||
56e8abab YC |
945 | /** |
946 | * irq_chip_mask_parent - Mask the parent interrupt | |
947 | * @data: Pointer to interrupt specific data | |
948 | */ | |
949 | void irq_chip_mask_parent(struct irq_data *data) | |
950 | { | |
951 | data = data->parent_data; | |
952 | data->chip->irq_mask(data); | |
953 | } | |
954 | ||
955 | /** | |
956 | * irq_chip_unmask_parent - Unmask the parent interrupt | |
957 | * @data: Pointer to interrupt specific data | |
958 | */ | |
959 | void irq_chip_unmask_parent(struct irq_data *data) | |
960 | { | |
961 | data = data->parent_data; | |
962 | data->chip->irq_unmask(data); | |
963 | } | |
964 | ||
965 | /** | |
966 | * irq_chip_eoi_parent - Invoke EOI on the parent interrupt | |
967 | * @data: Pointer to interrupt specific data | |
968 | */ | |
969 | void irq_chip_eoi_parent(struct irq_data *data) | |
970 | { | |
971 | data = data->parent_data; | |
972 | data->chip->irq_eoi(data); | |
973 | } | |
974 | ||
975 | /** | |
976 | * irq_chip_set_affinity_parent - Set affinity on the parent interrupt | |
977 | * @data: Pointer to interrupt specific data | |
978 | * @dest: The affinity mask to set | |
979 | * @force: Flag to enforce setting (disable online checks) | |
980 | * | |
981 | * Conditinal, as the underlying parent chip might not implement it. | |
982 | */ | |
983 | int irq_chip_set_affinity_parent(struct irq_data *data, | |
984 | const struct cpumask *dest, bool force) | |
985 | { | |
986 | data = data->parent_data; | |
987 | if (data->chip->irq_set_affinity) | |
988 | return data->chip->irq_set_affinity(data, dest, force); | |
b7560de1 GS |
989 | |
990 | return -ENOSYS; | |
991 | } | |
992 | ||
993 | /** | |
994 | * irq_chip_set_type_parent - Set IRQ type on the parent interrupt | |
995 | * @data: Pointer to interrupt specific data | |
996 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | |
997 | * | |
998 | * Conditional, as the underlying parent chip might not implement it. | |
999 | */ | |
1000 | int irq_chip_set_type_parent(struct irq_data *data, unsigned int type) | |
1001 | { | |
1002 | data = data->parent_data; | |
1003 | ||
1004 | if (data->chip->irq_set_type) | |
1005 | return data->chip->irq_set_type(data, type); | |
56e8abab YC |
1006 | |
1007 | return -ENOSYS; | |
1008 | } | |
1009 | ||
85f08c17 JL |
1010 | /** |
1011 | * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware | |
1012 | * @data: Pointer to interrupt specific data | |
1013 | * | |
1014 | * Iterate through the domain hierarchy of the interrupt and check | |
1015 | * whether a hw retrigger function exists. If yes, invoke it. | |
1016 | */ | |
1017 | int irq_chip_retrigger_hierarchy(struct irq_data *data) | |
1018 | { | |
1019 | for (data = data->parent_data; data; data = data->parent_data) | |
1020 | if (data->chip && data->chip->irq_retrigger) | |
1021 | return data->chip->irq_retrigger(data); | |
1022 | ||
6d4affea | 1023 | return 0; |
85f08c17 | 1024 | } |
08b55e2a | 1025 | |
0a4377de JL |
1026 | /** |
1027 | * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt | |
1028 | * @data: Pointer to interrupt specific data | |
8505a81b | 1029 | * @vcpu_info: The vcpu affinity information |
0a4377de JL |
1030 | */ |
1031 | int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info) | |
1032 | { | |
1033 | data = data->parent_data; | |
1034 | if (data->chip->irq_set_vcpu_affinity) | |
1035 | return data->chip->irq_set_vcpu_affinity(data, vcpu_info); | |
1036 | ||
1037 | return -ENOSYS; | |
1038 | } | |
1039 | ||
08b55e2a MZ |
1040 | /** |
1041 | * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt | |
1042 | * @data: Pointer to interrupt specific data | |
1043 | * @on: Whether to set or reset the wake-up capability of this irq | |
1044 | * | |
1045 | * Conditional, as the underlying parent chip might not implement it. | |
1046 | */ | |
1047 | int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on) | |
1048 | { | |
1049 | data = data->parent_data; | |
1050 | if (data->chip->irq_set_wake) | |
1051 | return data->chip->irq_set_wake(data, on); | |
1052 | ||
1053 | return -ENOSYS; | |
1054 | } | |
85f08c17 | 1055 | #endif |
515085ef JL |
1056 | |
1057 | /** | |
1058 | * irq_chip_compose_msi_msg - Componse msi message for a irq chip | |
1059 | * @data: Pointer to interrupt specific data | |
1060 | * @msg: Pointer to the MSI message | |
1061 | * | |
1062 | * For hierarchical domains we find the first chip in the hierarchy | |
1063 | * which implements the irq_compose_msi_msg callback. For non | |
1064 | * hierarchical we use the top level chip. | |
1065 | */ | |
1066 | int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) | |
1067 | { | |
1068 | struct irq_data *pos = NULL; | |
1069 | ||
1070 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1071 | for (; data; data = data->parent_data) | |
1072 | #endif | |
1073 | if (data->chip && data->chip->irq_compose_msi_msg) | |
1074 | pos = data; | |
1075 | if (!pos) | |
1076 | return -ENOSYS; | |
1077 | ||
1078 | pos->chip->irq_compose_msi_msg(pos, msg); | |
1079 | ||
1080 | return 0; | |
1081 | } |