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3795de23 TG |
1 | /* |
2 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
3 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
4 | * | |
5 | * This file contains the interrupt descriptor management code | |
6 | * | |
7 | * Detailed information is available in Documentation/DocBook/genericirq | |
8 | * | |
9 | */ | |
10 | #include <linux/irq.h> | |
11 | #include <linux/slab.h> | |
ec53cf23 | 12 | #include <linux/export.h> |
3795de23 TG |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/radix-tree.h> | |
1f5a5b87 | 16 | #include <linux/bitmap.h> |
76ba59f8 | 17 | #include <linux/irqdomain.h> |
3795de23 TG |
18 | |
19 | #include "internals.h" | |
20 | ||
21 | /* | |
22 | * lockdep: we want to handle all irq_desc locks as a single lock-class: | |
23 | */ | |
78f90d91 | 24 | static struct lock_class_key irq_desc_lock_class; |
3795de23 | 25 | |
fe051434 | 26 | #if defined(CONFIG_SMP) |
3795de23 TG |
27 | static void __init init_irq_default_affinity(void) |
28 | { | |
29 | alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT); | |
30 | cpumask_setall(irq_default_affinity); | |
31 | } | |
32 | #else | |
33 | static void __init init_irq_default_affinity(void) | |
34 | { | |
35 | } | |
36 | #endif | |
37 | ||
1f5a5b87 TG |
38 | #ifdef CONFIG_SMP |
39 | static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) | |
40 | { | |
9df872fa JL |
41 | if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, |
42 | gfp, node)) | |
1f5a5b87 TG |
43 | return -ENOMEM; |
44 | ||
45 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
46 | if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) { | |
9df872fa | 47 | free_cpumask_var(desc->irq_common_data.affinity); |
1f5a5b87 TG |
48 | return -ENOMEM; |
49 | } | |
50 | #endif | |
51 | return 0; | |
52 | } | |
53 | ||
54 | static void desc_smp_init(struct irq_desc *desc, int node) | |
55 | { | |
9df872fa | 56 | cpumask_copy(desc->irq_common_data.affinity, irq_default_affinity); |
b7b29338 TG |
57 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
58 | cpumask_clear(desc->pending_mask); | |
59 | #endif | |
449e9cae JL |
60 | #ifdef CONFIG_NUMA |
61 | desc->irq_common_data.node = node; | |
62 | #endif | |
b7b29338 TG |
63 | } |
64 | ||
1f5a5b87 TG |
65 | #else |
66 | static inline int | |
67 | alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; } | |
68 | static inline void desc_smp_init(struct irq_desc *desc, int node) { } | |
69 | #endif | |
70 | ||
b6873807 SAS |
71 | static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, |
72 | struct module *owner) | |
1f5a5b87 | 73 | { |
6c9ae009 ED |
74 | int cpu; |
75 | ||
af7080e0 JL |
76 | desc->irq_common_data.handler_data = NULL; |
77 | ||
0d0b4c86 | 78 | desc->irq_data.common = &desc->irq_common_data; |
1f5a5b87 TG |
79 | desc->irq_data.irq = irq; |
80 | desc->irq_data.chip = &no_irq_chip; | |
81 | desc->irq_data.chip_data = NULL; | |
1f5a5b87 | 82 | desc->irq_data.msi_desc = NULL; |
f9e4989e | 83 | irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); |
801a0e9a | 84 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
1f5a5b87 TG |
85 | desc->handle_irq = handle_bad_irq; |
86 | desc->depth = 1; | |
b7b29338 TG |
87 | desc->irq_count = 0; |
88 | desc->irqs_unhandled = 0; | |
1f5a5b87 | 89 | desc->name = NULL; |
b6873807 | 90 | desc->owner = owner; |
6c9ae009 ED |
91 | for_each_possible_cpu(cpu) |
92 | *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; | |
1f5a5b87 TG |
93 | desc_smp_init(desc, node); |
94 | } | |
95 | ||
3795de23 TG |
96 | int nr_irqs = NR_IRQS; |
97 | EXPORT_SYMBOL_GPL(nr_irqs); | |
98 | ||
a05a900a | 99 | static DEFINE_MUTEX(sparse_irq_lock); |
c1ee6264 | 100 | static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); |
1f5a5b87 | 101 | |
3795de23 TG |
102 | #ifdef CONFIG_SPARSE_IRQ |
103 | ||
baa0d233 | 104 | static RADIX_TREE(irq_desc_tree, GFP_KERNEL); |
3795de23 | 105 | |
1f5a5b87 | 106 | static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) |
3795de23 TG |
107 | { |
108 | radix_tree_insert(&irq_desc_tree, irq, desc); | |
109 | } | |
110 | ||
111 | struct irq_desc *irq_to_desc(unsigned int irq) | |
112 | { | |
113 | return radix_tree_lookup(&irq_desc_tree, irq); | |
114 | } | |
3911ff30 | 115 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 116 | |
1f5a5b87 TG |
117 | static void delete_irq_desc(unsigned int irq) |
118 | { | |
119 | radix_tree_delete(&irq_desc_tree, irq); | |
120 | } | |
121 | ||
122 | #ifdef CONFIG_SMP | |
123 | static void free_masks(struct irq_desc *desc) | |
124 | { | |
125 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
126 | free_cpumask_var(desc->pending_mask); | |
127 | #endif | |
9df872fa | 128 | free_cpumask_var(desc->irq_common_data.affinity); |
1f5a5b87 TG |
129 | } |
130 | #else | |
131 | static inline void free_masks(struct irq_desc *desc) { } | |
132 | #endif | |
133 | ||
c291ee62 TG |
134 | void irq_lock_sparse(void) |
135 | { | |
136 | mutex_lock(&sparse_irq_lock); | |
137 | } | |
138 | ||
139 | void irq_unlock_sparse(void) | |
140 | { | |
141 | mutex_unlock(&sparse_irq_lock); | |
142 | } | |
143 | ||
b6873807 | 144 | static struct irq_desc *alloc_desc(int irq, int node, struct module *owner) |
1f5a5b87 TG |
145 | { |
146 | struct irq_desc *desc; | |
baa0d233 | 147 | gfp_t gfp = GFP_KERNEL; |
1f5a5b87 TG |
148 | |
149 | desc = kzalloc_node(sizeof(*desc), gfp, node); | |
150 | if (!desc) | |
151 | return NULL; | |
152 | /* allocate based on nr_cpu_ids */ | |
6c9ae009 | 153 | desc->kstat_irqs = alloc_percpu(unsigned int); |
1f5a5b87 TG |
154 | if (!desc->kstat_irqs) |
155 | goto err_desc; | |
156 | ||
157 | if (alloc_masks(desc, gfp, node)) | |
158 | goto err_kstat; | |
159 | ||
160 | raw_spin_lock_init(&desc->lock); | |
161 | lockdep_set_class(&desc->lock, &irq_desc_lock_class); | |
162 | ||
b6873807 | 163 | desc_set_defaults(irq, desc, node, owner); |
1f5a5b87 TG |
164 | |
165 | return desc; | |
166 | ||
167 | err_kstat: | |
6c9ae009 | 168 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
169 | err_desc: |
170 | kfree(desc); | |
171 | return NULL; | |
172 | } | |
173 | ||
174 | static void free_desc(unsigned int irq) | |
175 | { | |
176 | struct irq_desc *desc = irq_to_desc(irq); | |
1f5a5b87 | 177 | |
13bfe99e TG |
178 | unregister_irq_proc(irq, desc); |
179 | ||
c291ee62 TG |
180 | /* |
181 | * sparse_irq_lock protects also show_interrupts() and | |
182 | * kstat_irq_usr(). Once we deleted the descriptor from the | |
183 | * sparse tree we can free it. Access in proc will fail to | |
184 | * lookup the descriptor. | |
185 | */ | |
a05a900a | 186 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 187 | delete_irq_desc(irq); |
a05a900a | 188 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
189 | |
190 | free_masks(desc); | |
6c9ae009 | 191 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
192 | kfree(desc); |
193 | } | |
194 | ||
b6873807 SAS |
195 | static int alloc_descs(unsigned int start, unsigned int cnt, int node, |
196 | struct module *owner) | |
1f5a5b87 TG |
197 | { |
198 | struct irq_desc *desc; | |
1f5a5b87 TG |
199 | int i; |
200 | ||
201 | for (i = 0; i < cnt; i++) { | |
b6873807 | 202 | desc = alloc_desc(start + i, node, owner); |
1f5a5b87 TG |
203 | if (!desc) |
204 | goto err; | |
a05a900a | 205 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 206 | irq_insert_desc(start + i, desc); |
a05a900a | 207 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
208 | } |
209 | return start; | |
210 | ||
211 | err: | |
212 | for (i--; i >= 0; i--) | |
213 | free_desc(start + i); | |
214 | ||
a05a900a | 215 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 216 | bitmap_clear(allocated_irqs, start, cnt); |
a05a900a | 217 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
218 | return -ENOMEM; |
219 | } | |
220 | ||
ed4dea6e | 221 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 | 222 | { |
ed4dea6e | 223 | if (nr > IRQ_BITMAP_BITS) |
e7bcecb7 | 224 | return -ENOMEM; |
ed4dea6e | 225 | nr_irqs = nr; |
e7bcecb7 TG |
226 | return 0; |
227 | } | |
228 | ||
3795de23 TG |
229 | int __init early_irq_init(void) |
230 | { | |
b683de2b | 231 | int i, initcnt, node = first_online_node; |
3795de23 | 232 | struct irq_desc *desc; |
3795de23 TG |
233 | |
234 | init_irq_default_affinity(); | |
235 | ||
b683de2b TG |
236 | /* Let arch update nr_irqs and return the nr of preallocated irqs */ |
237 | initcnt = arch_probe_nr_irqs(); | |
238 | printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt); | |
3795de23 | 239 | |
c1ee6264 TG |
240 | if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) |
241 | nr_irqs = IRQ_BITMAP_BITS; | |
242 | ||
243 | if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) | |
244 | initcnt = IRQ_BITMAP_BITS; | |
245 | ||
246 | if (initcnt > nr_irqs) | |
247 | nr_irqs = initcnt; | |
248 | ||
b683de2b | 249 | for (i = 0; i < initcnt; i++) { |
b6873807 | 250 | desc = alloc_desc(i, node, NULL); |
aa99ec0f TG |
251 | set_bit(i, allocated_irqs); |
252 | irq_insert_desc(i, desc); | |
3795de23 | 253 | } |
3795de23 TG |
254 | return arch_early_irq_init(); |
255 | } | |
256 | ||
3795de23 TG |
257 | #else /* !CONFIG_SPARSE_IRQ */ |
258 | ||
259 | struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { | |
260 | [0 ... NR_IRQS-1] = { | |
3795de23 TG |
261 | .handle_irq = handle_bad_irq, |
262 | .depth = 1, | |
263 | .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), | |
264 | } | |
265 | }; | |
266 | ||
3795de23 TG |
267 | int __init early_irq_init(void) |
268 | { | |
aa99ec0f | 269 | int count, i, node = first_online_node; |
3795de23 | 270 | struct irq_desc *desc; |
3795de23 TG |
271 | |
272 | init_irq_default_affinity(); | |
273 | ||
274 | printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS); | |
275 | ||
276 | desc = irq_desc; | |
277 | count = ARRAY_SIZE(irq_desc); | |
278 | ||
279 | for (i = 0; i < count; i++) { | |
6c9ae009 | 280 | desc[i].kstat_irqs = alloc_percpu(unsigned int); |
e7fbad30 LW |
281 | alloc_masks(&desc[i], GFP_KERNEL, node); |
282 | raw_spin_lock_init(&desc[i].lock); | |
154cd387 | 283 | lockdep_set_class(&desc[i].lock, &irq_desc_lock_class); |
b6873807 | 284 | desc_set_defaults(i, &desc[i], node, NULL); |
3795de23 TG |
285 | } |
286 | return arch_early_irq_init(); | |
287 | } | |
288 | ||
289 | struct irq_desc *irq_to_desc(unsigned int irq) | |
290 | { | |
291 | return (irq < NR_IRQS) ? irq_desc + irq : NULL; | |
292 | } | |
2c45aada | 293 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 294 | |
1f5a5b87 TG |
295 | static void free_desc(unsigned int irq) |
296 | { | |
d8179bc0 TG |
297 | struct irq_desc *desc = irq_to_desc(irq); |
298 | unsigned long flags; | |
299 | ||
300 | raw_spin_lock_irqsave(&desc->lock, flags); | |
6783011b | 301 | desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL); |
d8179bc0 | 302 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1f5a5b87 TG |
303 | } |
304 | ||
b6873807 SAS |
305 | static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, |
306 | struct module *owner) | |
1f5a5b87 | 307 | { |
b6873807 SAS |
308 | u32 i; |
309 | ||
310 | for (i = 0; i < cnt; i++) { | |
311 | struct irq_desc *desc = irq_to_desc(start + i); | |
312 | ||
313 | desc->owner = owner; | |
314 | } | |
1f5a5b87 TG |
315 | return start; |
316 | } | |
e7bcecb7 | 317 | |
ed4dea6e | 318 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 TG |
319 | { |
320 | return -ENOMEM; | |
321 | } | |
322 | ||
f63b6a05 TG |
323 | void irq_mark_irq(unsigned int irq) |
324 | { | |
325 | mutex_lock(&sparse_irq_lock); | |
326 | bitmap_set(allocated_irqs, irq, 1); | |
327 | mutex_unlock(&sparse_irq_lock); | |
328 | } | |
329 | ||
c940e01c TG |
330 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
331 | void irq_init_desc(unsigned int irq) | |
332 | { | |
d8179bc0 | 333 | free_desc(irq); |
c940e01c TG |
334 | } |
335 | #endif | |
336 | ||
3795de23 TG |
337 | #endif /* !CONFIG_SPARSE_IRQ */ |
338 | ||
fe12bc2c TG |
339 | /** |
340 | * generic_handle_irq - Invoke the handler for a particular irq | |
341 | * @irq: The irq number to handle | |
342 | * | |
343 | */ | |
344 | int generic_handle_irq(unsigned int irq) | |
345 | { | |
346 | struct irq_desc *desc = irq_to_desc(irq); | |
347 | ||
348 | if (!desc) | |
349 | return -EINVAL; | |
350 | generic_handle_irq_desc(irq, desc); | |
351 | return 0; | |
352 | } | |
edf76f83 | 353 | EXPORT_SYMBOL_GPL(generic_handle_irq); |
fe12bc2c | 354 | |
76ba59f8 MZ |
355 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
356 | /** | |
357 | * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain | |
358 | * @domain: The domain where to perform the lookup | |
359 | * @hwirq: The HW irq number to convert to a logical one | |
360 | * @lookup: Whether to perform the domain lookup or not | |
361 | * @regs: Register file coming from the low-level handling code | |
362 | * | |
363 | * Returns: 0 on success, or -EINVAL if conversion has failed | |
364 | */ | |
365 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, | |
366 | bool lookup, struct pt_regs *regs) | |
367 | { | |
368 | struct pt_regs *old_regs = set_irq_regs(regs); | |
369 | unsigned int irq = hwirq; | |
370 | int ret = 0; | |
371 | ||
372 | irq_enter(); | |
373 | ||
374 | #ifdef CONFIG_IRQ_DOMAIN | |
375 | if (lookup) | |
376 | irq = irq_find_mapping(domain, hwirq); | |
377 | #endif | |
378 | ||
379 | /* | |
380 | * Some hardware gives randomly wrong interrupts. Rather | |
381 | * than crashing, do something sensible. | |
382 | */ | |
383 | if (unlikely(!irq || irq >= nr_irqs)) { | |
384 | ack_bad_irq(irq); | |
385 | ret = -EINVAL; | |
386 | } else { | |
387 | generic_handle_irq(irq); | |
388 | } | |
389 | ||
390 | irq_exit(); | |
391 | set_irq_regs(old_regs); | |
392 | return ret; | |
393 | } | |
394 | #endif | |
395 | ||
1f5a5b87 TG |
396 | /* Dynamic interrupt handling */ |
397 | ||
398 | /** | |
399 | * irq_free_descs - free irq descriptors | |
400 | * @from: Start of descriptor range | |
401 | * @cnt: Number of consecutive irqs to free | |
402 | */ | |
403 | void irq_free_descs(unsigned int from, unsigned int cnt) | |
404 | { | |
1f5a5b87 TG |
405 | int i; |
406 | ||
407 | if (from >= nr_irqs || (from + cnt) > nr_irqs) | |
408 | return; | |
409 | ||
410 | for (i = 0; i < cnt; i++) | |
411 | free_desc(from + i); | |
412 | ||
a05a900a | 413 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 414 | bitmap_clear(allocated_irqs, from, cnt); |
a05a900a | 415 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 | 416 | } |
edf76f83 | 417 | EXPORT_SYMBOL_GPL(irq_free_descs); |
1f5a5b87 TG |
418 | |
419 | /** | |
420 | * irq_alloc_descs - allocate and initialize a range of irq descriptors | |
421 | * @irq: Allocate for specific irq number if irq >= 0 | |
422 | * @from: Start the search from this irq number | |
423 | * @cnt: Number of consecutive irqs to allocate. | |
424 | * @node: Preferred node on which the irq descriptor should be allocated | |
d522a0d1 | 425 | * @owner: Owning module (can be NULL) |
1f5a5b87 TG |
426 | * |
427 | * Returns the first irq number or error code | |
428 | */ | |
429 | int __ref | |
b6873807 SAS |
430 | __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
431 | struct module *owner) | |
1f5a5b87 | 432 | { |
1f5a5b87 TG |
433 | int start, ret; |
434 | ||
435 | if (!cnt) | |
436 | return -EINVAL; | |
437 | ||
c5182b88 MB |
438 | if (irq >= 0) { |
439 | if (from > irq) | |
440 | return -EINVAL; | |
441 | from = irq; | |
62a08ae2 TG |
442 | } else { |
443 | /* | |
444 | * For interrupts which are freely allocated the | |
445 | * architecture can force a lower bound to the @from | |
446 | * argument. x86 uses this to exclude the GSI space. | |
447 | */ | |
448 | from = arch_dynirq_lower_bound(from); | |
c5182b88 MB |
449 | } |
450 | ||
a05a900a | 451 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 452 | |
ed4dea6e YL |
453 | start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, |
454 | from, cnt, 0); | |
1f5a5b87 TG |
455 | ret = -EEXIST; |
456 | if (irq >=0 && start != irq) | |
457 | goto err; | |
458 | ||
ed4dea6e YL |
459 | if (start + cnt > nr_irqs) { |
460 | ret = irq_expand_nr_irqs(start + cnt); | |
e7bcecb7 TG |
461 | if (ret) |
462 | goto err; | |
463 | } | |
1f5a5b87 TG |
464 | |
465 | bitmap_set(allocated_irqs, start, cnt); | |
a05a900a | 466 | mutex_unlock(&sparse_irq_lock); |
b6873807 | 467 | return alloc_descs(start, cnt, node, owner); |
1f5a5b87 TG |
468 | |
469 | err: | |
a05a900a | 470 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
471 | return ret; |
472 | } | |
b6873807 | 473 | EXPORT_SYMBOL_GPL(__irq_alloc_descs); |
1f5a5b87 | 474 | |
7b6ef126 TG |
475 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
476 | /** | |
477 | * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware | |
478 | * @cnt: number of interrupts to allocate | |
479 | * @node: node on which to allocate | |
480 | * | |
481 | * Returns an interrupt number > 0 or 0, if the allocation fails. | |
482 | */ | |
483 | unsigned int irq_alloc_hwirqs(int cnt, int node) | |
484 | { | |
485 | int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL); | |
486 | ||
487 | if (irq < 0) | |
488 | return 0; | |
489 | ||
490 | for (i = irq; cnt > 0; i++, cnt--) { | |
491 | if (arch_setup_hwirq(i, node)) | |
492 | goto err; | |
493 | irq_clear_status_flags(i, _IRQ_NOREQUEST); | |
494 | } | |
495 | return irq; | |
496 | ||
497 | err: | |
498 | for (i--; i >= irq; i--) { | |
499 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); | |
500 | arch_teardown_hwirq(i); | |
501 | } | |
502 | irq_free_descs(irq, cnt); | |
503 | return 0; | |
504 | } | |
505 | EXPORT_SYMBOL_GPL(irq_alloc_hwirqs); | |
506 | ||
507 | /** | |
508 | * irq_free_hwirqs - Free irq descriptor and cleanup the hardware | |
509 | * @from: Free from irq number | |
510 | * @cnt: number of interrupts to free | |
511 | * | |
512 | */ | |
513 | void irq_free_hwirqs(unsigned int from, int cnt) | |
514 | { | |
8844aad8 | 515 | int i, j; |
7b6ef126 | 516 | |
8844aad8 | 517 | for (i = from, j = cnt; j > 0; i++, j--) { |
7b6ef126 TG |
518 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); |
519 | arch_teardown_hwirq(i); | |
520 | } | |
521 | irq_free_descs(from, cnt); | |
522 | } | |
523 | EXPORT_SYMBOL_GPL(irq_free_hwirqs); | |
524 | #endif | |
525 | ||
a98d24b7 TG |
526 | /** |
527 | * irq_get_next_irq - get next allocated irq number | |
528 | * @offset: where to start the search | |
529 | * | |
530 | * Returns next irq number after offset or nr_irqs if none is found. | |
531 | */ | |
532 | unsigned int irq_get_next_irq(unsigned int offset) | |
533 | { | |
534 | return find_next_bit(allocated_irqs, nr_irqs, offset); | |
535 | } | |
536 | ||
d5eb4ad2 | 537 | struct irq_desc * |
31d9d9b6 MZ |
538 | __irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus, |
539 | unsigned int check) | |
d5eb4ad2 TG |
540 | { |
541 | struct irq_desc *desc = irq_to_desc(irq); | |
542 | ||
543 | if (desc) { | |
31d9d9b6 MZ |
544 | if (check & _IRQ_DESC_CHECK) { |
545 | if ((check & _IRQ_DESC_PERCPU) && | |
546 | !irq_settings_is_per_cpu_devid(desc)) | |
547 | return NULL; | |
548 | ||
549 | if (!(check & _IRQ_DESC_PERCPU) && | |
550 | irq_settings_is_per_cpu_devid(desc)) | |
551 | return NULL; | |
552 | } | |
553 | ||
d5eb4ad2 TG |
554 | if (bus) |
555 | chip_bus_lock(desc); | |
556 | raw_spin_lock_irqsave(&desc->lock, *flags); | |
557 | } | |
558 | return desc; | |
559 | } | |
560 | ||
561 | void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus) | |
562 | { | |
563 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
564 | if (bus) | |
565 | chip_bus_sync_unlock(desc); | |
566 | } | |
567 | ||
31d9d9b6 MZ |
568 | int irq_set_percpu_devid(unsigned int irq) |
569 | { | |
570 | struct irq_desc *desc = irq_to_desc(irq); | |
571 | ||
572 | if (!desc) | |
573 | return -EINVAL; | |
574 | ||
575 | if (desc->percpu_enabled) | |
576 | return -EINVAL; | |
577 | ||
578 | desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL); | |
579 | ||
580 | if (!desc->percpu_enabled) | |
581 | return -ENOMEM; | |
582 | ||
583 | irq_set_percpu_devid_flags(irq); | |
584 | return 0; | |
585 | } | |
586 | ||
792d0018 TG |
587 | void kstat_incr_irq_this_cpu(unsigned int irq) |
588 | { | |
b51bf95c | 589 | kstat_incr_irqs_this_cpu(irq_to_desc(irq)); |
792d0018 TG |
590 | } |
591 | ||
c291ee62 TG |
592 | /** |
593 | * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu | |
594 | * @irq: The interrupt number | |
595 | * @cpu: The cpu number | |
596 | * | |
597 | * Returns the sum of interrupt counts on @cpu since boot for | |
598 | * @irq. The caller must ensure that the interrupt is not removed | |
599 | * concurrently. | |
600 | */ | |
3795de23 TG |
601 | unsigned int kstat_irqs_cpu(unsigned int irq, int cpu) |
602 | { | |
603 | struct irq_desc *desc = irq_to_desc(irq); | |
6c9ae009 ED |
604 | |
605 | return desc && desc->kstat_irqs ? | |
606 | *per_cpu_ptr(desc->kstat_irqs, cpu) : 0; | |
3795de23 | 607 | } |
478735e3 | 608 | |
c291ee62 TG |
609 | /** |
610 | * kstat_irqs - Get the statistics for an interrupt | |
611 | * @irq: The interrupt number | |
612 | * | |
613 | * Returns the sum of interrupt counts on all cpus since boot for | |
614 | * @irq. The caller must ensure that the interrupt is not removed | |
615 | * concurrently. | |
616 | */ | |
478735e3 KH |
617 | unsigned int kstat_irqs(unsigned int irq) |
618 | { | |
619 | struct irq_desc *desc = irq_to_desc(irq); | |
620 | int cpu; | |
5e9662fa | 621 | unsigned int sum = 0; |
478735e3 | 622 | |
6c9ae009 | 623 | if (!desc || !desc->kstat_irqs) |
478735e3 KH |
624 | return 0; |
625 | for_each_possible_cpu(cpu) | |
6c9ae009 | 626 | sum += *per_cpu_ptr(desc->kstat_irqs, cpu); |
478735e3 KH |
627 | return sum; |
628 | } | |
c291ee62 TG |
629 | |
630 | /** | |
631 | * kstat_irqs_usr - Get the statistics for an interrupt | |
632 | * @irq: The interrupt number | |
633 | * | |
634 | * Returns the sum of interrupt counts on all cpus since boot for | |
635 | * @irq. Contrary to kstat_irqs() this can be called from any | |
636 | * preemptible context. It's protected against concurrent removal of | |
637 | * an interrupt descriptor when sparse irqs are enabled. | |
638 | */ | |
639 | unsigned int kstat_irqs_usr(unsigned int irq) | |
640 | { | |
7df0b278 | 641 | unsigned int sum; |
c291ee62 TG |
642 | |
643 | irq_lock_sparse(); | |
644 | sum = kstat_irqs(irq); | |
645 | irq_unlock_sparse(); | |
646 | return sum; | |
647 | } |