[deliverable/binutils-gdb.git] / ld / testsuite / ld-spu / icache1.d

#source: icache1.s
#ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
#objdump: -D

.* elf32-spu


Disassembly of section \.text:

00000000 <_start>:
.*	41 00 02 03 	ilhu	\$3,4
.*	60 88 00 03 	iohl	\$3,4096	# 1000
.*	32 00 03 80 	br	24.*
0000000c <__icache_br_handler>:
   c:	00 00 00 00 	stop
00000010 <__icache_call_handler>:
	\.\.\.
  20:	00 04 08 00.*
  24:	31 00 02 4b 	brasl	\$75,10 <__icache_call_handler>
  28:	a0 00 00 08.*
  2c:	00 00 fc 80.*
	\.\.\.

Disassembly of section \.data:

.* <(\.data|_edata-0x10)>:
.*	00 04 08 00 	.*
.*	00 04 0d 04 	.*
.*	00 04 0c 00 	.*
.*	00 08 10 00 	.*

Disassembly of section \.bss:

.* <(__icache_tag_array|__bss_start)>:
	\.\.\.

.* <__icache_rewrite_to>:
	\.\.\.

.* <__icache_rewrite_from>:
	\.\.\.

Disassembly of section \.ovl\.init:

00000400 <__icache_fileoff>:
.*	00 00 00 00.*
.*	00 00 02 00.*
	\.\.\.

Disassembly of section \.ovly1:

00000400 <\.ovly1>:
.*	ai	\$1,\$1,64	# 40
.*	lqd	\$0,16\(\$1\)
.*	bi	\$0
	\.\.\.

Disassembly of section \.ovly2:

00000800 <f1>:
.*	40 20 00 00 	nop	\$0
.*	24 00 40 80 	stqd	\$0,16\(\$1\)
.*	1c f0 00 81 	ai	\$1,\$1,-64
.*	24 00 00 81 	stqd	\$1,0\(\$1\)
.*	33 00 78 80 	brsl	\$0,bd4 .*
.*	33 00 7a 00 	brsl	\$0,be4 .*
	\.\.\.
.*	32 00 17 80 	br	bf4 .*
	\.\.\.
 bd0:	00 04 0d 04.*
 bd4:	31 00 01 cb 	brasl	\$75,c .*
 bd8:	a0 00 08 10.*
 bdc:	00 00 e6 00.*
 be0:	00 04 0c 00.*
 be4:	31 00 01 cb 	brasl	\$75,c .*
 be8:	a0 00 08 14.*
 bec:	00 00 07 80.*
 bf0:	00 04 04 00.*
 bf4:	31 00 01 cb 	brasl	\$75,c .*
 bf8:	20 00 0b 38.*
 bfc:	00 7f 0e 80.*

Disassembly of section \.ovly3:

00000c00 <f3>:
	\.\.\.
.*	35 00 00 00 	bi	\$0

00000d04 <f2>:
.*	1c e0 00 81 	ai	\$1,\$1,-128
.*	24 00 00 81 	stqd	\$1,0\(\$1\)
	\.\.\.
.*	1c 20 00 81 	ai	\$1,\$1,128	# 80
.*	35 00 00 00 	bi	\$0
	\.\.\.

Disassembly of section \.ovly4:

00001000 <f5>:
.*	24 00 40 80 	stqd	\$0,16\(\$1\)
.*	24 f8 00 81 	stqd	\$1,-512\(\$1\)
.*	1c 80 00 81 	ai	\$1,\$1,-512
.*	33 7f fe 80 	brsl	\$0,1000 <f5>	# 1000
	\.\.\.
.*	42 01 00 03 	ila	\$3,200.*
.*	18 00 c0 81 	a	\$1,\$1,\$3
.*	34 00 40 80 	lqd	\$0,16\(\$1\)
.*	35 00 00 00 	bi	\$0
	\.\.\.

Disassembly of section \.ovly5:

00000400 <\.ovly5>:
	\.\.\.
.*	42 01 00 03 	ila	\$3,200 .*
.*	18 00 c0 81 	a	\$1,\$1,\$3
.*	34 00 40 80 	lqd	\$0,16\(\$1\)
.*	30 00 fe 80 	bra	7f4 .*
	\.\.\.
 7f0:	00 04 10 00.*
 7f4:	31 00 01 cb 	brasl	\$75,c .*
 7f8:	a0 00 07 2c.*
 7fc:	00 02 fe 80.*

Disassembly of section \.ovly6:

00000800 <\.ovly6>:
.*	31 01 7a 80 	brasl	\$0,bd4 .*
.*	33 00 7c 00 	brsl	\$0,be4 .*
	\.\.\.
.*	32 00 19 80 	br	bf4 .*
	\.\.\.
 bd0:	00 08 10 00.*
 bd4:	31 00 01 cb 	brasl	\$75,c .*
 bd8:	a0 00 08 00.*
 bdc:	00 03 7a 80.*
 be0:	00 08 10 00.*
 be4:	31 00 01 cb 	brasl	\$75,c .*
 be8:	a0 00 08 04.*
 bec:	00 00 83 80.*
 bf0:	00 08 04 00.*
 bf4:	31 00 01 cb 	brasl	\$75,c .*
 bf8:	20 00 0b 28.*
 bfc:	00 7f 02 80.*

Disassembly of section \.ovly7:

00000c00 <\.ovly7>:
.*	41 7f ff 83 	ilhu	\$3,65535	# ffff
.*	60 f8 30 03 	iohl	\$3,61536	# f060
.*	18 00 c0 84 	a	\$4,\$1,\$3
.*	00 20 00 00 	lnop
.*	04 00 02 01 	ori	\$1,\$4,0
.*	24 00 02 04 	stqd	\$4,0\(\$4\)
.*	33 00 77 80 	brsl	\$0,fd4 .*
.*	33 00 79 00 	brsl	\$0,fe4 .*
.*	34 00 00 81 	lqd	\$1,0\(\$1\)
	\.\.\.
.*	32 00 16 00 	br	ff4 .*
	\.\.\.
     fd0:	00 04 10 00.*
     fd4:	31 00 01 cb 	brasl	\$75,c .*
     fd8:	a0 00 0c 18.*
     fdc:	00 00 0a 80.*
     fe0:	00 08 10 00.*
     fe4:	31 00 01 cb 	brasl	\$75,c .*
     fe8:	a0 00 0c 1c.*
     fec:	00 00 05 80.*
     ff0:	00 08 08 00.*
     ff4:	31 00 01 cb 	brasl	\$75,c .*
     ff8:	20 00 0f 44.*
     ffc:	00 7f 01 80.*

Disassembly of section \.ovly8:

00001000 <f4>:
.*	24 00 40 80 	stqd	\$0,16\(\$1\)
.*	24 f8 00 81 	stqd	\$1,-512\(\$1\)
.*	1c 80 00 81 	ai	\$1,\$1,-512
.*	31 02 7c 80 	brasl	\$0,13e4 .*
	\.\.\.
.*	32 00 18 80 	br	13f4 .*
	\.\.\.
    13e0:	00 04 0d 04.*
    13e4:	31 00 01 cb 	brasl	\$75,c .*
    13e8:	a0 00 10 0c.*
    13ec:	00 03 dc 00.*
    13f0:	00 08 0c 00.*
    13f4:	31 00 01 cb 	brasl	\$75,c .*
    13f8:	20 00 13 30.*
    13fc:	00 7f 02 80.*

#pass
Commit	Line	Data
9da8c90e	1	#source: icache1.s
0c3b6736	2	#ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
9da8c90e AM	3	#objdump: -D
	4
	5	.* elf32-spu
	6
	7
64028ad7 UW	8	Disassembly of section \.text:
	9
	10	00000000 <_start>:
	11	.* 41 00 02 03 ilhu \$3,4
	12	.* 60 88 00 03 iohl \$3,4096 # 1000
	13	.* 32 00 03 80 br 24.*
	14	0000000c <__icache_br_handler>:
	15	c: 00 00 00 00 stop
	16	00000010 <__icache_call_handler>:
	17	\.\.\.
	18	20: 00 04 08 00.*
	19	24: 31 00 02 4b brasl \$75,10 <__icache_call_handler>
	20	28: a0 00 00 08.*
	21	2c: 00 00 fc 80.*
	22	\.\.\.
	23
	24	Disassembly of section \.data:
	25
d2667025	26	.* <(\.data\|_edata-0x10)>:
64028ad7 UW	27	.* 00 04 08 00 .*
	28	.* 00 04 0d 04 .*
	29	.* 00 04 0c 00 .*
	30	.* 00 08 10 00 .*
	31
	32	Disassembly of section \.bss:
	33
d2667025	34	.* <(__icache_tag_array\|__bss_start)>:
64028ad7 UW	35	\.\.\.
	36
	37	.* <__icache_rewrite_to>:
	38	\.\.\.
	39
	40	.* <__icache_rewrite_from>:
	41	\.\.\.
	42
	43	Disassembly of section \.ovl\.init:
	44
	45	00000400 <__icache_fileoff>:
9da8c90e	46	.* 00 00 00 00.*
452de53c	47	.* 00 00 02 00.*
9da8c90e AM	48	\.\.\.
	49
	50	Disassembly of section \.ovly1:
	51
64028ad7	52	00000400 <\.ovly1>:
9da8c90e AM	53	.* ai \$1,\$1,64 # 40
	54	.* lqd \$0,16\(\$1\)
	55	.* bi \$0
	56	\.\.\.
	57
	58	Disassembly of section \.ovly2:
	59
64028ad7	60	00000800 <f1>:
9da8c90e AM	61	.* 40 20 00 00 nop \$0
	62	.* 24 00 40 80 stqd \$0,16\(\$1\)
	63	.* 1c f0 00 81 ai \$1,\$1,-64
	64	.* 24 00 00 81 stqd \$1,0\(\$1\)
64028ad7 UW	65	.* 33 00 78 80 brsl \$0,bd4 .*
	66	.* 33 00 7a 00 brsl \$0,be4 .*
	67	\.\.\.
	68	.* 32 00 17 80 br bf4 .*
	69	\.\.\.
	70	bd0: 00 04 0d 04.*
	71	bd4: 31 00 01 cb brasl \$75,c .*
	72	bd8: a0 00 08 10.*
	73	bdc: 00 00 e6 00.*
	74	be0: 00 04 0c 00.*
	75	be4: 31 00 01 cb brasl \$75,c .*
	76	be8: a0 00 08 14.*
	77	bec: 00 00 07 80.*
	78	bf0: 00 04 04 00.*
	79	bf4: 31 00 01 cb brasl \$75,c .*
	80	bf8: 20 00 0b 38.*
	81	bfc: 00 7f 0e 80.*
9da8c90e AM	82
	83	Disassembly of section \.ovly3:
	84
64028ad7	85	00000c00 <f3>:
9da8c90e AM	86	\.\.\.
	87	.* 35 00 00 00 bi \$0
	88
64028ad7	89	00000d04 <f2>:
9da8c90e AM	90	.* 1c e0 00 81 ai \$1,\$1,-128
	91	.* 24 00 00 81 stqd \$1,0\(\$1\)
	92	\.\.\.
	93	.* 1c 20 00 81 ai \$1,\$1,128 # 80
	94	.* 35 00 00 00 bi \$0
	95	\.\.\.
	96
	97	Disassembly of section \.ovly4:
	98
64028ad7	99	00001000 <f5>:
9da8c90e AM	100	.* 24 00 40 80 stqd \$0,16\(\$1\)
	101	.* 24 f8 00 81 stqd \$1,-512\(\$1\)
	102	.* 1c 80 00 81 ai \$1,\$1,-512
64028ad7	103	.* 33 7f fe 80 brsl \$0,1000 <f5> # 1000
9da8c90e	104	\.\.\.
bbb0fc04	105	.* 42 01 00 03 ila \$3,200.*
9da8c90e AM	106	.* 18 00 c0 81 a \$1,\$1,\$3
	107	.* 34 00 40 80 lqd \$0,16\(\$1\)
	108	.* 35 00 00 00 bi \$0
	109	\.\.\.
	110
	111	Disassembly of section \.ovly5:
	112
64028ad7	113	00000400 <\.ovly5>:
9da8c90e AM	114	\.\.\.
	115	.* 42 01 00 03 ila \$3,200 .*
	116	.* 18 00 c0 81 a \$1,\$1,\$3
	117	.* 34 00 40 80 lqd \$0,16\(\$1\)
64028ad7	118	.* 30 00 fe 80 bra 7f4 .*
9da8c90e	119	\.\.\.
64028ad7 UW	120	7f0: 00 04 10 00.*
	121	7f4: 31 00 01 cb brasl \$75,c .*
	122	7f8: a0 00 07 2c.*
	123	7fc: 00 02 fe 80.*
9da8c90e AM	124
	125	Disassembly of section \.ovly6:
	126
64028ad7 UW	127	00000800 <\.ovly6>:
	128	.* 31 01 7a 80 brasl \$0,bd4 .*
	129	.* 33 00 7c 00 brsl \$0,be4 .*
	130	\.\.\.
	131	.* 32 00 19 80 br bf4 .*
	132	\.\.\.
	133	bd0: 00 08 10 00.*
	134	bd4: 31 00 01 cb brasl \$75,c .*
	135	bd8: a0 00 08 00.*
	136	bdc: 00 03 7a 80.*
	137	be0: 00 08 10 00.*
	138	be4: 31 00 01 cb brasl \$75,c .*
	139	be8: a0 00 08 04.*
	140	bec: 00 00 83 80.*
	141	bf0: 00 08 04 00.*
	142	bf4: 31 00 01 cb brasl \$75,c .*
	143	bf8: 20 00 0b 28.*
	144	bfc: 00 7f 02 80.*
9da8c90e AM	145
	146	Disassembly of section \.ovly7:
	147
64028ad7	148	00000c00 <\.ovly7>:
9da8c90e AM	149	.* 41 7f ff 83 ilhu \$3,65535 # ffff
	150	.* 60 f8 30 03 iohl \$3,61536 # f060
	151	.* 18 00 c0 84 a \$4,\$1,\$3
	152	.* 00 20 00 00 lnop
	153	.* 04 00 02 01 ori \$1,\$4,0
	154	.* 24 00 02 04 stqd \$4,0\(\$4\)
64028ad7 UW	155	.* 33 00 77 80 brsl \$0,fd4 .*
64028ad7 UW	156	.* 33 00 79 00 brsl \$0,fe4 .*
9da8c90e AM	157	.* 34 00 00 81 lqd \$1,0\(\$1\)
9da8c90e AM	158	\.\.\.
64028ad7	159	.* 32 00 16 00 br ff4 .*
9da8c90e	160	\.\.\.
64028ad7 UW	161	fd0: 00 04 10 00.*
	162	fd4: 31 00 01 cb brasl \$75,c .*
	163	fd8: a0 00 0c 18.*
	164	fdc: 00 00 0a 80.*
	165	fe0: 00 08 10 00.*
	166	fe4: 31 00 01 cb brasl \$75,c .*
	167	fe8: a0 00 0c 1c.*
	168	fec: 00 00 05 80.*
	169	ff0: 00 08 08 00.*
	170	ff4: 31 00 01 cb brasl \$75,c .*
	171	ff8: 20 00 0f 44.*
	172	ffc: 00 7f 01 80.*
9da8c90e AM	173
	174	Disassembly of section \.ovly8:
	175
64028ad7	176	00001000 <f4>:
9da8c90e AM	177	.* 24 00 40 80 stqd \$0,16\(\$1\)
	178	.* 24 f8 00 81 stqd \$1,-512\(\$1\)
	179	.* 1c 80 00 81 ai \$1,\$1,-512
64028ad7 UW	180	.* 31 02 7c 80 brasl \$0,13e4 .*
	181	\.\.\.
	182	.* 32 00 18 80 br 13f4 .*
	183	\.\.\.
	184	13e0: 00 04 0d 04.*
	185	13e4: 31 00 01 cb brasl \$75,c .*
	186	13e8: a0 00 10 0c.*
	187	13ec: 00 03 dc 00.*
	188	13f0: 00 08 0c 00.*
	189	13f4: 31 00 01 cb brasl \$75,c .*
	190	13f8: 20 00 13 30.*
	191	13fc: 00 7f 02 80.*
9da8c90e	192
9da8c90e	193	#pass