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Power4 should treat mftb as extended mfspr mnemonic
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
db76a700
AM		 12014-11-30 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
4 power4 and later.
5
d306ce58
SL		 62014-11-28 Sandra Loosemore <sandra@codesourcery.com>
7
8 * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
9 from descriptors.
10
8514e4db
AM		 112014-11-28 Alan Modra <amodra@gmail.com>
12
13 * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
14 (TB): Delete.
15 (insert_tbr, extract_tbr): Validate tbr number.
16
6e733cce
L		 172014-11-24 H.J. Lu <hongjiu.lu@intel.com>
18
19 * configure: Regenerated.
20
14f195c9
IT		 212014-11-17 Ilya Tocar <ilya.tocar@intel.com>
22
23 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
24 vpmultishiftqb.
25 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
26 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
27 (cpu_flags): Add CpuAVX512VBMI.
28 * i386-opc.h (enum): Add CpuAVX512VBMI.
29 (i386_cpu_flags): Add cpuavx512vbmi.
30 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
31 vpermt2b.
32 * i386-init.h: Regenerated.
33 * i386-tbl.h: Likewise.
34
2cc1b5aa
IT		 352014-11-17 Ilya Tocar <ilya.tocar@intel.com>
36
37 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
38 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
39 PREFIX_EVEX_0F38B5.
40 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
41 (cpu_flags): Add CpuAVX512IFMA.
42 * i386-opc.h (enum): Add CpuAVX512IFMA.
43 (i386_cpu_flags): Add cpuavx512ifma.
44 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
45 * i386-init.h: Regenerated.
46 * i386-tbl.h: Likewise.
47
9d8596f0
IT		 482014-11-17 Ilya Tocar <ilya.tocar@intel.com>
49
50 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
51 (prefix_table): Add pcommit.
52 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
53 (cpu_flags): Add CpuPCOMMIT.
54 * i386-opc.h (enum): Add CpuPCOMMIT.
55 (i386_cpu_flags): Add cpupcommit.
56 * i386-opc.tbl: Add pcommit.
57 * i386-init.h: Regenerated.
58 * i386-tbl.h: Likewise.
59
c5e7287a
IT		 602014-11-17 Ilya Tocar <ilya.tocar@intel.com>
61
62 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
63 (prefix_table): Add clwb.
64 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
65 (cpu_flags): Add CpuCLWB.
66 * i386-opc.h (enum): Add CpuCLWB.
67 (i386_cpu_flags): Add cpuclwb.
68 * i386-opc.tbl: Add clwb.
69 * i386-init.h: Regenerated.
70 * i386-tbl.h: Likewise.
71
b4714c7c
SL		 722014-11-06 Sandra Loosemore <sandra@codesourcery.com>
73
74 * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
75 (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
76
ba241f2d
NC		 772014-11-03 Nick Clifton <nickc@redhat.com>
78
79 * po/fi.po: Updated Finnish translation.
80
2c629856
N		 812014-10-31 Andrew Pinski <apinski@cavium.com>
82 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
83
84 * mips-dis.c (mips_arch_choices): Add octeon3.
85 * mips-opc.c (IOCT): Include INSN_OCTEON3.
86 (IOCT2): Likewise.
87 (IOCT3): New define.
88 (IVIRT): New define.
89 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
90 tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
91 IVIRT instructions.
92 Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
93 operand for IOCT3.
94
64b588b5
NC		 952014-10-29 Nick Clifton <nickc@redhat.com>
96
97 * po/de.po: Updated German translation.
98
96ba4233
SL		 992014-10-23 Sandra Loosemore <sandra@codesourcery.com>
100
101 * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
102 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
103 MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
104 size and format initializers. Merge 'b' arguments into 'j'.
105 (NIOS2_NUM_OPCODES): Adjust definition.
106 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
107 (nios2_opcodes): Adjust.
108 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
109 * nios2-dis.c (INSNLEN): Update comment.
110 (nios2_hash_init, nios2_hash): Delete.
111 (OPCODE_HASH_SIZE): New.
112 (nios2_r1_extract_opcode): New.
113 (nios2_disassembler_state): New.
114 (nios2_r1_disassembler_state): New.
115 (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
116 (nios2_find_opcode_hash): Use state object.
117 (bad_opcode): New.
118 (nios2_print_insn_arg): Add op parameter. Use it to access
119 format. Remove 'b' case.
120 (nios2_disassemble): Remove special case for nop. Remove
121 hard-coded instruction size.
122
12e87fac
JB		 1232014-10-21 Jan Beulich <jbeulich@suse.com>
124
125 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
126
d9490cd4
JM		 1272014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
128
129 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
130 entries.
0b6be415 131 Annotate several instructions with the HWCAP2_VIS3B hwcap.
d9490cd4 132
91dc4e0a
TG		 1332014-10-15 Tristan Gingold <gingold@adacore.com>
134
135 * configure: Regenerate.
136
3d68f91c
JM		 1372014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
138
139 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
140 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
141 Annotate table with HWCAP2 bits.
142 Add instructions xmontmul, xmontsqr, xmpmul.
143 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
144 r,i,%mwait' and `rd %mwait,r' instructions.
145 Add rd/wr instructions for accessing the %mcdper ancillary state
146 register.
147 (sparc-opcodes): Add sparc5/vis4.0 instructions:
148 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
149 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
150 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
151 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
152 fpsubus16, and faligndatai.
153 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
154 ancillary state register to the table.
155 (print_insn_sparc): Handle the %mcdper ancillary state register.
156 (print_insn_sparc): Handle new operand type '}'.
157
68f34464
L		 1582014-09-22 H.J. Lu <hongjiu.lu@intel.com>
159
160 * i386-dis.c (MOD_0F20): Removed.
161 (MOD_0F21): Likewise.
162 (MOD_0F22): Likewise.
163 (MOD_0F23): Likewise.
164 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
165 MOD_0F23 with "movZ".
166 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
167 (OP_R): Check mod/rm byte and call OP_E_register.
168
40c7a7cb
KLC		 1692014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
170
171 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
172 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
173 keyword_aridxi): Add audio ISA extension.
174 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
175 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
176 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
177 for nds32-dis.c using.
178 (build_opcode_syntax): Remove dead code.
179 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
180 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
181 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
182 operand parser.
183 * nds32-asm.h: Declare.
184 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
185 decoding by switch.
186
7361da2c
AB		 1872014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
188 Matthew Fortune <matthew.fortune@imgtec.com>
189
190 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
191 mips64r6.
192 (parse_mips_dis_option): Allow MSA and virtualization support for
193 mips64r6.
194 (mips_print_arg_state): Add fields dest_regno and seen_dest.
195 (mips_seen_register): New function.
196 (print_insn_arg): Refactored code to use mips_seen_register
197 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
198 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
199 the register rather than aborting.
200 (print_insn_args): Add length argument. Add code to correctly
201 calculate the instruction address for pc relative instructions.
202 (validate_insn_args): New static function.
203 (print_insn_mips): Prevent jalx disassembling for r6. Use
204 validate_insn_args.
205 (print_insn_micromips): Use validate_insn_args.
206 all the arguments are valid.
207 * mips-formats.h (PREV_CHECK): New define.
208 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
209 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
210 (RD_pc): New define.
211 (FS): New define.
212 (I37): New define.
213 (I69): New define.
214 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
215 MIPS R6 instructions from MIPS R2 instructions.
216
4b4c407a
L		 2172014-09-10 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
220 (putop): Handle "%LP".
221
df7b4545
JW		 2222014-09-03 Jiong Wang <jiong.wang@arm.com>
223
224 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
225 * aarch64-dis-2.c: Update auto-generated file.
226
ee804238
JW		 2272014-09-03 Jiong Wang <jiong.wang@arm.com>
228
229 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
230 (aarch64_feature_lse): New feature added.
231 (LSE): New Added.
232 (aarch64_opcode_table): New LSE instructions added. Improve
233 descriptions for ldarb/ldarh/ldar.
234 (aarch64_opcode_table): Describe PAIRREG.
235 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
236 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
237 (aarch64_print_operand): Recognize PAIRREG.
238 (operand_general_constraint_met_p): Check reg pair constraints for CASP
239 instructions.
240 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
241 (do_special_decoding): Recognize F_LSE_SZ.
242 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
243
5575639b
MR		 2442014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
245
246 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
247 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
248 "sdbbp", "syscall" and "wait".
249
84919466
MR		 2502014-08-21 Nathan Sidwell <nathan@codesourcery.com>
251 Maciej W. Rozycki <macro@codesourcery.com>
252
253 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
254 returned if the U bit is set.
255
a6c70539
MR		 2562014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
257
258 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
259 48-bit "li" encoding.
260
9ace48f3
AA		 2612014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
262
263 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
264 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
265 static functions, code was moved from...
266 (print_insn_s390): ...here.
267 (s390_extract_operand): Adjust comment. Change type of first
268 parameter from 'unsigned char *' to 'const bfd_byte *'.
269 (union operand_value): New.
270 (s390_extract_operand): Change return type to union operand_value.
271 Also avoid integer overflow in sign-extension.
272 (s390_print_insn_with_opcode): Adjust to changed return value from
273 s390_extract_operand(). Change "%i" printf format to "%u" for
274 unsigned values.
275 (init_disasm): Simplify initialization of opc_index[]. This also
276 fixes an access after the last element of s390_opcodes[].
277 (print_insn_s390): Simplify the opcode search loop.
278 Check architecture mask against all searched opcodes, not just the
279 first matching one.
280 (s390_print_insn_with_opcode): Drop function pointer dereferences
281 without effect.
282 (print_insn_s390): Likewise.
283 (s390_insn_length): Simplify formula for return value.
284 (s390_print_insn_with_opcode): Avoid special handling for the
285 separator before the first operand. Use new local variable
286 'flags' in place of 'operand->flags'.
287
60ac5798
MF		 2882014-08-14 Mike Frysinger <vapier@gentoo.org>
289
290 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
291 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
292 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
293 Change assignment of 1 to priv->comment to TRUE.
294 (print_insn_bfin): Change legal to a bfd_boolean. Change
295 assignment of 0/1 with priv comment and parallel and legal
296 to FALSE/TRUE.
297
b3f3b4b0
MF		 2982014-08-14 Mike Frysinger <vapier@gentoo.org>
299
300 * bfin-dis.c (OUT): Define.
301 (decode_CC2stat_0): Declare new op_names array.
302 Replace multiple if statements with a single one.
303
a4e600b2
MF		 3042014-08-14 Mike Frysinger <vapier@gentoo.org>
305
306 * bfin-dis.c (struct private): Add iw0.
307 (_print_insn_bfin): Assign iw0 to priv.iw0.
308 (print_insn_bfin): Drop ifetch and use priv.iw0.
309
703ec4e8
MF		 3102014-08-13 Mike Frysinger <vapier@gentoo.org>
311
312 * bfin-dis.c (comment, parallel): Move from global scope ...
313 (struct private): ... to this new struct.
314 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
315 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
316 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
317 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
318 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
319 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
320 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
321 print_insn_bfin): Declare private struct. Use priv's comment and
322 parallel members.
323
ed2c4879
MF		 3242014-08-13 Mike Frysinger <vapier@gentoo.org>
325
326 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
327 (_print_insn_bfin): Add check for unaligned pc.
328
ba329817
MF		 3292014-08-13 Mike Frysinger <vapier@gentoo.org>
330
331 * bfin-dis.c (ifetch): New function.
332 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
333 -1 when it errors.
334
43885403
MF		 3352014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
336
337 * micromips-opc.c (COD): Rename throughout to...
338 (CM): New define, update to use INSN_COPROC_MOVE.
339 (LCD): Rename throughout to...
340 (LC): New define, update to use INSN_LOAD_COPROC.
341 * mips-opc.c: Likewise.
342
351cdf24
MF		 3432014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
344
345 * micromips-opc.c (COD, LCD) New macros.
346 (cfc1, ctc1): Remove FP_S attribute.
347 (dmfc1, mfc1, mfhc1): Add LCD attribute.
348 (dmtc1, mtc1, mthc1): Add COD attribute.
349 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
350
90a915bf
IT		 3512014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
352 Alexander Ivchenko <alexander.ivchenko@intel.com>
353 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
354 Sergey Lega <sergey.s.lega@intel.com>
355 Anna Tikhonova <anna.tikhonova@intel.com>
356 Ilya Tocar <ilya.tocar@intel.com>
357 Andrey Turetskiy <andrey.turetskiy@intel.com>
358 Ilya Verbin <ilya.verbin@intel.com>
359 Kirill Yukhin <kirill.yukhin@intel.com>
360 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
361
362 * i386-dis-evex.h: Updated.
363 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
364 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
365 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
366 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
367 PREFIX_EVEX_0F3A67.
368 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
369 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
370 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
371 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
372 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
373 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
374 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
375 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
376 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
377 (prefix_table): Add entries for new instructions.
378 (vex_len_table): Ditto.
379 (vex_w_table): Ditto.
380 (OP_E_memory): Update xmmq_mode handling.
381 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
382 (cpu_flags): Add CpuAVX512DQ.
383 * i386-init.h: Regenerared.
384 * i386-opc.h (CpuAVX512DQ): New.
385 (i386_cpu_flags): Add cpuavx512dq.
386 * i386-opc.tbl: Add AVX512DQ instructions.
387 * i386-tbl.h: Regenerate.
388
1ba585e8
IT		 3892014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
390 Alexander Ivchenko <alexander.ivchenko@intel.com>
391 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
392 Sergey Lega <sergey.s.lega@intel.com>
393 Anna Tikhonova <anna.tikhonova@intel.com>
394 Ilya Tocar <ilya.tocar@intel.com>
395 Andrey Turetskiy <andrey.turetskiy@intel.com>
396 Ilya Verbin <ilya.verbin@intel.com>
397 Kirill Yukhin <kirill.yukhin@intel.com>
398 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
399
400 * i386-dis-evex.h: Add new instructions (prefixes bellow).
401 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
402 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
403 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
404 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
405 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
406 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
407 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
408 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
409 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
410 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
411 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
412 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
413 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
414 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
415 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
416 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
417 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
418 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
419 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
420 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
421 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
422 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
423 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
424 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
425 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
426 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
427 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
428 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
429 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
430 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
431 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
432 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
433 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
434 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
435 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
436 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
437 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
438 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
439 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
440 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
441 (prefix_table): Add entries for new instructions.
442 (vex_table) : Ditto.
443 (vex_len_table): Ditto.
444 (vex_w_table): Ditto.
445 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
446 mask_bd_mode handling.
447 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
448 handling.
449 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
450 handling.
451 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
452 (OP_EX): Add dqw_swap_mode handling.
453 (OP_VEX): Add mask_bd_mode handling.
454 (OP_Mask): Add mask_bd_mode handling.
455 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
456 (cpu_flags): Add CpuAVX512BW.
457 * i386-init.h: Regenerated.
458 * i386-opc.h (CpuAVX512BW): New.
459 (i386_cpu_flags): Add cpuavx512bw.
460 * i386-opc.tbl: Add AVX512BW instructions.
461 * i386-tbl.h: Regenerate.
462
99282af6
IT		 4632014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
464 Alexander Ivchenko <alexander.ivchenko@intel.com>
465 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
466 Sergey Lega <sergey.s.lega@intel.com>
467 Anna Tikhonova <anna.tikhonova@intel.com>
468 Ilya Tocar <ilya.tocar@intel.com>
469 Andrey Turetskiy <andrey.turetskiy@intel.com>
470 Ilya Verbin <ilya.verbin@intel.com>
471 Kirill Yukhin <kirill.yukhin@intel.com>
472 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
473
474 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
475 * i386-tbl.h: Regenerate.
476
b28d1bda
IT		 4772014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
478 Alexander Ivchenko <alexander.ivchenko@intel.com>
479 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
480 Sergey Lega <sergey.s.lega@intel.com>
481 Anna Tikhonova <anna.tikhonova@intel.com>
482 Ilya Tocar <ilya.tocar@intel.com>
483 Andrey Turetskiy <andrey.turetskiy@intel.com>
484 Ilya Verbin <ilya.verbin@intel.com>
485 Kirill Yukhin <kirill.yukhin@intel.com>
486 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
487
488 * i386-dis.c (intel_operand_size): Support 128/256 length in
489 vex_vsib_q_w_dq_mode.
490 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
491 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
492 (cpu_flags): Add CpuAVX512VL.
493 * i386-init.h: Regenerated.
494 * i386-opc.h (CpuAVX512VL): New.
495 (i386_cpu_flags): Add cpuavx512vl.
496 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
497 * i386-opc.tbl: Add AVX512VL instructions.
498 * i386-tbl.h: Regenerate.
499
018dc9be
SK		 5002014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
501
502 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
503 * or1k-opinst.c: Regenerate.
504
792f7758
IT		 5052014-07-08 Ilya Tocar <ilya.tocar@intel.com>
506
507 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
508 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
509
35eafcc7
AM		 5102014-07-04 Alan Modra <amodra@gmail.com>
511
512 * configure.ac: Rename from configure.in.
513 * Makefile.in: Regenerate.
514 * config.in: Regenerate.
515
2e98a7bd
AM		 5162014-07-04 Alan Modra <amodra@gmail.com>
517
518 * configure.in: Include bfd/version.m4.
519 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
520 (BFD_VERSION): Delete.
521 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
522 * configure: Regenerate.
523 * Makefile.in: Regenerate.
524
f36e8886
BS		 5252014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
526 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
527 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
528 Soundararajan <Sounderarajan.D@atmel.com>
529
530 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
2e98a7bd
AM		 531 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
532 machine is not avrtiny.
f36e8886 533
6ddf779d
PDM		 5342014-06-26 Philippe De Muyter <phdm@macqel.be>
535
536 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
537 constants.
538
c151b1c6
AM		 5392014-06-12 Alan Modra <amodra@gmail.com>
540
541 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
542 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
543
d9949a36
L		 5442014-06-10 H.J. Lu <hongjiu.lu@intel.com>
545
546 * i386-dis.c (fwait_prefix): New.
547 (ckprefix): Set fwait_prefix.
548 (print_insn): Properly print prefixes before fwait.
549
a47622ac
AM		 5502014-06-07 Alan Modra <amodra@gmail.com>
551
552 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
553
270c9937
JB		 5542014-06-05 Joel Brobecker <brobecker@adacore.com>
555
556 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
557 bfd's development.sh.
558 * Makefile.in, configure: Regenerate.
559
9f445129
NC		 5602014-06-03 Nick Clifton <nickc@redhat.com>
561
562 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
563 decide when extended addressing is being used.
564
ec9a8169
EB		 5652014-06-02 Eric Botcazou <ebotcazou@adacore.com>
566
567 * sparc-opc.c (cas): Disable for LEON.
568 (casl): Likewise.
569
cdf2a8b7
AM		 5702014-05-20 Alan Modra <amodra@gmail.com>
571
572 * m68k-dis.c: Don't include setjmp.h.
573
df18fdba
L		 5742014-05-09 H.J. Lu <hongjiu.lu@intel.com>
575
576 * i386-dis.c (ADDR16_PREFIX): Removed.
577 (ADDR32_PREFIX): Likewise.
578 (DATA16_PREFIX): Likewise.
579 (DATA32_PREFIX): Likewise.
580 (prefix_name): Updated.
581 (print_insn): Simplify data and address size prefixes processing.
582
999b995d
SK		 5832014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
584
585 * or1k-desc.c: Regenerated.
586 * or1k-desc.h: Likewise.
587 * or1k-opc.c: Likewise.
588 * or1k-opc.h: Likewise.
589 * or1k-opinst.c: Likewise.
590
ae52f483
AB		 5912014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
592
593 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
594 (I34): New define.
595 (I36): New define.
596 (I66): New define.
597 (I68): New define.
598 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
599 mips64r5.
600 (parse_mips_dis_option): Update MSA and virtualization support to
9f445129 601 allow mips64r3 and mips64r5.
ae52f483 602
f7730599
AB		 6032014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
604
605 * mips-opc.c (G3): Remove I4.
606
285ca992
L		 6072014-05-05 H.J. Lu <hongjiu.lu@intel.com>
608
609 PR binutils/16893
610 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
611 (end_codep): Likewise.
612 (mandatory_prefix): Likewise.
613 (active_seg_prefix): Likewise.
614 (ckprefix): Set active_seg_prefix to the active segment register
615 prefix.
616 (seg_prefix): Removed.
617 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
618 for prefix index. Ignore the index if it is invalid and the
619 mandatory prefix isn't required.
620 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
621 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
622 in used_prefixes here. Don't print unused prefixes. Check
623 active_seg_prefix for the active segment register prefix.
624 Restore the DFLAG bit in sizeflag if the data size prefix is
625 unused. Check the unused mandatory PREFIX_XXX prefixes
626 (append_seg): Only print the segment register which gets used.
627 (OP_E_memory): Check active_seg_prefix for the segment register
628 prefix.
629 (OP_OFF): Likewise.
630 (OP_OFF64): Likewise.
631 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
632
8df14d78
L		 6332014-05-02 H.J. Lu <hongjiu.lu@intel.com>
634
635 PR binutils/16886
636 * config.in: Regenerated.
637 * configure: Likewise.
638 * configure.in: Check if sigsetjmp is available.
639 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
640 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
641 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
642 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
643 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
644 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
645 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
646 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
647 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
648 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
649 (OPCODES_SIGSETJMP): Likewise.
650 (OPCODES_SIGLONGJMP): Likewise.
651 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
652 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
653 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
654 * xtensa-dis.c (dis_private): Replace jmp_buf with
655 OPCODES_SIGJMP_BUF.
656 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
657 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
658 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
659 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
660 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
661
86a80a50
L		 6622014-05-01 H.J. Lu <hongjiu.lu@intel.com>
663
664 PR binutils/16891
665 * i386-dis.c (print_insn): Handle prefixes before fwait.
666
a9e18c6a
AM		 6672014-04-26 Alan Modra <amodra@gmail.com>
668
669 * po/POTFILES.in: Regenerate.
670
7d64c587
AB		 6712014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
672
673 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
674 to allow the MIPS XPA ASE.
675 (parse_mips_dis_option): Process the -Mxpa option.
676 * mips-opc.c (XPA): New define.
677 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
678 locations of the ctc0 and cfc0 instructions.
679
73589c9d
CS		 6802014-04-22 Christian Svensson <blue@cmd.nu>
681
682 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
683 * configure.in: Likewise.
684 * disassemble.c: Likewise.
685 * or1k-asm.c: New file.
686 * or1k-desc.c: New file.
687 * or1k-desc.h: New file.
688 * or1k-dis.c: New file.
689 * or1k-ibld.c: New file.
690 * or1k-opc.c: New file.
691 * or1k-opc.h: New file.
692 * or1k-opinst.c: New file.
693 * Makefile.in: Regenerate.
694 * configure: Regenerate.
695 * openrisc-asm.c: Delete.
696 * openrisc-desc.c: Delete.
697 * openrisc-desc.h: Delete.
698 * openrisc-dis.c: Delete.
699 * openrisc-ibld.c: Delete.
700 * openrisc-opc.c: Delete.
701 * openrisc-opc.h: Delete.
702 * or32-dis.c: Delete.
703 * or32-opc.c: Delete.
704
2cf200a4
IT		 7052014-04-04 Ilya Tocar <ilya.tocar@intel.com>
706
707 * i386-dis.c (rm_table): Add encls, enclu.
708 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
709 (cpu_flags): Add CpuSE1.
710 * i386-opc.h (enum): Add CpuSE1.
711 (i386_cpu_flags): Add cpuse1.
712 * i386-opc.tbl: Add encls, enclu.
713 * i386-init.h: Regenerated.
714 * i386-tbl.h: Likewise.
715
31c981bc
AG		 7162014-04-02 Anthony Green <green@moxielogic.com>
717
718 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
719 instructions, sex.b and sex.s.
720
76dfed02
YZ		 7212014-03-26 Jiong Wang <jiong.wang@arm.com>
722
723 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
724 instructions.
725
5fc35d96
IT		 7262014-03-20 Ilya Tocar <ilya.tocar@intel.com>
727
728 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
729 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
730 vscatterqps.
731 * i386-tbl.h: Regenerate.
732
ec92c392
JM		 7332014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
734
735 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
736 %hstick_enable added.
737
b8985e5c
NC		 7382014-03-19 Nick Clifton <nickc@redhat.com>
739
740 * rx-decode.opc (bwl): Allow for bogus instructions with a size
741 field of 3.
b41c812c 742 (sbwl, ubwl, SCALE): Likewise.
b8985e5c
NC		 743 * rx-decode.c: Regenerate.
744
fa47fa92
AM		 7452014-03-12 Alan Modra <amodra@gmail.com>
746
747 * Makefile.in: Regenerate.
748
4b95cf5c
AM		 7492014-03-05 Alan Modra <amodra@gmail.com>
750
751 Update copyright years.
752
cd0c81e9 7532014-03-04 Heiher <r@hev.cc>
4ba154f5
RS		 754
755 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
756
079b5aec
RS		 7572014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
758
759 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
760 so that they come after the Loongson extensions.
761
2c80b753
AM		 7622014-03-03 Alan Modra <amodra@gmail.com>
763
764 * i386-gen.c (process_copyright): Emit copyright notice on one line.
765
b721f1fa
AM		 7662014-02-28 Alan Modra <amodra@gmail.com>
767
768 * msp430-decode.c: Regenerate.
769
f17c8bfc
YZ		 7702014-02-27 Jiong Wang <jiong.wang@arm.com>
771
772 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
773 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
774
a58549dd
YZ		 7752014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
776
777 * aarch64-opc.c (print_register_offset_address): Call
778 get_int_reg_name to prepare the register name.
779
d6e9dd78
IT		 7802014-02-25 Ilya Tocar <ilya.tocar@intel.com>
781
782 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
783 * i386-tbl.h: Regenerate.
784
7852014-02-20 Ilya Tocar <ilya.tocar@intel.com>
dcf893b5
IT		 786
787 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
788 (cpu_flags): Add CpuPREFETCHWT1.
789 * i386-init.h: Regenerate.
790 * i386-opc.h (CpuPREFETCHWT1): New.
791 (i386_cpu_flags): Add cpuprefetchwt1.
792 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
793 * i386-tbl.h: Regenerate.
794
957d0955
IT		 7952014-02-20 Ilya Tocar <ilya.tocar@intel.com>
796
797 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
798 to CpuAVX512F.
799 * i386-tbl.h: Regenerate.
800
10632b79
L		 8012014-02-19 H.J. Lu <hongjiu.lu@intel.com>
802
803 * i386-gen.c (output_cpu_flags): Don't output trailing space.
804 (output_opcode_modifier): Likewise.
805 (output_operand_type): Likewise.
806 * i386-init.h: Regenerated.
807 * i386-tbl.h: Likewise.
808
963f3586
IT		 8092014-02-12 Ilya Tocar <ilya.tocar@intel.com>
810
811 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
812 MOD_0FC7_REG_5.
813 (PREFIX enum): Add PREFIX_0FAE_REG_7.
814 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
815 (prefix_table): Add clflusopt.
816 (mod_table): Add xrstors, xsavec, xsaves.
817 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
818 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
819 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
820 * i386-init.h: Regenerate.
821 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
822 xsaves64, xsavec, xsavec64.
823 * i386-tbl.h: Regenerate.
824
c1c69e83
AM		 8252014-02-10 Alan Modra <amodra@gmail.com>
826
827 * po/POTFILES.in: Regenerate.
828 * po/opcodes.pot: Regenerate.
829
eaa9d1ad
MZ		 8302014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
831 Jan Beulich <jbeulich@suse.com>
832
833 PR binutils/16490
834 * i386-dis.c (OP_E_memory): Fix shift computation for
835 vex_vsib_q_w_dq_mode.
836
e2e6193d
RM		 8372014-01-09 Bradley Nelson <bradnelson@google.com>
838 Roland McGrath <mcgrathr@google.com>
839
840 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
841 last_rex_prefix is -1.
842
221fd5d5
L		 8432014-01-08 H.J. Lu <hongjiu.lu@intel.com>
844
845 * i386-gen.c (process_copyright): Update copyright year to 2014.
846
b0b0c9fc
MR		 8472014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
848
849 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
850
5fb776a6 851For older changes see ChangeLog-2013
252b5132 852\f
5fb776a6 853Copyright (C) 2014 Free Software Foundation, Inc.
752937aa
NC		 854
855Copying and distribution of this file, with or without modification,
856are permitted in any medium without royalty provided the copyright
857notice and this notice are preserved.
858
252b5132 859Local Variables:
2f6d2f85
NC		 860mode: change-log
861left-margin: 8
862fill-column: 74
252b5132
RH		 863version-control: never
864End:
GDB Binutils - Deliverables
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