sim: bfin: fix UART LSR read-only bit saturation
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12011-04-27 Nick Clifton <nickc@redhat.com>
2
3 * po/da.po: Updated Danish translation.
4
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52011-04-26 Anton Blanchard <anton@samba.org>
6
7 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
8
9887672f
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92011-04-21 DJ Delorie <dj@redhat.com>
10
11 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
12 * rx-decode.c: Regenerate.
13
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142011-04-20 H.J. Lu <hongjiu.lu@intel.com>
15
16 * i386-init.h: Regenerated.
17
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182011-04-19 Quentin Neill <quentin.neill@amd.com>
19
20 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
21 from bdver1 flags.
22
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232011-04-13 Nick Clifton <nickc@redhat.com>
24
25 * v850-dis.c (disassemble): Always print a closing square brace if
26 an opening square brace was printed.
27
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282011-04-12 Nick Clifton <nickc@redhat.com>
29
30 PR binutils/12534
31 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
32 patterns.
33 (print_insn_thumb32): Handle %L.
34
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352011-04-11 Julian Brown <julian@codesourcery.com>
36
37 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
38 (print_insn_thumb32): Add APSR bitmask support.
39
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402011-04-07 Paul Carroll<pcarroll@codesourcery.com>
41
42 * arm-dis.c (print_insn): init vars moved into private_data structure.
43
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442011-03-24 Mike Frysinger <vapier@gentoo.org>
45
46 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
47
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482011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
49
50 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
51 post-increment to support LPM Z+ instruction. Add support for 'E'
52 constraint for DES instruction.
53 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
54
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552011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
56
57 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
58
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592011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
60
61 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
62 Use branch types instead.
63 (print_insn): Likewise.
64
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652011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
66
67 * mips-opc.c (mips_builtin_opcodes): Correct register use
68 annotation of "alnv.ps".
69
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702011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
71
72 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
73
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742011-02-22 Mike Frysinger <vapier@gentoo.org>
75
76 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
77
f5caf9f4
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782011-02-22 Mike Frysinger <vapier@gentoo.org>
79
80 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
81
e5bc4265
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822011-02-19 Mike Frysinger <vapier@gentoo.org>
83
84 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
85 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
86 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
87 exception, end_of_registers, msize, memory, bfd_mach.
88 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
89 LB0REG, LC1REG, LT1REG, LB1REG): Delete
90 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
91 (get_allreg): Change to new defines. Fallback to abort().
92
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932011-02-14 Mike Frysinger <vapier@gentoo.org>
94
95 * bfin-dis.c: Add whitespace/parenthesis where needed.
96
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972011-02-14 Mike Frysinger <vapier@gentoo.org>
98
99 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
100 than 7.
101
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1022011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
103
104 * configure: Regenerate.
105
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1062011-02-13 Mike Frysinger <vapier@gentoo.org>
107
108 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
109
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1102011-02-13 Mike Frysinger <vapier@gentoo.org>
111
112 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
113 dregs only when P is set, and dregs_lo otherwise.
114
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1152011-02-13 Mike Frysinger <vapier@gentoo.org>
116
117 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
118
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1192011-02-12 Mike Frysinger <vapier@gentoo.org>
120
121 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
122
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1232011-02-12 Mike Frysinger <vapier@gentoo.org>
124
125 * bfin-dis.c (machine_registers): Delete REG_GP.
126 (reg_names): Delete "GP".
127 (decode_allregs): Change REG_GP to REG_LASTREG.
128
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1292011-02-12 Mike Frysinger <vapier@gentoo.org>
130
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131 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
132 M_IH, M_IU): Delete.
26bb3ddd 133
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1342011-02-11 Mike Frysinger <vapier@gentoo.org>
135
136 * bfin-dis.c (reg_names): Add const.
137 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
138 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
139 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
140 decode_counters, decode_allregs): Likewise.
141
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1422011-02-09 Michael Snyder <msnyder@vmware.com>
143
144 * i386-dis.c (OP_J): Parenthesize expression to prevent
145 truncated addresses.
146 (print_insn): Fix indentation off-by-one.
147
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1482011-02-01 Nick Clifton <nickc@redhat.com>
149
150 * po/da.po: Updated Danish translation.
151
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1522011-01-21 Dave Murphy <davem@devkitpro.org>
153
154 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
155
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1562011-01-18 H.J. Lu <hongjiu.lu@intel.com>
157
158 * i386-dis.c (sIbT): New.
159 (b_T_mode): Likewise.
160 (dis386): Replace sIb with sIbT on "pushT".
161 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
162 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
163
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1642011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
165
166 * i386-init.h: Regenerated.
167 * i386-tbl.h: Regenerated
168
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1692011-01-17 Quentin Neill <quentin.neill@amd.com>
170
171 * i386-dis.c (REG_XOP_TBM_01): New.
172 (REG_XOP_TBM_02): New.
173 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
174 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
175 entries, and add bextr instruction.
176
177 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
178 (cpu_flags): Add CpuTBM.
179
180 * i386-opc.h (CpuTBM) New.
181 (i386_cpu_flags): Add bit cputbm.
182
183 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
184 blcs, blsfill, blsic, t1mskc, and tzmsk.
185
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1862011-01-12 DJ Delorie <dj@redhat.com>
187
188 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
189
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1902011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
191
192 * mips-dis.c (print_insn_args): Adjust the value to print the real
193 offset for "+c" argument.
194
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1952011-01-10 Nick Clifton <nickc@redhat.com>
196
197 * po/da.po: Updated Danish translation.
198
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1992011-01-05 Nathan Sidwell <nathan@codesourcery.com>
200
201 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
202
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2032011-01-04 H.J. Lu <hongjiu.lu@intel.com>
204
205 * i386-dis.c (REG_VEX_38F3): New.
206 (PREFIX_0FBC): Likewise.
207 (PREFIX_VEX_38F2): Likewise.
208 (PREFIX_VEX_38F3_REG_1): Likewise.
209 (PREFIX_VEX_38F3_REG_2): Likewise.
210 (PREFIX_VEX_38F3_REG_3): Likewise.
211 (PREFIX_VEX_38F7): Likewise.
212 (VEX_LEN_38F2_P_0): Likewise.
213 (VEX_LEN_38F3_R_1_P_0): Likewise.
214 (VEX_LEN_38F3_R_2_P_0): Likewise.
215 (VEX_LEN_38F3_R_3_P_0): Likewise.
216 (VEX_LEN_38F7_P_0): Likewise.
217 (dis386_twobyte): Use PREFIX_0FBC.
218 (reg_table): Add REG_VEX_38F3.
219 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
220 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
221 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
222 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
223 PREFIX_VEX_38F7.
224 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
225 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
226 VEX_LEN_38F7_P_0.
227
228 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
229 (cpu_flags): Add CpuBMI.
230
231 * i386-opc.h (CpuBMI): New.
232 (i386_cpu_flags): Add cpubmi.
233
234 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
235 * i386-init.h: Regenerated.
236 * i386-tbl.h: Likewise.
237
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2382011-01-04 H.J. Lu <hongjiu.lu@intel.com>
239
240 * i386-dis.c (VexGdq): New.
241 (OP_VEX): Handle dq_mode.
242
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2432011-01-01 H.J. Lu <hongjiu.lu@intel.com>
244
245 * i386-gen.c (process_copyright): Update copyright to 2011.
246
9e9e0820 247For older changes see ChangeLog-2010
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