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x86: eliminate ImmExt abuse
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
474da251
JB		 12019-11-12 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (operand_instances): Add RegB entry.
4 * i386-opc.h (enum operand_instance): Add RegB.
5 * i386-opc.tbl (RegC, RegD, RegB): Define.
6 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
7 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
8 monitorx, mwaitx): Drop ImmExt and convert encodings
9 accordingly.
10 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
11 (edx, rdx): Add Instance=RegD.
12 (ebx, rbx): Add Instance=RegB.
13 * i386-tbl.h: Re-generate.
14
75e5731b
JB		 152019-11-12 Jan Beulich <jbeulich@suse.com>
16
17 * i386-gen.c (operand_type_init): Adjust
18 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
19 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
20 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
21 (operand_instances): New.
22 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
23 (output_operand_type): New parameter "instance". Process it.
24 (process_i386_operand_type): New local variable "instance".
25 (main): Adjust static assertions.
26 * i386-opc.h (INSTANCE_WIDTH): Define.
27 (enum operand_instance): New.
28 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
29 (union i386_operand_type): Replace acc, inoutportreg, and
30 shiftcount by instance.
31 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
32 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
33 Add Instance=.
34 * i386-init.h, i386-tbl.h: Re-generate.
35
91802f3c
JB		 362019-11-11 Jan Beulich <jbeulich@suse.com>
37
38 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
39 smaxp/sminp entries' "tied_operand" field to 2.
40
4f5fc85d
JB		 412019-11-11 Jan Beulich <jbeulich@suse.com>
42
43 * aarch64-opc.c (operand_general_constraint_met_p): Replace
44 "index" local variable by that of the already existing "num".
45
dc2be329
L		 462019-11-08 H.J. Lu <hongjiu.lu@intel.com>
47
48 PR gas/25167
49 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
50 * i386-tbl.h: Regenerated.
51
f74a6307
JB		 522019-11-08 Jan Beulich <jbeulich@suse.com>
53
54 * i386-gen.c (operand_type_init): Add Class= to
55 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
56 OPERAND_TYPE_REGBND entry.
57 (operand_classes): Add RegMask and RegBND entries.
58 (operand_types): Drop RegMask and RegBND entry.
59 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
60 (RegMask, RegBND): Delete.
61 (union i386_operand_type): Remove regmask and regbnd fields.
62 * i386-opc.tbl (RegMask, RegBND): Define.
63 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
64 Class=RegBND.
65 * i386-init.h, i386-tbl.h: Re-generate.
66
3528c362
JB		 672019-11-08 Jan Beulich <jbeulich@suse.com>
68
69 * i386-gen.c (operand_type_init): Add Class= to
70 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
71 OPERAND_TYPE_REGZMM entries.
72 (operand_classes): Add RegMMX and RegSIMD entries.
73 (operand_types): Drop RegMMX and RegSIMD entries.
74 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
75 (RegMMX, RegSIMD): Delete.
76 (union i386_operand_type): Remove regmmx and regsimd fields.
77 * i386-opc.tbl (RegMMX): Define.
78 (RegXMM, RegYMM, RegZMM): Add Class=.
79 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
80 Class=RegSIMD.
81 * i386-init.h, i386-tbl.h: Re-generate.
82
4a5c67ed
JB		 832019-11-08 Jan Beulich <jbeulich@suse.com>
84
85 * i386-gen.c (operand_type_init): Add Class= to
86 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
87 entries.
88 (operand_classes): Add RegCR, RegDR, and RegTR entries.
89 (operand_types): Drop Control, Debug, and Test entries.
90 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
91 (Control, Debug, Test): Delete.
92 (union i386_operand_type): Remove control, debug, and test
93 fields.
94 * i386-opc.tbl (Control, Debug, Test): Define.
95 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
96 Class=RegDR, and Test by Class=RegTR.
97 * i386-init.h, i386-tbl.h: Re-generate.
98
00cee14f
JB		 992019-11-08 Jan Beulich <jbeulich@suse.com>
100
101 * i386-gen.c (operand_type_init): Add Class= to
102 OPERAND_TYPE_SREG entry.
103 (operand_classes): Add SReg entry.
104 (operand_types): Drop SReg entry.
105 * i386-opc.h (enum operand_class): Add SReg.
106 (SReg): Delete.
107 (union i386_operand_type): Remove sreg field.
108 * i386-opc.tbl (SReg): Define.
109 * i386-reg.tbl: Replace SReg by Class=SReg.
110 * i386-init.h, i386-tbl.h: Re-generate.
111
bab6aec1
JB		 1122019-11-08 Jan Beulich <jbeulich@suse.com>
113
114 * i386-gen.c (operand_type_init): Add Class=. New
115 OPERAND_TYPE_ANYIMM entry.
116 (operand_classes): New.
117 (operand_types): Drop Reg entry.
118 (output_operand_type): New parameter "class". Process it.
119 (process_i386_operand_type): New local variable "class".
120 (main): Adjust static assertions.
121 * i386-opc.h (CLASS_WIDTH): Define.
122 (enum operand_class): New.
123 (Reg): Replace by Class. Adjust comment.
124 (union i386_operand_type): Replace reg by class.
125 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
126 Class=.
127 * i386-reg.tbl: Replace Reg by Class=Reg.
128 * i386-init.h: Re-generate.
129
1f4cd317
MM		 1302019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
131
132 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
133 (aarch64_opcode_table): Add data gathering hint mnemonic.
134 * opcodes/aarch64-dis-2.c: Account for new instruction.
135
616ce08e
MM		 1362019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
137
138 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
139
140
8382113f
MM		 1412019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
142
143 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
144 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
145 aarch64_feature_f64mm): New feature sets.
146 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
147 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
148 instructions.
149 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
150 macros.
151 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
152 (OP_SVE_QQQ): New qualifier.
153 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
154 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
155 the movprfx constraint.
156 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
157 (aarch64_opcode_table): Define new instructions smmla,
158 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
159 uzip{1/2}, trn{1/2}.
160 * aarch64-opc.c (operand_general_constraint_met_p): Handle
161 AARCH64_OPND_SVE_ADDR_RI_S4x32.
162 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
163 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
164 Account for new instructions.
165 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
166 S4x32 operand.
167 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
168
aab2c27d
MM		 1692019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1702019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
171
172 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
173 Armv8.6-A.
174 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
175 (neon_opcodes): Add bfloat SIMD instructions.
176 (print_insn_coprocessor): Add new control character %b to print
177 condition code without checking cp_num.
178 (print_insn_neon): Account for BFloat16 instructions that have no
179 special top-byte handling.
180
33593eaf
MM		 1812019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1822019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
183
184 * arm-dis.c (print_insn_coprocessor,
185 print_insn_generic_coprocessor): Create wrapper functions around
186 the implementation of the print_insn_coprocessor control codes.
187 (print_insn_coprocessor_1): Original print_insn_coprocessor
188 function that now takes which array to look at as an argument.
189 (print_insn_arm): Use both print_insn_coprocessor and
190 print_insn_generic_coprocessor.
191 (print_insn_thumb32): As above.
192
df678013
MM		 1932019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1942019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
195
196 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
197 in reglane special case.
198 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
199 aarch64_find_next_opcode): Account for new instructions.
200 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
201 in reglane special case.
202 * aarch64-opc.c (struct operand_qualifier_data): Add data for
203 new AARCH64_OPND_QLF_S_2H qualifier.
204 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
205 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
206 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
207 sets.
208 (BFLOAT_SVE, BFLOAT): New feature set macros.
209 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
210 instructions.
211 (aarch64_opcode_table): Define new instructions bfdot,
212 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
213 bfcvtn2, bfcvt.
214
8ae2d3d9
MM		 2152019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2162019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
217
218 * aarch64-tbl.h (ARMV8_6): New macro.
219
142861df
JB		 2202019-11-07 Jan Beulich <jbeulich@suse.com>
221
222 * i386-dis.c (prefix_table): Add mcommit.
223 (rm_table): Add rdpru.
224 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
225 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
226 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
227 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
228 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
229 * i386-opc.tbl (mcommit, rdpru): New.
230 * i386-init.h, i386-tbl.h: Re-generate.
231
081e283f
JB		 2322019-11-07 Jan Beulich <jbeulich@suse.com>
233
234 * i386-dis.c (OP_Mwait): Drop local variable "names", use
235 "names32" instead.
236 (OP_Monitor): Drop local variable "op1_names", re-purpose
237 "names" for it instead, and replace former "names" uses by
238 "names32" ones.
239
c050c89a
JB		 2402019-11-07 Jan Beulich <jbeulich@suse.com>
241
242 PR/gas 25167
243 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
244 operand-less forms.
245 * opcodes/i386-tbl.h: Re-generate.
246
7abb8d81
JB		 2472019-11-05 Jan Beulich <jbeulich@suse.com>
248
249 * i386-dis.c (OP_Mwaitx): Delete.
250 (prefix_table): Use OP_Mwait for mwaitx entry.
251 (OP_Mwait): Also handle mwaitx.
252
267b8516
JB		 2532019-11-05 Jan Beulich <jbeulich@suse.com>
254
255 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
256 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
257 (prefix_table): Add respective entries.
258 (rm_table): Link to those entries.
259
f8687e93
JB		 2602019-11-05 Jan Beulich <jbeulich@suse.com>
261
262 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
263 (REG_0F1C_P_0_MOD_0): ... this.
264 (REG_0F1E_MOD_3): Rename to ...
265 (REG_0F1E_P_1_MOD_3): ... this.
266 (RM_0F01_REG_5): Rename to ...
267 (RM_0F01_REG_5_MOD_3): ... this.
268 (RM_0F01_REG_7): Rename to ...
269 (RM_0F01_REG_7_MOD_3): ... this.
270 (RM_0F1E_MOD_3_REG_7): Rename to ...
271 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
272 (RM_0FAE_REG_6): Rename to ...
273 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
274 (RM_0FAE_REG_7): Rename to ...
275 (RM_0FAE_REG_7_MOD_3): ... this.
276 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
277 (PREFIX_0F01_REG_5_MOD_0): ... this.
278 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
279 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
280 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
281 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
282 (PREFIX_0FAE_REG_0): Rename to ...
283 (PREFIX_0FAE_REG_0_MOD_3): ... this.
284 (PREFIX_0FAE_REG_1): Rename to ...
285 (PREFIX_0FAE_REG_1_MOD_3): ... this.
286 (PREFIX_0FAE_REG_2): Rename to ...
287 (PREFIX_0FAE_REG_2_MOD_3): ... this.
288 (PREFIX_0FAE_REG_3): Rename to ...
289 (PREFIX_0FAE_REG_3_MOD_3): ... this.
290 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
291 (PREFIX_0FAE_REG_4_MOD_0): ... this.
292 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
293 (PREFIX_0FAE_REG_4_MOD_3): ... this.
294 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
295 (PREFIX_0FAE_REG_5_MOD_0): ... this.
296 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
297 (PREFIX_0FAE_REG_5_MOD_3): ... this.
298 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
299 (PREFIX_0FAE_REG_6_MOD_0): ... this.
300 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
301 (PREFIX_0FAE_REG_6_MOD_3): ... this.
302 (PREFIX_0FAE_REG_7): Rename to ...
303 (PREFIX_0FAE_REG_7_MOD_0): ... this.
304 (PREFIX_MOD_0_0FC3): Rename to ...
305 (PREFIX_0FC3_MOD_0): ... this.
306 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
307 (PREFIX_0FC7_REG_6_MOD_0): ... this.
308 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
309 (PREFIX_0FC7_REG_6_MOD_3): ... this.
310 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
311 (PREFIX_0FC7_REG_7_MOD_3): ... this.
312 (reg_table, prefix_table, mod_table, rm_table): Adjust
313 accordingly.
314
5103274f
NC		 3152019-11-04 Nick Clifton <nickc@redhat.com>
316
317 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
318 of a v850 system register. Move the v850_sreg_names array into
319 this function.
320 (get_v850_reg_name): Likewise for ordinary register names.
321 (get_v850_vreg_name): Likewise for vector register names.
322 (get_v850_cc_name): Likewise for condition codes.
323 * get_v850_float_cc_name): Likewise for floating point condition
324 codes.
325 (get_v850_cacheop_name): Likewise for cache-ops.
326 (get_v850_prefop_name): Likewise for pref-ops.
327 (disassemble): Use the new accessor functions.
328
1820262b
DB		 3292019-10-30 Delia Burduv <delia.burduv@arm.com>
330
331 * aarch64-opc.c (print_immediate_offset_address): Don't print the
332 immediate for the writeback form of ldraa/ldrab if it is 0.
333 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
334 * aarch64-opc-2.c: Regenerated.
335
3cc17af5
JB		 3362019-10-30 Jan Beulich <jbeulich@suse.com>
337
338 * i386-gen.c (operand_type_shorthands): Delete.
339 (operand_type_init): Expand previous shorthands.
340 (set_bitfield_from_shorthand): Rename back to ...
341 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
342 of operand_type_init[].
343 (set_bitfield): Adjust call to the above function.
344 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
345 RegXMM, RegYMM, RegZMM): Define.
346 * i386-reg.tbl: Expand prior shorthands.
347
a2cebd03
JB		 3482019-10-30 Jan Beulich <jbeulich@suse.com>
349
350 * i386-gen.c (output_i386_opcode): Change order of fields
351 emitted to output.
352 * i386-opc.h (struct insn_template): Move operands field.
353 Convert extension_opcode field to unsigned short.
354 * i386-tbl.h: Re-generate.
355
507916b8
JB		 3562019-10-30 Jan Beulich <jbeulich@suse.com>
357
358 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
359 of W.
360 * i386-opc.h (W): Extend comment.
361 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
362 general purpose variants not allowing for byte operands.
363 * i386-tbl.h: Re-generate.
364
efea62b4
NC		 3652019-10-29 Nick Clifton <nickc@redhat.com>
366
367 * tic30-dis.c (print_branch): Correct size of operand array.
368
9adb2591
NC		 3692019-10-29 Nick Clifton <nickc@redhat.com>
370
371 * d30v-dis.c (print_insn): Check that operand index is valid
372 before attempting to access the operands array.
373
993a00a9
NC		 3742019-10-29 Nick Clifton <nickc@redhat.com>
375
376 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
377 locating the bit to be tested.
378
66a66a17
NC		 3792019-10-29 Nick Clifton <nickc@redhat.com>
380
381 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
382 values.
383 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
384 (print_insn_s12z): Check for illegal size values.
385
1ee3542c
NC		 3862019-10-28 Nick Clifton <nickc@redhat.com>
387
388 * csky-dis.c (csky_chars_to_number): Check for a negative
389 count. Use an unsigned integer to construct the return value.
390
bbf9a0b5
NC		 3912019-10-28 Nick Clifton <nickc@redhat.com>
392
393 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
394 operand buffer. Set value to 15 not 13.
395 (get_register_operand): Use OPERAND_BUFFER_LEN.
396 (get_indirect_operand): Likewise.
397 (print_two_operand): Likewise.
398 (print_three_operand): Likewise.
399 (print_oar_insn): Likewise.
400
d1e304bc
NC		 4012019-10-28 Nick Clifton <nickc@redhat.com>
402
403 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
404 (bit_extract_simple): Likewise.
405 (bit_copy): Likewise.
406 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
407 index_offset array are not accessed.
408
dee33451
NC		 4092019-10-28 Nick Clifton <nickc@redhat.com>
410
411 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
412 operand.
413
27cee81d
NC		 4142019-10-25 Nick Clifton <nickc@redhat.com>
415
416 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
417 access to opcodes.op array element.
418
de6d8dc2
NC		 4192019-10-23 Nick Clifton <nickc@redhat.com>
420
421 * rx-dis.c (get_register_name): Fix spelling typo in error
422 message.
423 (get_condition_name, get_flag_name, get_double_register_name)
424 (get_double_register_high_name, get_double_register_low_name)
425 (get_double_control_register_name, get_double_condition_name)
426 (get_opsize_name, get_size_name): Likewise.
427
6207ed28
NC		 4282019-10-22 Nick Clifton <nickc@redhat.com>
429
430 * rx-dis.c (get_size_name): New function. Provides safe
431 access to name array.
432 (get_opsize_name): Likewise.
433 (print_insn_rx): Use the accessor functions.
434
12234dfd
NC		 4352019-10-16 Nick Clifton <nickc@redhat.com>
436
437 * rx-dis.c (get_register_name): New function. Provides safe
438 access to name array.
439 (get_condition_name, get_flag_name, get_double_register_name)
440 (get_double_register_high_name, get_double_register_low_name)
441 (get_double_control_register_name, get_double_condition_name):
442 Likewise.
443 (print_insn_rx): Use the accessor functions.
444
1d378749
NC		 4452019-10-09 Nick Clifton <nickc@redhat.com>
446
447 PR 25041
448 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
449 instructions.
450
d241b910
JB		 4512019-10-07 Jan Beulich <jbeulich@suse.com>
452
453 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
454 (cmpsd): Likewise. Move EsSeg to other operand.
455 * opcodes/i386-tbl.h: Re-generate.
456
f5c5b7c1
AM		 4572019-09-23 Alan Modra <amodra@gmail.com>
458
459 * m68k-dis.c: Include cpu-m68k.h
460
7beeaeb8
AM		 4612019-09-23 Alan Modra <amodra@gmail.com>
462
463 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
464 "elf/mips.h" earlier.
465
3f9aad11
JB		 4662018-09-20 Jan Beulich <jbeulich@suse.com>
467
468 PR gas/25012
469 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
470 with SReg operand.
471 * i386-tbl.h: Re-generate.
472
fd361982
AM		 4732019-09-18 Alan Modra <amodra@gmail.com>
474
475 * arc-ext.c: Update throughout for bfd section macro changes.
476
e0b2a78c
SM		 4772019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
478
479 * Makefile.in: Re-generate.
480 * configure: Re-generate.
481
7e9ad3a3
JW		 4822019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
483
484 * riscv-opc.c (riscv_opcodes): Change subset field
485 to insn_class field for all instructions.
486 (riscv_insn_types): Likewise.
487
bb695960
PB		 4882019-09-16 Phil Blundell <pb@pbcl.net>
489
490 * configure: Regenerated.
491
8063ab7e
MV		 4922019-09-10 Miod Vallat <miod@online.fr>
493
494 PR 24982
495 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
496
60391a25
PB		 4972019-09-09 Phil Blundell <pb@pbcl.net>
498
499 binutils 2.33 branch created.
500
f44b758d
NC		 5012019-09-03 Nick Clifton <nickc@redhat.com>
502
503 PR 24961
504 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
505 greater than zero before indexing via (bufcnt -1).
506
1e4b5e7d
NC		 5072019-09-03 Nick Clifton <nickc@redhat.com>
508
509 PR 24958
510 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
511 (MAX_SPEC_REG_NAME_LEN): Define.
512 (struct mmix_dis_info): Use defined constants for array lengths.
513 (get_reg_name): New function.
514 (get_sprec_reg_name): New function.
515 (print_insn_mmix): Use new functions.
516
c4a23bf8
SP		 5172019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
518
519 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
520 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
521 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
522
a051e2f3
KT		 5232019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
524
525 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
526 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
527 (aarch64_sys_reg_supported_p): Update checks for the above.
528
08132bdd
SP		 5292019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
530
531 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
532 cases MVE_SQRSHRL and MVE_UQRSHLL.
533 (print_insn_mve): Add case for specifier 'k' to check
534 specific bit of the instruction.
535
d88bdcb4
PA		 5362019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
537
538 PR 24854
539 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
540 encountering an unknown machine type.
541 (print_insn_arc): Handle arc_insn_length returning 0. In error
542 cases return -1 rather than calling abort.
543
bc750500
JB		 5442019-08-07 Jan Beulich <jbeulich@suse.com>
545
546 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
547 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
548 IgnoreSize.
549 * i386-tbl.h: Re-generate.
550
23d188c7
BW		 5512019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
552
553 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
554 instructions.
555
c0d6f62f
JW		 5562019-07-30 Mel Chen <mel.chen@sifive.com>
557
558 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
559 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
560
561 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
562 fscsr.
563
0f3f7167
CZ		 5642019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
565
566 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
567 and MPY class instructions.
568 (parse_option): Add nps400 option.
569 (print_arc_disassembler_options): Add nps400 info.
570
7e126ba3
CZ		 5712019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
572
573 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
574 (bspop): Likewise.
575 (modapp): Likewise.
576 * arc-opc.c (RAD_CHK): Add.
577 * arc-tbl.h: Regenerate.
578
a028026d
KT		 5792019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
580
581 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
582 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
583
ac79ff9e
NC		 5842019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
585
586 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
587 instructions as UNPREDICTABLE.
588
231097b0
JM		 5892019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
590
591 * bpf-desc.c: Regenerated.
592
1d942ae9
JB		 5932019-07-17 Jan Beulich <jbeulich@suse.com>
594
595 * i386-gen.c (static_assert): Define.
596 (main): Use it.
597 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
598 (Opcode_Modifier_Num): ... this.
599 (Mem): Delete.
600
dfd69174
JB		 6012019-07-16 Jan Beulich <jbeulich@suse.com>
602
603 * i386-gen.c (operand_types): Move RegMem ...
604 (opcode_modifiers): ... here.
605 * i386-opc.h (RegMem): Move to opcode modifer enum.
606 (union i386_operand_type): Move regmem field ...
607 (struct i386_opcode_modifier): ... here.
608 * i386-opc.tbl (RegMem): Define.
609 (mov, movq): Move RegMem on segment, control, debug, and test
610 register flavors.
611 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
612 to non-SSE2AVX flavor.
613 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
614 Move RegMem on register only flavors. Drop IgnoreSize from
615 legacy encoding flavors.
616 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
617 flavors.
618 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
619 register only flavors.
620 (vmovd): Move RegMem and drop IgnoreSize on register only
621 flavor. Change opcode and operand order to store form.
622 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
623
21df382b
JB		 6242019-07-16 Jan Beulich <jbeulich@suse.com>
625
626 * i386-gen.c (operand_type_init, operand_types): Replace SReg
627 entries.
628 * i386-opc.h (SReg2, SReg3): Replace by ...
629 (SReg): ... this.
630 (union i386_operand_type): Replace sreg fields.
631 * i386-opc.tbl (mov, ): Use SReg.
632 (push, pop): Likewies. Drop i386 and x86-64 specific segment
633 register flavors.
634 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
635 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
636
3719fd55
JM		 6372019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
638
639 * bpf-desc.c: Regenerate.
640 * bpf-opc.c: Likewise.
641 * bpf-opc.h: Likewise.
642
92434a14
JM		 6432019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
644
645 * bpf-desc.c: Regenerate.
646 * bpf-opc.c: Likewise.
647
43dd7626
HPN		 6482019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
649
650 * arm-dis.c (print_insn_coprocessor): Rename index to
651 index_operand.
652
98602811
JW		 6532019-07-05 Kito Cheng <kito.cheng@sifive.com>
654
655 * riscv-opc.c (riscv_insn_types): Add r4 type.
656
657 * riscv-opc.c (riscv_insn_types): Add b and j type.
658
659 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
660 format for sb type and correct s type.
661
01c1ee4a
RS		 6622019-07-02 Richard Sandiford <richard.sandiford@arm.com>
663
664 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
665 SVE FMOV alias of FCPY.
666
83adff69
RS		 6672019-07-02 Richard Sandiford <richard.sandiford@arm.com>
668
669 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
670 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
671
89418844
RS		 6722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
673
674 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
675 registers in an instruction prefixed by MOVPRFX.
676
41be57ca
MM		 6772019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
678
679 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
680 sve_size_13 icode to account for variant behaviour of
681 pmull{t,b}.
682 * aarch64-dis-2.c: Regenerate.
683 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
684 sve_size_13 icode to account for variant behaviour of
685 pmull{t,b}.
686 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
687 (OP_SVE_VVV_Q_D): Add new qualifier.
688 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
689 (struct aarch64_opcode): Split pmull{t,b} into those requiring
690 AES and those not.
691
9d3bf266
JB		 6922019-07-01 Jan Beulich <jbeulich@suse.com>
693
694 * opcodes/i386-gen.c (operand_type_init): Remove
695 OPERAND_TYPE_VEC_IMM4 entry.
696 (operand_types): Remove Vec_Imm4.
697 * opcodes/i386-opc.h (Vec_Imm4): Delete.
698 (union i386_operand_type): Remove vec_imm4.
699 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
700 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
701
c3949f43
JB		 7022019-07-01 Jan Beulich <jbeulich@suse.com>
703
704 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
705 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
706 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
707 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
708 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
709 monitorx, mwaitx): Drop ImmExt from operand-less forms.
710 * i386-tbl.h: Re-generate.
711
5641ec01
JB		 7122019-07-01 Jan Beulich <jbeulich@suse.com>
713
714 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
715 register operands.
716 * i386-tbl.h: Re-generate.
717
79dec6b7
JB		 7182019-07-01 Jan Beulich <jbeulich@suse.com>
719
720 * i386-opc.tbl (C): New.
721 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
722 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
723 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
724 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
725 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
726 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
727 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
728 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
729 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
730 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
731 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
732 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
733 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
734 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
735 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
736 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
737 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
738 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
739 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
740 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
741 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
742 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
743 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
744 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
745 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
746 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
747 flavors.
748 * i386-tbl.h: Re-generate.
749
a0a1771e
JB		 7502019-07-01 Jan Beulich <jbeulich@suse.com>
751
752 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
753 register operands.
754 * i386-tbl.h: Re-generate.
755
cd546e7b
JB		 7562019-07-01 Jan Beulich <jbeulich@suse.com>
757
758 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
759 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
760 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
761 * i386-tbl.h: Re-generate.
762
e3bba3fc
JB		 7632019-07-01 Jan Beulich <jbeulich@suse.com>
764
765 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
766 Disp8MemShift from register only templates.
767 * i386-tbl.h: Re-generate.
768
36cc073e
JB		 7692019-07-01 Jan Beulich <jbeulich@suse.com>
770
771 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
772 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
773 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
774 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
775 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
776 EVEX_W_0F11_P_3_M_1): Delete.
777 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
778 EVEX_W_0F11_P_3): New.
779 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
780 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
781 MOD_EVEX_0F11_PREFIX_3 table entries.
782 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
783 PREFIX_EVEX_0F11 table entries.
784 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
785 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
786 EVEX_W_0F11_P_3_M_{0,1} table entries.
787
219920a7
JB		 7882019-07-01 Jan Beulich <jbeulich@suse.com>
789
790 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
791 Delete.
792
e395f487
L		 7932019-06-27 H.J. Lu <hongjiu.lu@intel.com>
794
795 PR binutils/24719
796 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
797 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
798 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
799 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
800 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
801 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
802 EVEX_LEN_0F38C7_R_6_P_2_W_1.
803 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
804 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
805 PREFIX_EVEX_0F38C6_REG_6 entries.
806 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
807 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
808 EVEX_W_0F38C7_R_6_P_2 entries.
809 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
810 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
811 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
812 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
813 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
814 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
815 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
816
2b7bcc87
JB		 8172019-06-27 Jan Beulich <jbeulich@suse.com>
818
819 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
820 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
821 VEX_LEN_0F2D_P_3): Delete.
822 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
823 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
824 (prefix_table): ... here.
825
c1dc7af5
JB		 8262019-06-27 Jan Beulich <jbeulich@suse.com>
827
828 * i386-dis.c (Iq): Delete.
829 (Id): New.
830 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
831 TBM insns.
832 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
833 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
834 (OP_E_memory): Also honor needindex when deciding whether an
835 address size prefix needs printing.
836 (OP_I): Remove handling of q_mode. Add handling of d_mode.
837
d7560e2d
JW		 8382019-06-26 Jim Wilson <jimw@sifive.com>
839
840 PR binutils/24739
841 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
842 Set info->display_endian to info->endian_code.
843
2c703856
JB		 8442019-06-25 Jan Beulich <jbeulich@suse.com>
845
846 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
847 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
848 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
849 OPERAND_TYPE_ACC64 entries.
850 * i386-init.h: Re-generate.
851
54fbadc0
JB		 8522019-06-25 Jan Beulich <jbeulich@suse.com>
853
854 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
855 Delete.
856 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
857 of dqa_mode.
858 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
859 entries here.
860 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
861 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
862
a280ab8e
JB		 8632019-06-25 Jan Beulich <jbeulich@suse.com>
864
865 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
866 variables.
867
e1a1babd
JB		 8682019-06-25 Jan Beulich <jbeulich@suse.com>
869
870 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
871 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
872 movnti.
d7560e2d 873 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 874 * i386-tbl.h: Re-generate.
875
b8364fa7
JB		 8762019-06-25 Jan Beulich <jbeulich@suse.com>
877
878 * i386-opc.tbl (and): Mark Imm8S form for optimization.
879 * i386-tbl.h: Re-generate.
880
ad692897
L		 8812019-06-21 H.J. Lu <hongjiu.lu@intel.com>
882
883 * i386-dis-evex.h: Break into ...
884 * i386-dis-evex-len.h: New file.
885 * i386-dis-evex-mod.h: Likewise.
886 * i386-dis-evex-prefix.h: Likewise.
887 * i386-dis-evex-reg.h: Likewise.
888 * i386-dis-evex-w.h: Likewise.
889 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
890 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
891 i386-dis-evex-mod.h.
892
f0a6222e
L		 8932019-06-19 H.J. Lu <hongjiu.lu@intel.com>
894
895 PR binutils/24700
896 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
897 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
898 EVEX_W_0F385B_P_2.
899 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
900 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
901 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
902 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
903 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
904 EVEX_LEN_0F385B_P_2_W_1.
905 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
906 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
907 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
908 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
909 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
910 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
911 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
912 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
913 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
914 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
915
6e1c90b7
L		 9162019-06-17 H.J. Lu <hongjiu.lu@intel.com>
917
918 PR binutils/24691
919 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
920 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
921 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
922 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
923 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
924 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
925 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
926 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
927 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
928 EVEX_LEN_0F3A43_P_2_W_1.
929 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
930 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
931 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
932 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
933 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
934 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
935 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
936 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
937 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
938 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
939 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
940 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
941
bcc5a6eb
NC		 9422019-06-14 Nick Clifton <nickc@redhat.com>
943
944 * po/fr.po; Updated French translation.
945
e4c4ac46
SH		 9462019-06-13 Stafford Horne <shorne@gmail.com>
947
948 * or1k-asm.c: Regenerated.
949 * or1k-desc.c: Regenerated.
950 * or1k-desc.h: Regenerated.
951 * or1k-dis.c: Regenerated.
952 * or1k-ibld.c: Regenerated.
953 * or1k-opc.c: Regenerated.
954 * or1k-opc.h: Regenerated.
955 * or1k-opinst.c: Regenerated.
956
a0e44ef5
PB		 9572019-06-12 Peter Bergner <bergner@linux.ibm.com>
958
959 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
960
12efd68d
L		 9612019-06-05 H.J. Lu <hongjiu.lu@intel.com>
962
963 PR binutils/24633
964 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
965 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
966 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
967 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
968 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
969 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
970 EVEX_LEN_0F3A1B_P_2_W_1.
971 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
972 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
973 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
974 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
975 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
976 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
977 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
978 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
979
63c6fc6c
L		 9802019-06-04 H.J. Lu <hongjiu.lu@intel.com>
981
982 PR binutils/24626
983 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
984 EVEX.vvvv when disassembling VEX and EVEX instructions.
985 (OP_VEX): Set vex.register_specifier to 0 after readding
986 vex.register_specifier.
987 (OP_Vex_2src_1): Likewise.
988 (OP_Vex_2src_2): Likewise.
989 (OP_LWP_E): Likewise.
990 (OP_EX_Vex): Don't check vex.register_specifier.
991 (OP_XMM_Vex): Likewise.
992
9186c494
L		 9932019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
994 Lili Cui <lili.cui@intel.com>
995
996 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
997 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
998 instructions.
999 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1000 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1001 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1002 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1003 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1004 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1005 * i386-init.h: Regenerated.
1006 * i386-tbl.h: Likewise.
1007
5d79adc4
L		 10082019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1009 Lili Cui <lili.cui@intel.com>
1010
1011 * doc/c-i386.texi: Document enqcmd.
1012 * testsuite/gas/i386/enqcmd-intel.d: New file.
1013 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1014 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1015 * testsuite/gas/i386/enqcmd.d: Likewise.
1016 * testsuite/gas/i386/enqcmd.s: Likewise.
1017 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1018 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1019 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1020 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1021 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1022 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1023 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1024 and x86-64-enqcmd.
1025
a9d96ab9
AH		 10262019-06-04 Alan Hayward <alan.hayward@arm.com>
1027
1028 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1029
4f6d070a
AM		 10302019-06-03 Alan Modra <amodra@gmail.com>
1031
1032 * ppc-dis.c (prefix_opcd_indices): Correct size.
1033
a2f4b66c
L		 10342019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1035
1036 PR gas/24625
1037 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1038 Disp8ShiftVL.
1039 * i386-tbl.h: Regenerated.
1040
405b5bd8
AM		 10412019-05-24 Alan Modra <amodra@gmail.com>
1042
1043 * po/POTFILES.in: Regenerate.
1044
8acf1435
PB		 10452019-05-24 Peter Bergner <bergner@linux.ibm.com>
1046 Alan Modra <amodra@gmail.com>
1047
1048 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1049 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1050 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1051 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1052 XTOP>): Define and add entries.
1053 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1054 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1055 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1056 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1057
dd7efa79
PB		 10582019-05-24 Peter Bergner <bergner@linux.ibm.com>
1059 Alan Modra <amodra@gmail.com>
1060
1061 * ppc-dis.c (ppc_opts): Add "future" entry.
1062 (PREFIX_OPCD_SEGS): Define.
1063 (prefix_opcd_indices): New array.
1064 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1065 (lookup_prefix): New function.
1066 (print_insn_powerpc): Handle 64-bit prefix instructions.
1067 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1068 (PMRR, POWERXX): Define.
1069 (prefix_opcodes): New instruction table.
1070 (prefix_num_opcodes): New constant.
1071
79472b45
JM		 10722019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1073
1074 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1075 * configure: Regenerated.
1076 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1077 and cpu/bpf.opc.
1078 (HFILES): Add bpf-desc.h and bpf-opc.h.
1079 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1080 bpf-ibld.c and bpf-opc.c.
1081 (BPF_DEPS): Define.
1082 * Makefile.in: Regenerated.
1083 * disassemble.c (ARCH_bpf): Define.
1084 (disassembler): Add case for bfd_arch_bpf.
1085 (disassemble_init_for_target): Likewise.
1086 (enum epbf_isa_attr): Define.
1087 * disassemble.h: extern print_insn_bpf.
1088 * bpf-asm.c: Generated.
1089 * bpf-opc.h: Likewise.
1090 * bpf-opc.c: Likewise.
1091 * bpf-ibld.c: Likewise.
1092 * bpf-dis.c: Likewise.
1093 * bpf-desc.h: Likewise.
1094 * bpf-desc.c: Likewise.
1095
ba6cd17f
SD		 10962019-05-21 Sudakshina Das <sudi.das@arm.com>
1097
1098 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1099 and VMSR with the new operands.
1100
e39c1607
SD		 11012019-05-21 Sudakshina Das <sudi.das@arm.com>
1102
1103 * arm-dis.c (enum mve_instructions): New enum
1104 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1105 and cneg.
1106 (mve_opcodes): New instructions as above.
1107 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1108 csneg and csel.
1109 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1110
23d00a41
SD		 11112019-05-21 Sudakshina Das <sudi.das@arm.com>
1112
1113 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1114 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1115 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1116 uqshl, urshrl and urshr.
1117 (is_mve_okay_in_it): Add new instructions to TRUE list.
1118 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1119 (print_insn_mve): Updated to accept new %j,
1120 %<bitfield>m and %<bitfield>n patterns.
1121
cd4797ee
FS		 11222019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1123
1124 * mips-opc.c (mips_builtin_opcodes): Change source register
1125 constraint for DAUI.
1126
999b073b
NC		 11272019-05-20 Nick Clifton <nickc@redhat.com>
1128
1129 * po/fr.po: Updated French translation.
1130
14b456f2
AV		 11312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1132 Michael Collison <michael.collison@arm.com>
1133
1134 * arm-dis.c (thumb32_opcodes): Add new instructions.
1135 (enum mve_instructions): Likewise.
1136 (enum mve_undefined): Add new reasons.
1137 (is_mve_encoding_conflict): Handle new instructions.
1138 (is_mve_undefined): Likewise.
1139 (is_mve_unpredictable): Likewise.
1140 (print_mve_undefined): Likewise.
1141 (print_mve_size): Likewise.
1142
f49bb598
AV		 11432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1144 Michael Collison <michael.collison@arm.com>
1145
1146 * arm-dis.c (thumb32_opcodes): Add new instructions.
1147 (enum mve_instructions): Likewise.
1148 (is_mve_encoding_conflict): Handle new instructions.
1149 (is_mve_undefined): Likewise.
1150 (is_mve_unpredictable): Likewise.
1151 (print_mve_size): Likewise.
1152
56858bea
AV		 11532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1154 Michael Collison <michael.collison@arm.com>
1155
1156 * arm-dis.c (thumb32_opcodes): Add new instructions.
1157 (enum mve_instructions): Likewise.
1158 (is_mve_encoding_conflict): Likewise.
1159 (is_mve_unpredictable): Likewise.
1160 (print_mve_size): Likewise.
1161
e523f101
AV		 11622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1163 Michael Collison <michael.collison@arm.com>
1164
1165 * arm-dis.c (thumb32_opcodes): Add new instructions.
1166 (enum mve_instructions): Likewise.
1167 (is_mve_encoding_conflict): Handle new instructions.
1168 (is_mve_undefined): Likewise.
1169 (is_mve_unpredictable): Likewise.
1170 (print_mve_size): Likewise.
1171
66dcaa5d
AV		 11722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1173 Michael Collison <michael.collison@arm.com>
1174
1175 * arm-dis.c (thumb32_opcodes): Add new instructions.
1176 (enum mve_instructions): Likewise.
1177 (is_mve_encoding_conflict): Handle new instructions.
1178 (is_mve_undefined): Likewise.
1179 (is_mve_unpredictable): Likewise.
1180 (print_mve_size): Likewise.
1181 (print_insn_mve): Likewise.
1182
d052b9b7
AV		 11832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1184 Michael Collison <michael.collison@arm.com>
1185
1186 * arm-dis.c (thumb32_opcodes): Add new instructions.
1187 (print_insn_thumb32): Handle new instructions.
1188
ed63aa17
AV		 11892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1190 Michael Collison <michael.collison@arm.com>
1191
1192 * arm-dis.c (enum mve_instructions): Add new instructions.
1193 (enum mve_undefined): Add new reasons.
1194 (is_mve_encoding_conflict): Handle new instructions.
1195 (is_mve_undefined): Likewise.
1196 (is_mve_unpredictable): Likewise.
1197 (print_mve_undefined): Likewise.
1198 (print_mve_size): Likewise.
1199 (print_mve_shift_n): Likewise.
1200 (print_insn_mve): Likewise.
1201
897b9bbc
AV		 12022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1203 Michael Collison <michael.collison@arm.com>
1204
1205 * arm-dis.c (enum mve_instructions): Add new instructions.
1206 (is_mve_encoding_conflict): Handle new instructions.
1207 (is_mve_unpredictable): Likewise.
1208 (print_mve_rotate): Likewise.
1209 (print_mve_size): Likewise.
1210 (print_insn_mve): Likewise.
1211
1c8f2df8
AV		 12122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1213 Michael Collison <michael.collison@arm.com>
1214
1215 * arm-dis.c (enum mve_instructions): Add new instructions.
1216 (is_mve_encoding_conflict): Handle new instructions.
1217 (is_mve_unpredictable): Likewise.
1218 (print_mve_size): Likewise.
1219 (print_insn_mve): Likewise.
1220
d3b63143
AV		 12212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1222 Michael Collison <michael.collison@arm.com>
1223
1224 * arm-dis.c (enum mve_instructions): Add new instructions.
1225 (enum mve_undefined): Add new reasons.
1226 (is_mve_encoding_conflict): Handle new instructions.
1227 (is_mve_undefined): Likewise.
1228 (is_mve_unpredictable): Likewise.
1229 (print_mve_undefined): Likewise.
1230 (print_mve_size): Likewise.
1231 (print_insn_mve): Likewise.
1232
14925797
AV		 12332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1234 Michael Collison <michael.collison@arm.com>
1235
1236 * arm-dis.c (enum mve_instructions): Add new instructions.
1237 (is_mve_encoding_conflict): Handle new instructions.
1238 (is_mve_undefined): Likewise.
1239 (is_mve_unpredictable): Likewise.
1240 (print_mve_size): Likewise.
1241 (print_insn_mve): Likewise.
1242
c507f10b
AV		 12432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1244 Michael Collison <michael.collison@arm.com>
1245
1246 * arm-dis.c (enum mve_instructions): Add new instructions.
1247 (enum mve_unpredictable): Add new reasons.
1248 (enum mve_undefined): Likewise.
1249 (is_mve_okay_in_it): Handle new isntructions.
1250 (is_mve_encoding_conflict): Likewise.
1251 (is_mve_undefined): Likewise.
1252 (is_mve_unpredictable): Likewise.
1253 (print_mve_vmov_index): Likewise.
1254 (print_simd_imm8): Likewise.
1255 (print_mve_undefined): Likewise.
1256 (print_mve_unpredictable): Likewise.
1257 (print_mve_size): Likewise.
1258 (print_insn_mve): Likewise.
1259
bf0b396d
AV		 12602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1261 Michael Collison <michael.collison@arm.com>
1262
1263 * arm-dis.c (enum mve_instructions): Add new instructions.
1264 (enum mve_unpredictable): Add new reasons.
1265 (enum mve_undefined): Likewise.
1266 (is_mve_encoding_conflict): Handle new instructions.
1267 (is_mve_undefined): Likewise.
1268 (is_mve_unpredictable): Likewise.
1269 (print_mve_undefined): Likewise.
1270 (print_mve_unpredictable): Likewise.
1271 (print_mve_rounding_mode): Likewise.
1272 (print_mve_vcvt_size): Likewise.
1273 (print_mve_size): Likewise.
1274 (print_insn_mve): Likewise.
1275
ef1576a1
AV		 12762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1277 Michael Collison <michael.collison@arm.com>
1278
1279 * arm-dis.c (enum mve_instructions): Add new instructions.
1280 (enum mve_unpredictable): Add new reasons.
1281 (enum mve_undefined): Likewise.
1282 (is_mve_undefined): Handle new instructions.
1283 (is_mve_unpredictable): Likewise.
1284 (print_mve_undefined): Likewise.
1285 (print_mve_unpredictable): Likewise.
1286 (print_mve_size): Likewise.
1287 (print_insn_mve): Likewise.
1288
aef6d006
AV		 12892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1290 Michael Collison <michael.collison@arm.com>
1291
1292 * arm-dis.c (enum mve_instructions): Add new instructions.
1293 (enum mve_undefined): Add new reasons.
1294 (insns): Add new instructions.
1295 (is_mve_encoding_conflict):
1296 (print_mve_vld_str_addr): New print function.
1297 (is_mve_undefined): Handle new instructions.
1298 (is_mve_unpredictable): Likewise.
1299 (print_mve_undefined): Likewise.
1300 (print_mve_size): Likewise.
1301 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1302 (print_insn_mve): Handle new operands.
1303
04d54ace
AV		 13042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1305 Michael Collison <michael.collison@arm.com>
1306
1307 * arm-dis.c (enum mve_instructions): Add new instructions.
1308 (enum mve_unpredictable): Add new reasons.
1309 (is_mve_encoding_conflict): Handle new instructions.
1310 (is_mve_unpredictable): Likewise.
1311 (mve_opcodes): Add new instructions.
1312 (print_mve_unpredictable): Handle new reasons.
1313 (print_mve_register_blocks): New print function.
1314 (print_mve_size): Handle new instructions.
1315 (print_insn_mve): Likewise.
1316
9743db03
AV		 13172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1318 Michael Collison <michael.collison@arm.com>
1319
1320 * arm-dis.c (enum mve_instructions): Add new instructions.
1321 (enum mve_unpredictable): Add new reasons.
1322 (enum mve_undefined): Likewise.
1323 (is_mve_encoding_conflict): Handle new instructions.
1324 (is_mve_undefined): Likewise.
1325 (is_mve_unpredictable): Likewise.
1326 (coprocessor_opcodes): Move NEON VDUP from here...
1327 (neon_opcodes): ... to here.
1328 (mve_opcodes): Add new instructions.
1329 (print_mve_undefined): Handle new reasons.
1330 (print_mve_unpredictable): Likewise.
1331 (print_mve_size): Handle new instructions.
1332 (print_insn_neon): Handle vdup.
1333 (print_insn_mve): Handle new operands.
1334
143275ea
AV		 13352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1336 Michael Collison <michael.collison@arm.com>
1337
1338 * arm-dis.c (enum mve_instructions): Add new instructions.
1339 (enum mve_unpredictable): Add new values.
1340 (mve_opcodes): Add new instructions.
1341 (vec_condnames): New array with vector conditions.
1342 (mve_predicatenames): New array with predicate suffixes.
1343 (mve_vec_sizename): New array with vector sizes.
1344 (enum vpt_pred_state): New enum with vector predication states.
1345 (struct vpt_block): New struct type for vpt blocks.
1346 (vpt_block_state): Global struct to keep track of state.
1347 (mve_extract_pred_mask): New helper function.
1348 (num_instructions_vpt_block): Likewise.
1349 (mark_outside_vpt_block): Likewise.
1350 (mark_inside_vpt_block): Likewise.
1351 (invert_next_predicate_state): Likewise.
1352 (update_next_predicate_state): Likewise.
1353 (update_vpt_block_state): Likewise.
1354 (is_vpt_instruction): Likewise.
1355 (is_mve_encoding_conflict): Add entries for new instructions.
1356 (is_mve_unpredictable): Likewise.
1357 (print_mve_unpredictable): Handle new cases.
1358 (print_instruction_predicate): Likewise.
1359 (print_mve_size): New function.
1360 (print_vec_condition): New function.
1361 (print_insn_mve): Handle vpt blocks and new print operands.
1362
f08d8ce3
AV		 13632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1364
1365 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1366 8, 14 and 15 for Armv8.1-M Mainline.
1367
73cd51e5
AV		 13682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1369 Michael Collison <michael.collison@arm.com>
1370
1371 * arm-dis.c (enum mve_instructions): New enum.
1372 (enum mve_unpredictable): Likewise.
1373 (enum mve_undefined): Likewise.
1374 (struct mopcode32): New struct.
1375 (is_mve_okay_in_it): New function.
1376 (is_mve_architecture): Likewise.
1377 (arm_decode_field): Likewise.
1378 (arm_decode_field_multiple): Likewise.
1379 (is_mve_encoding_conflict): Likewise.
1380 (is_mve_undefined): Likewise.
1381 (is_mve_unpredictable): Likewise.
1382 (print_mve_undefined): Likewise.
1383 (print_mve_unpredictable): Likewise.
1384 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1385 (print_insn_mve): New function.
1386 (print_insn_thumb32): Handle MVE architecture.
1387 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1388
3076e594
NC		 13892019-05-10 Nick Clifton <nickc@redhat.com>
1390
1391 PR 24538
1392 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1393 end of the table prematurely.
1394
387e7624
FS		 13952019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1396
1397 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1398 macros for R6.
1399
0067be51
AM		 14002019-05-11 Alan Modra <amodra@gmail.com>
1401
1402 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1403 when -Mraw is in effect.
1404
42e6288f
MM		 14052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1406
1407 * aarch64-dis-2.c: Regenerate.
1408 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1409 (OP_SVE_BBB): New variant set.
1410 (OP_SVE_DDDD): New variant set.
1411 (OP_SVE_HHH): New variant set.
1412 (OP_SVE_HHHU): New variant set.
1413 (OP_SVE_SSS): New variant set.
1414 (OP_SVE_SSSU): New variant set.
1415 (OP_SVE_SHH): New variant set.
1416 (OP_SVE_SBBU): New variant set.
1417 (OP_SVE_DSS): New variant set.
1418 (OP_SVE_DHHU): New variant set.
1419 (OP_SVE_VMV_HSD_BHS): New variant set.
1420 (OP_SVE_VVU_HSD_BHS): New variant set.
1421 (OP_SVE_VVVU_SD_BH): New variant set.
1422 (OP_SVE_VVVU_BHSD): New variant set.
1423 (OP_SVE_VVV_QHD_DBS): New variant set.
1424 (OP_SVE_VVV_HSD_BHS): New variant set.
1425 (OP_SVE_VVV_HSD_BHS2): New variant set.
1426 (OP_SVE_VVV_BHS_HSD): New variant set.
1427 (OP_SVE_VV_BHS_HSD): New variant set.
1428 (OP_SVE_VVV_SD): New variant set.
1429 (OP_SVE_VVU_BHS_HSD): New variant set.
1430 (OP_SVE_VZVV_SD): New variant set.
1431 (OP_SVE_VZVV_BH): New variant set.
1432 (OP_SVE_VZV_SD): New variant set.
1433 (aarch64_opcode_table): Add sve2 instructions.
1434
28ed815a
MM		 14352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1436
1437 * aarch64-asm-2.c: Regenerated.
1438 * aarch64-dis-2.c: Regenerated.
1439 * aarch64-opc-2.c: Regenerated.
1440 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1441 for SVE_SHLIMM_UNPRED_22.
1442 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1443 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1444 operand.
1445
fd1dc4a0
MM		 14462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1447
1448 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1449 sve_size_tsz_bhs iclass encode.
1450 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1451 sve_size_tsz_bhs iclass decode.
1452
31e36ab3
MM		 14532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1454
1455 * aarch64-asm-2.c: Regenerated.
1456 * aarch64-dis-2.c: Regenerated.
1457 * aarch64-opc-2.c: Regenerated.
1458 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1459 for SVE_Zm4_11_INDEX.
1460 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1461 (fields): Handle SVE_i2h field.
1462 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1463 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1464
1be5f94f
MM		 14652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1466
1467 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1468 sve_shift_tsz_bhsd iclass encode.
1469 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1470 sve_shift_tsz_bhsd iclass decode.
1471
3c17238b
MM		 14722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1473
1474 * aarch64-asm-2.c: Regenerated.
1475 * aarch64-dis-2.c: Regenerated.
1476 * aarch64-opc-2.c: Regenerated.
1477 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1478 (aarch64_encode_variant_using_iclass): Handle
1479 sve_shift_tsz_hsd iclass encode.
1480 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1481 sve_shift_tsz_hsd iclass decode.
1482 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1483 for SVE_SHRIMM_UNPRED_22.
1484 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1485 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1486 operand.
1487
cd50a87a
MM		 14882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1489
1490 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1491 sve_size_013 iclass encode.
1492 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1493 sve_size_013 iclass decode.
1494
3c705960
MM		 14952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1496
1497 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1498 sve_size_bh iclass encode.
1499 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1500 sve_size_bh iclass decode.
1501
0a57e14f
MM		 15022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1503
1504 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1505 sve_size_sd2 iclass encode.
1506 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1507 sve_size_sd2 iclass decode.
1508 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1509 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1510
c469c864
MM		 15112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1512
1513 * aarch64-asm-2.c: Regenerated.
1514 * aarch64-dis-2.c: Regenerated.
1515 * aarch64-opc-2.c: Regenerated.
1516 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1517 for SVE_ADDR_ZX.
1518 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1519 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1520
116adc27
MM		 15212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1522
1523 * aarch64-asm-2.c: Regenerated.
1524 * aarch64-dis-2.c: Regenerated.
1525 * aarch64-opc-2.c: Regenerated.
1526 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1527 for SVE_Zm3_11_INDEX.
1528 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1529 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1530 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1531 fields.
1532 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1533
3bd82c86
MM		 15342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1535
1536 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1537 sve_size_hsd2 iclass encode.
1538 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1539 sve_size_hsd2 iclass decode.
1540 * aarch64-opc.c (fields): Handle SVE_size field.
1541 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1542
adccc507
MM		 15432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1544
1545 * aarch64-asm-2.c: Regenerated.
1546 * aarch64-dis-2.c: Regenerated.
1547 * aarch64-opc-2.c: Regenerated.
1548 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1549 for SVE_IMM_ROT3.
1550 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1551 (fields): Handle SVE_rot3 field.
1552 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1553 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1554
5cd99750
MM		 15552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1556
1557 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1558 instructions.
1559
7ce2460a
MM		 15602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1561
1562 * aarch64-tbl.h
1563 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1564 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1565 aarch64_feature_sve2bitperm): New feature sets.
1566 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1567 for feature set addresses.
1568 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1569 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1570
41cee089
FS		 15712019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1572 Faraz Shahbazker <fshahbazker@wavecomp.com>
1573
1574 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1575 argument and set ASE_EVA_R6 appropriately.
1576 (set_default_mips_dis_options): Pass ISA to above.
1577 (parse_mips_dis_option): Likewise.
1578 * mips-opc.c (EVAR6): New macro.
1579 (mips_builtin_opcodes): Add llwpe, scwpe.
1580
b83b4b13
SD		 15812019-05-01 Sudakshina Das <sudi.das@arm.com>
1582
1583 * aarch64-asm-2.c: Regenerated.
1584 * aarch64-dis-2.c: Regenerated.
1585 * aarch64-opc-2.c: Regenerated.
1586 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1587 AARCH64_OPND_TME_UIMM16.
1588 (aarch64_print_operand): Likewise.
1589 * aarch64-tbl.h (QL_IMM_NIL): New.
1590 (TME): New.
1591 (_TME_INSN): New.
1592 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1593
4a90ce95
JD		 15942019-04-29 John Darrington <john@darrington.wattle.id.au>
1595
1596 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1597
a45328b9
AB		 15982019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1599 Faraz Shahbazker <fshahbazker@wavecomp.com>
1600
1601 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1602
d10be0cb
JD		 16032019-04-24 John Darrington <john@darrington.wattle.id.au>
1604
1605 * s12z-opc.h: Add extern "C" bracketing to help
1606 users who wish to use this interface in c++ code.
1607
a679f24e
JD		 16082019-04-24 John Darrington <john@darrington.wattle.id.au>
1609
1610 * s12z-opc.c (bm_decode): Handle bit map operations with the
1611 "reserved0" mode.
1612
32c36c3c
AV		 16132019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1614
1615 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1616 specifier. Add entries for VLDR and VSTR of system registers.
1617 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1618 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1619 of %J and %K format specifier.
1620
efd6b359
AV		 16212019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1622
1623 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1624 Add new entries for VSCCLRM instruction.
1625 (print_insn_coprocessor): Handle new %C format control code.
1626
6b0dd094
AV		 16272019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1628
1629 * arm-dis.c (enum isa): New enum.
1630 (struct sopcode32): New structure.
1631 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1632 set isa field of all current entries to ANY.
1633 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1634 Only match an entry if its isa field allows the current mode.
1635
4b5a202f
AV		 16362019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1637
1638 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1639 CLRM.
1640 (print_insn_thumb32): Add logic to print %n CLRM register list.
1641
60f993ce
AV		 16422019-04-15 Sudakshina Das <sudi.das@arm.com>
1643
1644 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1645 and %Q patterns.
1646
f6b2b12d
AV		 16472019-04-15 Sudakshina Das <sudi.das@arm.com>
1648
1649 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1650 (print_insn_thumb32): Edit the switch case for %Z.
1651
1889da70
AV		 16522019-04-15 Sudakshina Das <sudi.das@arm.com>
1653
1654 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1655
65d1bc05
AV		 16562019-04-15 Sudakshina Das <sudi.das@arm.com>
1657
1658 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1659
1caf72a5
AV		 16602019-04-15 Sudakshina Das <sudi.das@arm.com>
1661
1662 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1663
f1c7f421
AV		 16642019-04-15 Sudakshina Das <sudi.das@arm.com>
1665
1666 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1667 Arm register with r13 and r15 unpredictable.
1668 (thumb32_opcodes): New instructions for bfx and bflx.
1669
4389b29a
AV		 16702019-04-15 Sudakshina Das <sudi.das@arm.com>
1671
1672 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1673
e5d6e09e
AV		 16742019-04-15 Sudakshina Das <sudi.das@arm.com>
1675
1676 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1677
e12437dc
AV		 16782019-04-15 Sudakshina Das <sudi.das@arm.com>
1679
1680 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1681
031254f2
AV		 16822019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1683
1684 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1685
e5a557ac
JD		 16862019-04-12 John Darrington <john@darrington.wattle.id.au>
1687
1688 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1689 "optr". ("operator" is a reserved word in c++).
1690
bd7ceb8d
SD		 16912019-04-11 Sudakshina Das <sudi.das@arm.com>
1692
1693 * aarch64-opc.c (aarch64_print_operand): Add case for
1694 AARCH64_OPND_Rt_SP.
1695 (verify_constraints): Likewise.
1696 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1697 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1698 to accept Rt|SP as first operand.
1699 (AARCH64_OPERANDS): Add new Rt_SP.
1700 * aarch64-asm-2.c: Regenerated.
1701 * aarch64-dis-2.c: Regenerated.
1702 * aarch64-opc-2.c: Regenerated.
1703
e54010f1
SD		 17042019-04-11 Sudakshina Das <sudi.das@arm.com>
1705
1706 * aarch64-asm-2.c: Regenerated.
1707 * aarch64-dis-2.c: Likewise.
1708 * aarch64-opc-2.c: Likewise.
1709 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1710
7e96e219
RS		 17112019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1712
1713 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1714
6f2791d5
L		 17152019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1716
1717 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1718 * i386-init.h: Regenerated.
1719
e392bad3
AM		 17202019-04-07 Alan Modra <amodra@gmail.com>
1721
1722 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1723 op_separator to control printing of spaces, comma and parens
1724 rather than need_comma, need_paren and spaces vars.
1725
dffaa15c
AM		 17262019-04-07 Alan Modra <amodra@gmail.com>
1727
1728 PR 24421
1729 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1730 (print_insn_neon, print_insn_arm): Likewise.
1731
d6aab7a1
XG		 17322019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1733
1734 * i386-dis-evex.h (evex_table): Updated to support BF16
1735 instructions.
1736 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1737 and EVEX_W_0F3872_P_3.
1738 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1739 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1740 * i386-opc.h (enum): Add CpuAVX512_BF16.
1741 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1742 * i386-opc.tbl: Add AVX512 BF16 instructions.
1743 * i386-init.h: Regenerated.
1744 * i386-tbl.h: Likewise.
1745
66e85460
AM		 17462019-04-05 Alan Modra <amodra@gmail.com>
1747
1748 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1749 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1750 to favour printing of "-" branch hint when using the "y" bit.
1751 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1752
c2b1c275
AM		 17532019-04-05 Alan Modra <amodra@gmail.com>
1754
1755 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1756 opcode until first operand is output.
1757
aae9718e
PB		 17582019-04-04 Peter Bergner <bergner@linux.ibm.com>
1759
1760 PR gas/24349
1761 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1762 (valid_bo_post_v2): Add support for 'at' branch hints.
1763 (insert_bo): Only error on branch on ctr.
1764 (get_bo_hint_mask): New function.
1765 (insert_boe): Add new 'branch_taken' formal argument. Add support
1766 for inserting 'at' branch hints.
1767 (extract_boe): Add new 'branch_taken' formal argument. Add support
1768 for extracting 'at' branch hints.
1769 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1770 (BOE): Delete operand.
1771 (BOM, BOP): New operands.
1772 (RM): Update value.
1773 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1774 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1775 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1776 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1777 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1778 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1779 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1780 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1781 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1782 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1783 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1784 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1785 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1786 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1787 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1788 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1789 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1790 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1791 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1792 bttarl+>: New extended mnemonics.
1793
96a86c01
AM		 17942019-03-28 Alan Modra <amodra@gmail.com>
1795
1796 PR 24390
1797 * ppc-opc.c (BTF): Define.
1798 (powerpc_opcodes): Use for mtfsb*.
1799 * ppc-dis.c (print_insn_powerpc): Print fields with both
1800 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1801
796d6298
TC		 18022019-03-25 Tamar Christina <tamar.christina@arm.com>
1803
1804 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1805 (mapping_symbol_for_insn): Implement new algorithm.
1806 (print_insn): Remove duplicate code.
1807
60df3720
TC		 18082019-03-25 Tamar Christina <tamar.christina@arm.com>
1809
1810 * aarch64-dis.c (print_insn_aarch64):
1811 Implement override.
1812
51457761
TC		 18132019-03-25 Tamar Christina <tamar.christina@arm.com>
1814
1815 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1816 order.
1817
53b2f36b
TC		 18182019-03-25 Tamar Christina <tamar.christina@arm.com>
1819
1820 * aarch64-dis.c (last_stop_offset): New.
1821 (print_insn_aarch64): Use stop_offset.
1822
89199bb5
L		 18232019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1824
1825 PR gas/24359
1826 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1827 CPU_ANY_AVX2_FLAGS.
1828 * i386-init.h: Regenerated.
1829
97ed31ae
L		 18302019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1831
1832 PR gas/24348
1833 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1834 vmovdqu16, vmovdqu32 and vmovdqu64.
1835 * i386-tbl.h: Regenerated.
1836
0919bfe9
AK		 18372019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1838
1839 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1840 from vstrszb, vstrszh, and vstrszf.
1841
18422019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1843
1844 * s390-opc.txt: Add instruction descriptions.
1845
21820ebe
JW		 18462019-02-08 Jim Wilson <jimw@sifive.com>
1847
1848 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1849 <bne>: Likewise.
1850
f7dd2fb2
TC		 18512019-02-07 Tamar Christina <tamar.christina@arm.com>
1852
1853 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1854
6456d318
TC		 18552019-02-07 Tamar Christina <tamar.christina@arm.com>
1856
1857 PR binutils/23212
1858 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1859 * aarch64-opc.c (verify_elem_sd): New.
1860 (fields): Add FLD_sz entr.
1861 * aarch64-tbl.h (_SIMD_INSN): New.
1862 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1863 fmulx scalar and vector by element isns.
1864
4a83b610
NC		 18652019-02-07 Nick Clifton <nickc@redhat.com>
1866
1867 * po/sv.po: Updated Swedish translation.
1868
fc60b8c8
AK		 18692019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1870
1871 * s390-mkopc.c (main): Accept arch13 as cpu string.
1872 * s390-opc.c: Add new instruction formats and instruction opcode
1873 masks.
1874 * s390-opc.txt: Add new arch13 instructions.
1875
e10620d3
TC		 18762019-01-25 Sudakshina Das <sudi.das@arm.com>
1877
1878 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1879 (aarch64_opcode): Change encoding for stg, stzg
1880 st2g and st2zg.
1881 * aarch64-asm-2.c: Regenerated.
1882 * aarch64-dis-2.c: Regenerated.
1883 * aarch64-opc-2.c: Regenerated.
1884
20a4ca55
SD		 18852019-01-25 Sudakshina Das <sudi.das@arm.com>
1886
1887 * aarch64-asm-2.c: Regenerated.
1888 * aarch64-dis-2.c: Likewise.
1889 * aarch64-opc-2.c: Likewise.
1890 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1891
550fd7bf
SD		 18922019-01-25 Sudakshina Das <sudi.das@arm.com>
1893 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1894
1895 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1896 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1897 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1898 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1899 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1900 case for ldstgv_indexed.
1901 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1902 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1903 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1904 * aarch64-asm-2.c: Regenerated.
1905 * aarch64-dis-2.c: Regenerated.
1906 * aarch64-opc-2.c: Regenerated.
1907
d9938630
NC		 19082019-01-23 Nick Clifton <nickc@redhat.com>
1909
1910 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1911
375cd423
NC		 19122019-01-21 Nick Clifton <nickc@redhat.com>
1913
1914 * po/de.po: Updated German translation.
1915 * po/uk.po: Updated Ukranian translation.
1916
57299f48
CX		 19172019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1918 * mips-dis.c (mips_arch_choices): Fix typo in
1919 gs464, gs464e and gs264e descriptors.
1920
f48dfe41
NC		 19212019-01-19 Nick Clifton <nickc@redhat.com>
1922
1923 * configure: Regenerate.
1924 * po/opcodes.pot: Regenerate.
1925
f974f26c
NC		 19262018-06-24 Nick Clifton <nickc@redhat.com>
1927
1928 2.32 branch created.
1929
39f286cd
JD		 19302019-01-09 John Darrington <john@darrington.wattle.id.au>
1931
448b8ca8
JD		 1932 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1933 if it is null.
1934 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1935 zero.
1936
3107326d
AP		 19372019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1938
1939 * configure: Regenerate.
1940
7e9ca91e
AM		 19412019-01-07 Alan Modra <amodra@gmail.com>
1942
1943 * configure: Regenerate.
1944 * po/POTFILES.in: Regenerate.
1945
ef1ad42b
JD		 19462019-01-03 John Darrington <john@darrington.wattle.id.au>
1947
1948 * s12z-opc.c: New file.
1949 * s12z-opc.h: New file.
1950 * s12z-dis.c: Removed all code not directly related to display
1951 of instructions. Used the interface provided by the new files
1952 instead.
1953 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1954 * Makefile.in: Regenerate.
ef1ad42b 1955 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1956 * configure: Regenerate.
ef1ad42b 1957
82704155
AM		 19582019-01-01 Alan Modra <amodra@gmail.com>
1959
1960 Update year range in copyright notice of all files.
1961
d5c04e1b 1962For older changes see ChangeLog-2018
3499769a 1963\f
d5c04e1b 1964Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1965
1966Copying and distribution of this file, with or without modification,
1967are permitted in any medium without royalty provided the copyright
1968notice and this notice are preserved.
1969
1970Local Variables:
1971mode: change-log
1972left-margin: 8
1973fill-column: 74
1974version-control: never
1975End:
GDB Binutils - Deliverables
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