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ubsan: bfin-dis.c:160 shift exponent 32 is too large
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
427202d9
AM		 12020-09-02 Alan Modra <amodra@gmail.com>
2
3 * bfin-dis.c (MASKBITS): Use SIGNBIT.
4
4211a340
CQ		 52020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
6
7 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
8 to CSKYV2_ISA_3E3R3 instruction set.
9
8119cc38
CQ		 102020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
11
12 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
13
8dbe96f0
AM		 142020-09-01 Alan Modra <amodra@gmail.com>
15
16 * mep-ibld.c: Regenerate.
17
e2e82b11
CQ		 182020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
19
20 * csky-dis.c (csky_output_operand): Assign dis_info.value for
21 OPRND_TYPE_VREG.
22
2781f857
AM		 232020-08-30 Alan Modra <amodra@gmail.com>
24
25 * cr16-dis.c: Formatting.
26 (parameter): Delete struct typedef. Use dwordU instead
27 throughout file.
28 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
29 and tbitb.
30 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
31
0c0577f6
AM		 322020-08-29 Alan Modra <amodra@gmail.com>
33
34 PR 26446
35 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
36 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
37
a1e60a1b
AM		 382020-08-28 Alan Modra <amodra@gmail.com>
39
40 PR 26449
41 PR 26450
42 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
43 (extract_normal): Likewise.
44 (insert_normal): Likewise, and move past zero length test.
45 (put_insn_int_value): Handle mask for zero length, use 1UL.
46 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
47 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
48 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
49 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
50
0861f561
CQ		 512020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
52
53 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
54 (csky_dis_info): Add member isa.
55 (csky_find_inst_info): Skip instructions that do not belong to
56 current CPU.
57 (csky_get_disassembler): Get infomation from attribute section.
58 (print_insn_csky): Set defualt ISA flag.
59 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
60 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
61 isa_flag32'type to unsigned 64 bits.
62
31b3f3e6
JM		 632020-08-26 Jose E. Marchesi <jemarch@gnu.org>
64
65 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
66
4449c81a
DF		 672020-08-26 David Faust <david.faust@oracle.com>
68
69 * bpf-desc.c: Regenerate.
70 * bpf-desc.h: Likewise.
71 * bpf-opc.c: Likewise.
72 * bpf-opc.h: Likewise.
73 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
74 ISA when appropriate.
75
8640c87d
AM		 762020-08-25 Alan Modra <amodra@gmail.com>
77
78 PR 26504
79 * vax-dis.c (parse_disassembler_options): Always add at least one
80 to entry_addr_total_slots.
81
531c73a3
CQ		 822020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
83
84 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
85 in other CPUs to speed up disassembling.
86 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
87 Change plsli.u16 to plsli.16, change sync's operand format.
88
d04aee0f
CQ		 892020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
90
91 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
92
ccf61261
NC		 932020-08-21 Nick Clifton <nickc@redhat.com>
94
95 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
96 symbols.
97
d285ba8d
CQ		 982020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
99
100 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
101
18a8a00e
AM		 1022020-08-19 Alan Modra <amodra@gmail.com>
103
104 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
105 vcmpuq and xvtlsbb.
106
587a4371
PB		 1072020-08-18 Peter Bergner <bergner@linux.ibm.com>
108
109 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
110 <xvcvbf16spn>: ...to this.
111
2e49fd1e
AC		 1122020-08-12 Alex Coplan <alex.coplan@arm.com>
113
114 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
115
79ddc884
NC		 1162020-08-12 Nick Clifton <nickc@redhat.com>
117
118 * po/sr.po: Updated Serbian translation.
119
08770ec2
AM		 1202020-08-11 Alan Modra <amodra@gmail.com>
121
122 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
123
f7cb161e
PW		 1242020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
125
126 * aarch64-opc.c (aarch64_print_operand):
127 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
128 (aarch64_sys_reg_supported_p): Function removed.
129 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
130 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
131 into this function.
132
3eb65174
AM		 1332020-08-10 Alan Modra <amodra@gmail.com>
134
135 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
136 instructions.
137
8b2742a1
AM		 1382020-08-10 Alan Modra <amodra@gmail.com>
139
140 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
141 Enable icbt for power5, miso for power8.
142
5fbec329
AM		 1432020-08-10 Alan Modra <amodra@gmail.com>
144
145 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
146 mtvsrd, and similarly for mfvsrd.
147
563a3225
CG		 1482020-08-04 Christian Groessler <chris@groessler.org>
149 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
150
151 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
152 opcodes (special "out" to absolute address).
153 * z8k-opc.h: Regenerate.
154
41eb8e88
L		 1552020-07-30 H.J. Lu <hongjiu.lu@intel.com>
156
157 PR gas/26305
158 * i386-opc.h (Prefix_Disp8): New.
159 (Prefix_Disp16): Likewise.
160 (Prefix_Disp32): Likewise.
161 (Prefix_Load): Likewise.
162 (Prefix_Store): Likewise.
163 (Prefix_VEX): Likewise.
164 (Prefix_VEX3): Likewise.
165 (Prefix_EVEX): Likewise.
166 (Prefix_REX): Likewise.
167 (Prefix_NoOptimize): Likewise.
168 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
169 * i386-tbl.h: Regenerated.
170
98116973
AA		 1712020-07-29 Andreas Arnez <arnez@linux.ibm.com>
172
173 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
174 default case with abort() instead of printing an error message and
175 continuing, to avoid a maybe-uninitialized warning.
176
2dddfa20
NC		 1772020-07-24 Nick Clifton <nickc@redhat.com>
178
179 * po/de.po: Updated German translation.
180
bf4ba07c
JB		 1812020-07-21 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (OP_E_memory): Revert previous change.
184
04c662e2
L		 1852020-07-15 H.J. Lu <hongjiu.lu@intel.com>
186
187 PR gas/26237
188 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
189 without base nor index registers.
190
f0e8d0ba
JB		 1912020-07-15 Jan Beulich <jbeulich@suse.com>
192
193 * i386-dis.c (putop): Move 'V' and 'W' handling.
194
c3f5525f
JB		 1952020-07-15 Jan Beulich <jbeulich@suse.com>
196
197 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
198 construct for push/pop of register.
199 (putop): Honor cond when handling 'P'. Drop handling of plain
200 'V'.
201
36938cab
JB		 2022020-07-15 Jan Beulich <jbeulich@suse.com>
203
204 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
205 description. Drop '&' description. Use P for push of immediate,
206 pushf/popf, enter, and leave. Use %LP for lret/retf.
207 (dis386_twobyte): Use P for push/pop of fs/gs.
208 (reg_table): Use P for push/pop. Use @ for near call/jmp.
209 (x86_64_table): Use P for far call/jmp.
210 (putop): Drop handling of 'U' and '&'. Move and adjust handling
211 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
212 labels.
213 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
214 and dqw_mode (unconditional).
215
8e58ef80
L		 2162020-07-14 H.J. Lu <hongjiu.lu@intel.com>
217
218 PR gas/26237
219 * i386-dis.c (OP_E_memory): Without base nor index registers,
220 32-bit displacement to 64 bits.
221
570b0ed6
CZ		 2222020-07-14 Claudiu Zissulescu <claziss@gmail.com>
223
224 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
225 faulty double register pair is detected.
226
bfbd9438
JB		 2272020-07-14 Jan Beulich <jbeulich@suse.com>
228
229 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
230
78467458
JB		 2312020-07-14 Jan Beulich <jbeulich@suse.com>
232
233 * i386-dis.c (OP_R, Rm): Delete.
234 (MOD_0F24, MOD_0F26): Rename to ...
235 (X86_64_0F24, X86_64_0F26): ... respectively.
236 (dis386): Update 'L' and 'Z' comments.
237 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
238 table references.
239 (mod_table): Move opcode 0F24 and 0F26 entries ...
240 (x86_64_table): ... here.
241 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
242 'Z' case block.
243
464d2b65
JB		 2442020-07-14 Jan Beulich <jbeulich@suse.com>
245
246 * i386-dis.c (Rd, Rdq, MaskR): Delete.
247 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
248 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
249 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
250 MOD_EVEX_0F387C): New enumerators.
251 (reg_table): Use Edq for rdssp.
252 (prefix_table): Use Edq for incssp.
253 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
254 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
255 ktest*, and kshift*. Use Edq / MaskE for kmov*.
256 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
257 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
258 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
259 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
260 0F3828_P_1 and 0F3838_P_1.
261 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
262 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
263
035e7389
JB		 2642020-07-14 Jan Beulich <jbeulich@suse.com>
265
266 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
267 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
268 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
269 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
270 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
271 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
272 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
273 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
274 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
275 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
276 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
277 (reg_table, prefix_table, three_byte_table, vex_table,
278 vex_len_table, mod_table, rm_table): Replace / remove respective
279 entries.
280 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
281 of PREFIX_DATA in used_prefixes.
282
bb5b3501
JB		 2832020-07-14 Jan Beulich <jbeulich@suse.com>
284
285 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
286 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
287 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
288 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
289 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
290 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
291 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
292 VEX_W_0F3A33_L_0): Delete.
293 (dis386): Adjust "BW" description.
294 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
295 0F3A31, 0F3A32, and 0F3A33.
296 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
297 entries.
298 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
299 entries.
300
7531c613
JB		 3012020-07-14 Jan Beulich <jbeulich@suse.com>
302
303 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
304 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
305 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
306 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
307 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
308 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
309 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
310 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
311 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
312 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
313 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
314 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
315 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
316 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
317 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
318 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
319 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
320 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
321 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
322 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
323 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
324 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
325 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
326 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
327 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
328 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
329 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
330 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
331 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
332 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
333 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
334 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
335 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
336 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
337 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
338 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
339 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
340 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
341 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
342 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
343 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
344 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
345 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
346 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
347 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
348 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
349 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
350 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
351 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
352 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
353 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
354 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
355 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
356 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
357 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
358 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
359 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
360 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
361 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
362 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
363 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
364 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
365 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
366 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
367 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
368 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
369 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
370 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
371 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
372 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
373 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
374 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
375 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
376 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
377 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
378 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
379 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
380 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
381 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
382 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
383 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
384 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
385 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
386 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
387 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
388 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
389 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
390 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
391 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
392 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
393 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
394 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
395 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
396 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
397 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
398 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
399 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
400 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
401 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
402 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
403 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
404 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
405 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
406 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
407 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
408 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
409 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
410 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
411 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
412 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
413 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
414 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
415 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
416 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
417 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
418 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
419 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
420 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
421 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
422 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
423 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
424 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
425 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
426 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
427 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
428 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
429 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
430 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
431 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
432 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
433 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
434 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
435 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
436 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
437 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
438 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
439 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
440 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
441 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
442 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
443 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
444 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
445 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
446 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
447 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
448 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
449 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
450 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
451 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
452 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
453 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
454 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
455 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
456 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
457 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
458 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
459 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
460 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
461 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
462 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
463 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
464 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
465 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
466 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
467 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
468 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
469 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
470 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
471 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
472 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
473 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
474 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
475 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
476 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
477 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
478 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
479 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
480 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
481 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
482 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
483 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
484 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
485 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
486 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
487 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
488 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
489 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
490 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
491 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
492 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
493 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
494 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
495 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
496 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
497 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
498 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
499 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
500 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
501 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
502 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
503 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
504 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
505 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
506 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
507 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
508 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
509 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
510 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
511 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
512 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
513 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
514 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
515 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
516 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
517 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
518 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
519 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
520 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
521 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
522 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
523 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
524 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
525 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
526 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
527 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
528 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
529 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
530 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
531 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
532 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
533 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
534 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
535 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
536 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
537 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
538 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
539 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
540 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
541 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
542 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
543 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
544 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
545 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
546 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
547 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
548 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
549 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
550 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
551 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
552 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
553 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
554 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
555 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
556 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
557 EVEX_W_0F3A72_P_2): Rename to ...
558 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
559 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
560 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
561 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
562 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
563 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
564 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
565 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
566 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
567 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
568 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
569 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
570 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
571 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
572 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
573 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
574 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
575 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
576 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
577 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
578 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
579 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
580 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
581 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
582 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
583 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
584 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
585 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
586 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
587 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
588 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
589 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
590 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
591 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
592 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
593 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
594 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
595 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
596 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
597 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
598 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
599 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
600 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
601 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
602 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
603 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
604 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
605 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
606 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
607 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
608 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
609 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
610 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
611 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
612 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
613 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
614 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
615 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
616 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
617 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
618 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
619 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
620 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
621 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
622 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
623 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
624 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
625 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
626 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
627 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
628 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
629 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
630 respectively.
631 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
632 vex_w_table, mod_table): Replace / remove respective entries.
633 (print_insn): Move up dp->prefix_requirement handling. Handle
634 PREFIX_DATA.
635 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
636 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
637 Replace / remove respective entries.
638
17d3c7ec
JB		 6392020-07-14 Jan Beulich <jbeulich@suse.com>
640
641 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
642 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
643 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
644 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
645 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
646 the latter two.
647 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
648 0F2C, 0F2D, 0F2E, and 0F2F.
649 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
650 0F2F table entries.
651
41f5efc6
JB		 6522020-07-14 Jan Beulich <jbeulich@suse.com>
653
654 * i386-dis.c (OP_VexR, VexScalarR): New.
655 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
656 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
657 need_vex_reg): Delete.
658 (prefix_table): Replace VexScalar by VexScalarR and
659 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
660 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
661 (vex_len_table): Replace EXqVexScalarS by EXqS.
662 (get_valid_dis386): Don't set need_vex_reg.
663 (print_insn): Don't initialize need_vex_reg.
664 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
665 q_scalar_swap_mode cases.
666 (OP_EX): Don't check for d_scalar_swap_mode and
667 q_scalar_swap_mode.
668 (OP_VEX): Done check need_vex_reg.
669 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
670 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
671 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
672
89e65d17
JB		 6732020-07-14 Jan Beulich <jbeulich@suse.com>
674
675 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
676 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
677 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
678 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
679 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
680 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
681 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
682 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
683 (vex_table): Replace Vex128 by Vex.
684 (vex_len_table): Likewise. Adjust referenced enum names.
685 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
686 referenced enum names.
687 (OP_VEX): Drop vex128_mode and vex256_mode cases.
688 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
689
492a76aa
JB		 6902020-07-14 Jan Beulich <jbeulich@suse.com>
691
692 * i386-dis.c (dis386): "LW" description now applies to "DQ".
693 (putop): Handle "DQ". Don't handle "LW" anymore.
694 (prefix_table, mod_table): Replace %LW by %DQ.
695 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
696
059edf8b
JB		 6972020-07-14 Jan Beulich <jbeulich@suse.com>
698
699 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
700 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
701 d_scalar_swap_mode case handling. Move shift adjsutment into
702 the case its applicable to.
703
4726e9a4
JB		 7042020-07-14 Jan Beulich <jbeulich@suse.com>
705
706 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
707 (EXbScalar, EXwScalar): Fold to ...
708 (EXbwUnit): ... this.
709 (b_scalar_mode, w_scalar_mode): Fold to ...
710 (bw_unit_mode): ... this.
711 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
712 w_scalar_mode handling by bw_unit_mode one.
713 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
714 ...
715 * i386-dis-evex-prefix.h: ... here.
716
b24d668c
JB		 7172020-07-14 Jan Beulich <jbeulich@suse.com>
718
719 * i386-dis.c (PCMPESTR_Fixup): Delete.
720 (dis386): Adjust "LQ" description.
721 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
722 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
723 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
724 vpcmpestrm, and vpcmpestri.
725 (putop): Honor "cond" when handling LQ.
726 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
727 vcvtsi2ss and vcvtusi2ss.
728 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
729 vcvtsi2sd and vcvtusi2sd.
730
c4de7606
JB		 7312020-07-14 Jan Beulich <jbeulich@suse.com>
732
733 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
734 (simd_cmp_op): Add const.
735 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
736 (CMP_Fixup): Handle VEX case.
737 (prefix_table): Replace VCMP by CMP.
738 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
739
9ab00b61
JB		 7402020-07-14 Jan Beulich <jbeulich@suse.com>
741
742 * i386-dis.c (MOVBE_Fixup): Delete.
743 (Mv): Define.
744 (prefix_table): Use Mv for movbe entries.
745
2875b28a
JB		 7462020-07-14 Jan Beulich <jbeulich@suse.com>
747
748 * i386-dis.c (CRC32_Fixup): Delete.
749 (prefix_table): Use Eb/Ev for crc32 entries.
750
e184e611
JB		 7512020-07-14 Jan Beulich <jbeulich@suse.com>
752
753 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
754 Conditionalize invocations of "USED_REX (0)".
755
e8b5d5f9
JB		 7562020-07-14 Jan Beulich <jbeulich@suse.com>
757
758 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
759 CH, DH, BH, AX, DX): Delete.
760 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
761 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
762 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
763
260cd341
LC		 7642020-07-10 Lili Cui <lili.cui@intel.com>
765
766 * i386-dis.c (TMM): New.
767 (EXtmm): Likewise.
768 (VexTmm): Likewise.
769 (MVexSIBMEM): Likewise.
770 (tmm_mode): Likewise.
771 (vex_sibmem_mode): Likewise.
772 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
773 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
774 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
775 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
776 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
777 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
778 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
779 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
780 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
781 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
782 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
783 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
784 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
785 (PREFIX_VEX_0F3849_X86_64): Likewise.
786 (PREFIX_VEX_0F384B_X86_64): Likewise.
787 (PREFIX_VEX_0F385C_X86_64): Likewise.
788 (PREFIX_VEX_0F385E_X86_64): Likewise.
789 (X86_64_VEX_0F3849): Likewise.
790 (X86_64_VEX_0F384B): Likewise.
791 (X86_64_VEX_0F385C): Likewise.
792 (X86_64_VEX_0F385E): Likewise.
793 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
794 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
795 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
796 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
797 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
798 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
799 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
800 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
801 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
802 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
803 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
804 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
805 (VEX_W_0F3849_X86_64_P_0): Likewise.
806 (VEX_W_0F3849_X86_64_P_2): Likewise.
807 (VEX_W_0F3849_X86_64_P_3): Likewise.
808 (VEX_W_0F384B_X86_64_P_1): Likewise.
809 (VEX_W_0F384B_X86_64_P_2): Likewise.
810 (VEX_W_0F384B_X86_64_P_3): Likewise.
811 (VEX_W_0F385C_X86_64_P_1): Likewise.
812 (VEX_W_0F385E_X86_64_P_0): Likewise.
813 (VEX_W_0F385E_X86_64_P_1): Likewise.
814 (VEX_W_0F385E_X86_64_P_2): Likewise.
815 (VEX_W_0F385E_X86_64_P_3): Likewise.
816 (names_tmm): Likewise.
817 (att_names_tmm): Likewise.
818 (intel_operand_size): Handle void_mode.
819 (OP_XMM): Handle tmm_mode.
820 (OP_EX): Likewise.
821 (OP_VEX): Likewise.
822 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
823 CpuAMX_BF16 and CpuAMX_TILE.
824 (operand_type_shorthands): Add RegTMM.
825 (operand_type_init): Likewise.
826 (operand_types): Add Tmmword.
827 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
828 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
829 * i386-opc.h (CpuAMX_INT8): New.
830 (CpuAMX_BF16): Likewise.
831 (CpuAMX_TILE): Likewise.
832 (SIBMEM): Likewise.
833 (Tmmword): Likewise.
834 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
835 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
836 (i386_operand_type): Add tmmword.
837 * i386-opc.tbl: Add AMX instructions.
838 * i386-reg.tbl: Add AMX registers.
839 * i386-init.h: Regenerated.
840 * i386-tbl.h: Likewise.
841
467bbef0
JB		 8422020-07-08 Jan Beulich <jbeulich@suse.com>
843
844 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
845 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
846 Rename to ...
847 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
848 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
849 respectively.
850 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
851 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
852 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
853 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
854 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
855 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
856 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
857 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
858 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
859 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
860 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
861 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
862 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
863 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
864 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
865 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
866 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
867 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
868 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
869 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
870 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
871 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
872 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
873 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
874 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
875 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
876 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
877 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
878 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
879 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
880 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
881 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
882 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
883 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
884 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
885 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
886 (reg_table): Re-order XOP entries. Adjust their operands.
887 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
888 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
889 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
890 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
891 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
892 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
893 entries by references ...
894 (vex_len_table): ... to resepctive new entries here. For several
895 new and existing entries reference ...
896 (vex_w_table): ... new entries here.
897 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
898
6384fd9e
JB		 8992020-07-08 Jan Beulich <jbeulich@suse.com>
900
901 * i386-dis.c (XMVexScalarI4): Define.
902 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
903 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
904 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
905 (vex_len_table): Move scalar FMA4 entries ...
906 (prefix_table): ... here.
907 (OP_REG_VexI4): Handle scalar_mode.
908 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
909 * i386-tbl.h: Re-generate.
910
e6123d0c
JB		 9112020-07-08 Jan Beulich <jbeulich@suse.com>
912
913 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
914 Vex_2src_2): Delete.
915 (OP_VexW, VexW): New.
916 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
917 for shifts and rotates by register.
918
93abb146
JB		 9192020-07-08 Jan Beulich <jbeulich@suse.com>
920
921 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
922 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
923 OP_EX_VexReg): Delete.
924 (OP_VexI4, VexI4): New.
925 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
926 (prefix_table): ... here.
927 (print_insn): Drop setting of vex_w_done.
928
b13b1bc0
JB		 9292020-07-08 Jan Beulich <jbeulich@suse.com>
930
931 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
932 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
933 (xop_table): Replace operands of 4-operand insns.
934 (OP_REG_VexI4): Move VEX.W based operand swaping here.
935
f337259f
CZ		 9362020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
937
938 * arc-opc.c (insert_rbd): New function.
939 (RBD): Define.
940 (RBDdup): Likewise.
941 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
942 instructions.
943
931452b6
JB		 9442020-07-07 Jan Beulich <jbeulich@suse.com>
945
946 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
947 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
948 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
949 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
950 Delete.
951 (putop): Handle "BW".
952 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
953 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
954 and 0F3A3F ...
955 * i386-dis-evex-prefix.h: ... here.
956
b5b098c2
JB		 9572020-07-06 Jan Beulich <jbeulich@suse.com>
958
959 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
960 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
961 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
962 VEX_W_0FXOP_09_83): New enumerators.
963 (xop_table): Reference the above.
964 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
965 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
966 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
967 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
968
21a3faeb
JB		 9692020-07-06 Jan Beulich <jbeulich@suse.com>
970
971 * i386-dis.c (EVEX_W_0F3838_P_1,
972 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
973 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
974 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
975 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
976 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
977 (putop): Centralize management of last[]. Delete SAVE_LAST.
978 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
979 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
980 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
981 * i386-dis-evex-prefix.h: here.
982
bc152a17
JB		 9832020-07-06 Jan Beulich <jbeulich@suse.com>
984
985 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
986 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
987 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
988 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
989 enumerators.
990 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
991 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
992 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
993 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
994 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
995 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
996 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
997 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
998 these, respectively.
999 * i386-dis-evex-len.h: Adjust comments.
1000 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1001 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1002 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1003 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1004 MOD_EVEX_0F385B_P_2_W_1 table entries.
1005 * i386-dis-evex-w.h: Reference mod_table[] for
1006 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1007 EVEX_W_0F385B_P_2.
1008
c82a99a0
JB		 10092020-07-06 Jan Beulich <jbeulich@suse.com>
1010
1011 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1012 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1013 EXymm.
1014 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1015 Likewise. Mark 256-bit entries invalid.
1016
fedfb81e
JB		 10172020-07-06 Jan Beulich <jbeulich@suse.com>
1018
1019 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1020 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1021 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1022 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1023 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1024 PREFIX_EVEX_0F382B): Delete.
1025 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1026 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1027 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1028 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1029 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1030 to ...
1031 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1032 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1033 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1034 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1035 respectively.
1036 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1037 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1038 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1039 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1040 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1041 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1042 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1043 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1044 PREFIX_EVEX_0F382B): Remove table entries.
1045 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1046 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1047 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1048
3a57774c
JB		 10492020-07-06 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1052 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1053 enumerators.
1054 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1055 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1056 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1057 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1058 entries.
1059
e74d9fa9
JB		 10602020-07-06 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1063 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1064 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1065 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1066 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1067 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1068 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1069 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1070 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1071 entries.
1072
6431c801
JB		 10732020-07-06 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1076 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1077 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1078 respectively.
1079 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1080 entries.
1081 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1082 opcode 0F3A1D.
1083 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1084 entry.
1085 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1086
6df22cf6
JB		 10872020-07-06 Jan Beulich <jbeulich@suse.com>
1088
1089 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1090 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1091 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1092 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1093 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1094 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1095 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1096 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1097 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1098 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1099 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1100 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1101 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1102 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1103 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1104 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1105 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1106 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1107 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1108 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1109 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1110 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1111 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1112 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1113 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1114 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1115 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1116 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1117 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1118 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1119 (prefix_table): Add EXxEVexR to FMA table entries.
1120 (OP_Rounding): Move abort() invocation.
1121 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1122 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1123 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1124 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1125 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1126 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1127 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1128 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1129 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1130 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1131 0F3ACE, 0F3ACF.
1132 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1133 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1134 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1135 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1136 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1137 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1138 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1139 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1140 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1141 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1142 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1143 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1144 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1145 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1146 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1147 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1148 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1149 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1150 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1151 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1152 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1153 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1154 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1155 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1156 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1157 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1158 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1159 Delete table entries.
1160 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1161 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1162 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1163 Likewise.
1164
39e0f456
JB		 11652020-07-06 Jan Beulich <jbeulich@suse.com>
1166
1167 * i386-dis.c (EXqScalarS): Delete.
1168 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1169 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1170
5b872f7d
JB		 11712020-07-06 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-dis.c (safe-ctype.h): Include.
1174 (EXdScalar, EXqScalar): Delete.
1175 (d_scalar_mode, q_scalar_mode): Delete.
1176 (prefix_table, vex_len_table): Use EXxmm_md in place of
1177 EXdScalar and EXxmm_mq in place of EXqScalar.
1178 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1179 d_scalar_mode and q_scalar_mode.
1180 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1181 (vmovsd): Use EXxmm_mq.
1182
ddc73fa9
NC		 11832020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1184
1185 PR 26204
1186 * arc-dis.c: Fix spelling mistake.
1187 * po/opcodes.pot: Regenerate.
1188
17550be7
NC		 11892020-07-06 Nick Clifton <nickc@redhat.com>
1190
1191 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1192 * po/uk.po: Updated Ukranian translation.
1193
b19d852d
NC		 11942020-07-04 Nick Clifton <nickc@redhat.com>
1195
1196 * configure: Regenerate.
1197 * po/opcodes.pot: Regenerate.
1198
b115b9fd
NC		 11992020-07-04 Nick Clifton <nickc@redhat.com>
1200
1201 Binutils 2.35 branch created.
1202
c2ecccb3
L		 12032020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1204
1205 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1206 * i386-opc.h (VexSwapSources): New.
1207 (i386_opcode_modifier): Add vexswapsources.
1208 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1209 with two source operands swapped.
1210 * i386-tbl.h: Regenerated.
1211
08ccfccf
NC		 12122020-06-30 Nelson Chu <nelson.chu@sifive.com>
1213
1214 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1215 unprivileged CSR can also be initialized.
1216
279edac5
AM		 12172020-06-29 Alan Modra <amodra@gmail.com>
1218
1219 * arm-dis.c: Use C style comments.
1220 * cr16-opc.c: Likewise.
1221 * ft32-dis.c: Likewise.
1222 * moxie-opc.c: Likewise.
1223 * tic54x-dis.c: Likewise.
1224 * s12z-opc.c: Remove useless comment.
1225 * xgate-dis.c: Likewise.
1226
e978ad62
L		 12272020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 * i386-opc.tbl: Add a blank line.
1230
63112cd6
L		 12312020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1232
1233 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1234 (VecSIB128): Renamed to ...
1235 (VECSIB128): This.
1236 (VecSIB256): Renamed to ...
1237 (VECSIB256): This.
1238 (VecSIB512): Renamed to ...
1239 (VECSIB512): This.
1240 (VecSIB): Renamed to ...
1241 (SIB): This.
1242 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1243 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1244 (VecSIB256): Likewise.
1245 (VecSIB512): Likewise.
79b32e73 1246 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1247 and VecSIB512, respectively.
1248
d1c36125
JB		 12492020-06-26 Jan Beulich <jbeulich@suse.com>
1250
1251 * i386-dis.c: Adjust description of I macro.
1252 (x86_64_table): Drop use of I.
1253 (float_mem): Replace use of I.
1254 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1255
2a1bb84c
JB		 12562020-06-26 Jan Beulich <jbeulich@suse.com>
1257
1258 * i386-dis.c: (print_insn): Avoid straight assignment to
1259 priv.orig_sizeflag when processing -M sub-options.
1260
8f570d62
JB		 12612020-06-25 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-dis.c: Adjust description of J macro.
1264 (dis386, x86_64_table, mod_table): Replace J.
1265 (putop): Remove handling of J.
1266
464dc4af
JB		 12672020-06-25 Jan Beulich <jbeulich@suse.com>
1268
1269 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1270
589958d6
JB		 12712020-06-25 Jan Beulich <jbeulich@suse.com>
1272
1273 * i386-dis.c: Adjust description of "LQ" macro.
1274 (dis386_twobyte): Use LQ for sysret.
1275 (putop): Adjust handling of LQ.
1276
39ff0b81
NC		 12772020-06-22 Nelson Chu <nelson.chu@sifive.com>
1278
1279 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1280 * riscv-dis.c: Include elfxx-riscv.h.
1281
d27c357a
JB		 12822020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1283
1284 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1285
6fde587f
CL		 12862020-06-17 Lili Cui <lili.cui@intel.com>
1287
1288 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1289
efe30057
L		 12902020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1291
1292 PR gas/26115
1293 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1294 * i386-opc.tbl: Likewise.
1295 * i386-tbl.h: Regenerated.
1296
d8af286f
NC		 12972020-06-12 Nelson Chu <nelson.chu@sifive.com>
1298
1299 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1300
14962256
AC		 13012020-06-11 Alex Coplan <alex.coplan@arm.com>
1302
1303 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1304 (SR_CORE): Likewise.
1305 (SR_FEAT): Likewise.
1306 (SR_RNG): Likewise.
1307 (SR_V8_1): Likewise.
1308 (SR_V8_2): Likewise.
1309 (SR_V8_3): Likewise.
1310 (SR_V8_4): Likewise.
1311 (SR_PAN): Likewise.
1312 (SR_RAS): Likewise.
1313 (SR_SSBS): Likewise.
1314 (SR_SVE): Likewise.
1315 (SR_ID_PFR2): Likewise.
1316 (SR_PROFILE): Likewise.
1317 (SR_MEMTAG): Likewise.
1318 (SR_SCXTNUM): Likewise.
1319 (aarch64_sys_regs): Refactor to store feature information in the table.
1320 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1321 that now describe their own features.
1322 (aarch64_pstatefield_supported_p): Likewise.
1323
f9630fa6
L		 13242020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1325
1326 * i386-dis.c (prefix_table): Fix a typo in comments.
1327
73239888
JB		 13282020-06-09 Jan Beulich <jbeulich@suse.com>
1329
1330 * i386-dis.c (rex_ignored): Delete.
1331 (ckprefix): Drop rex_ignored initialization.
1332 (get_valid_dis386): Drop setting of rex_ignored.
1333 (print_insn): Drop checking of rex_ignored. Don't record data
1334 size prefix as used with VEX-and-alike encodings.
1335
18897deb
JB		 13362020-06-09 Jan Beulich <jbeulich@suse.com>
1337
1338 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1339 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1340 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1341 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1342 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1343 VEX_0F12, and VEX_0F16.
1344 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1345 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1346 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1347 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1348 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1349 MOD_VEX_0F16_PREFIX_2 entries.
1350
97e6786a
JB		 13512020-06-09 Jan Beulich <jbeulich@suse.com>
1352
1353 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1354 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1355 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1356 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1357 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1358 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1359 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1360 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1361 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1362 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1363 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1364 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1365 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1366 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1367 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1368 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1369 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1370 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1371 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1372 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1373 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1374 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1375 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1376 EVEX_W_0FC6_P_2): Delete.
1377 (print_insn): Add EVEX.W vs embedded prefix consistency check
1378 to prefix validation.
1379 * i386-dis-evex.h (evex_table): Don't further descend for
1380 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1381 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1382 and 0F2B.
1383 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1384 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1385 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1386 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1387 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1388 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1389 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1390 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1391 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1392 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1393 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1394 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1395 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1396 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1397 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1398 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1399 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1400 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1401 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1402 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1403 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1404 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1405 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1406 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1407 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1408 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1409 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1410
bf926894
JB		 14112020-06-09 Jan Beulich <jbeulich@suse.com>
1412
1413 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1414 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1415 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1416 vmovmskpX.
1417 (print_insn): Drop pointless check against bad_opcode. Split
1418 prefix validation into legacy and VEX-and-alike parts.
1419 (putop): Re-work 'X' macro handling.
1420
a5aaedb9
JB		 14212020-06-09 Jan Beulich <jbeulich@suse.com>
1422
1423 * i386-dis.c (MOD_0F51): Rename to ...
1424 (MOD_0F50): ... this.
1425
26417f19
AC		 14262020-06-08 Alex Coplan <alex.coplan@arm.com>
1427
1428 * arm-dis.c (arm_opcodes): Add dfb.
1429 (thumb32_opcodes): Add dfb.
1430
8a6fb3f9
JB		 14312020-06-08 Jan Beulich <jbeulich@suse.com>
1432
1433 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1434
1424c35d
AM		 14352020-06-06 Alan Modra <amodra@gmail.com>
1436
1437 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1438
d3d1cc7b
AM		 14392020-06-05 Alan Modra <amodra@gmail.com>
1440
1441 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1442 size is large enough.
1443
d8740be1
JM		 14442020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1445
1446 * disassemble.c (disassemble_init_for_target): Set endian_code for
1447 bpf targets.
1448 * bpf-desc.c: Regenerate.
1449 * bpf-opc.c: Likewise.
1450 * bpf-dis.c: Likewise.
1451
e9bffec9
JM		 14522020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1453
1454 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1455 (cgen_put_insn_value): Likewise.
1456 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1457 * cgen-dis.in (print_insn): Likewise.
1458 * cgen-ibld.in (insert_1): Likewise.
1459 (insert_1): Likewise.
1460 (insert_insn_normal): Likewise.
1461 (extract_1): Likewise.
1462 * bpf-dis.c: Regenerate.
1463 * bpf-ibld.c: Likewise.
1464 * bpf-ibld.c: Likewise.
1465 * cgen-dis.in: Likewise.
1466 * cgen-ibld.in: Likewise.
1467 * cgen-opc.c: Likewise.
1468 * epiphany-dis.c: Likewise.
1469 * epiphany-ibld.c: Likewise.
1470 * fr30-dis.c: Likewise.
1471 * fr30-ibld.c: Likewise.
1472 * frv-dis.c: Likewise.
1473 * frv-ibld.c: Likewise.
1474 * ip2k-dis.c: Likewise.
1475 * ip2k-ibld.c: Likewise.
1476 * iq2000-dis.c: Likewise.
1477 * iq2000-ibld.c: Likewise.
1478 * lm32-dis.c: Likewise.
1479 * lm32-ibld.c: Likewise.
1480 * m32c-dis.c: Likewise.
1481 * m32c-ibld.c: Likewise.
1482 * m32r-dis.c: Likewise.
1483 * m32r-ibld.c: Likewise.
1484 * mep-dis.c: Likewise.
1485 * mep-ibld.c: Likewise.
1486 * mt-dis.c: Likewise.
1487 * mt-ibld.c: Likewise.
1488 * or1k-dis.c: Likewise.
1489 * or1k-ibld.c: Likewise.
1490 * xc16x-dis.c: Likewise.
1491 * xc16x-ibld.c: Likewise.
1492 * xstormy16-dis.c: Likewise.
1493 * xstormy16-ibld.c: Likewise.
1494
b3db6d07
JM		 14952020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1496
1497 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1498 (print_insn_): Handle instruction endian.
1499 * bpf-dis.c: Regenerate.
1500 * bpf-desc.c: Regenerate.
1501 * epiphany-dis.c: Likewise.
1502 * epiphany-desc.c: Likewise.
1503 * fr30-dis.c: Likewise.
1504 * fr30-desc.c: Likewise.
1505 * frv-dis.c: Likewise.
1506 * frv-desc.c: Likewise.
1507 * ip2k-dis.c: Likewise.
1508 * ip2k-desc.c: Likewise.
1509 * iq2000-dis.c: Likewise.
1510 * iq2000-desc.c: Likewise.
1511 * lm32-dis.c: Likewise.
1512 * lm32-desc.c: Likewise.
1513 * m32c-dis.c: Likewise.
1514 * m32c-desc.c: Likewise.
1515 * m32r-dis.c: Likewise.
1516 * m32r-desc.c: Likewise.
1517 * mep-dis.c: Likewise.
1518 * mep-desc.c: Likewise.
1519 * mt-dis.c: Likewise.
1520 * mt-desc.c: Likewise.
1521 * or1k-dis.c: Likewise.
1522 * or1k-desc.c: Likewise.
1523 * xc16x-dis.c: Likewise.
1524 * xc16x-desc.c: Likewise.
1525 * xstormy16-dis.c: Likewise.
1526 * xstormy16-desc.c: Likewise.
1527
4ee4189f
NC		 15282020-06-03 Nick Clifton <nickc@redhat.com>
1529
1530 * po/sr.po: Updated Serbian translation.
1531
44730156
NC		 15322020-06-03 Nelson Chu <nelson.chu@sifive.com>
1533
1534 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1535 (riscv_get_priv_spec_class): Likewise.
1536
3c3d0376
AM		 15372020-06-01 Alan Modra <amodra@gmail.com>
1538
1539 * bpf-desc.c: Regenerate.
1540
78c1c354
JM		 15412020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1542 David Faust <david.faust@oracle.com>
1543
1544 * bpf-desc.c: Regenerate.
1545 * bpf-opc.h: Likewise.
1546 * bpf-opc.c: Likewise.
1547 * bpf-dis.c: Likewise.
1548
efcf5fb5
AM		 15492020-05-28 Alan Modra <amodra@gmail.com>
1550
1551 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1552 values.
1553
ab382d64
AM		 15542020-05-28 Alan Modra <amodra@gmail.com>
1555
1556 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1557 immediates.
1558 (print_insn_ns32k): Revert last change.
1559
151f5de4
NC		 15602020-05-28 Nick Clifton <nickc@redhat.com>
1561
1562 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1563 static.
1564
25e1eca8
SL		 15652020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1566
1567 Fix extraction of signed constants in nios2 disassembler (again).
1568
1569 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1570 extractions of signed fields.
1571
57b17940
SSF		 15722020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1573
1574 * s390-opc.txt: Relocate vector load/store instructions with
1575 additional alignment parameter and change architecture level
1576 constraint from z14 to z13.
1577
d96bf37b
AM		 15782020-05-21 Alan Modra <amodra@gmail.com>
1579
1580 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1581 * sparc-dis.c: Likewise.
1582 * tic4x-dis.c: Likewise.
1583 * xtensa-dis.c: Likewise.
1584 * bpf-desc.c: Regenerate.
1585 * epiphany-desc.c: Regenerate.
1586 * fr30-desc.c: Regenerate.
1587 * frv-desc.c: Regenerate.
1588 * ip2k-desc.c: Regenerate.
1589 * iq2000-desc.c: Regenerate.
1590 * lm32-desc.c: Regenerate.
1591 * m32c-desc.c: Regenerate.
1592 * m32r-desc.c: Regenerate.
1593 * mep-asm.c: Regenerate.
1594 * mep-desc.c: Regenerate.
1595 * mt-desc.c: Regenerate.
1596 * or1k-desc.c: Regenerate.
1597 * xc16x-desc.c: Regenerate.
1598 * xstormy16-desc.c: Regenerate.
1599
8f595e9b
NC		 16002020-05-20 Nelson Chu <nelson.chu@sifive.com>
1601
1602 * riscv-opc.c (riscv_ext_version_table): The table used to store
1603 all information about the supported spec and the corresponding ISA
1604 versions. Currently, only Zicsr is supported to verify the
1605 correctness of Z sub extension settings. Others will be supported
1606 in the future patches.
1607 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1608 classes and the corresponding strings.
1609 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1610 spec class by giving a ISA spec string.
1611 * riscv-opc.c (struct priv_spec_t): New structure.
1612 (struct priv_spec_t priv_specs): List for all supported privilege spec
1613 classes and the corresponding strings.
1614 (riscv_get_priv_spec_class): New function. Get the corresponding
1615 privilege spec class by giving a spec string.
1616 (riscv_get_priv_spec_name): New function. Get the corresponding
1617 privilege spec string by giving a CSR version class.
1618 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1619 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1620 according to the chosen version. Build a hash table riscv_csr_hash to
1621 store the valid CSR for the chosen pirv verison. Dump the direct
1622 CSR address rather than it's name if it is invalid.
1623 (parse_riscv_dis_option_without_args): New function. Parse the options
1624 without arguments.
1625 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1626 parse the options without arguments first, and then handle the options
1627 with arguments. Add the new option -Mpriv-spec, which has argument.
1628 * riscv-dis.c (print_riscv_disassembler_options): Add description
1629 about the new OBJDUMP option.
1630
3d205eb4
PB		 16312020-05-19 Peter Bergner <bergner@linux.ibm.com>
1632
1633 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1634 WC values on POWER10 sync, dcbf and wait instructions.
1635 (insert_pl, extract_pl): New functions.
1636 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1637 (LS3): New , 3-bit L for sync.
1638 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1639 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1640 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1641 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1642 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1643 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1644 <wait>: Enable PL operand on POWER10.
1645 <dcbf>: Enable L3OPT operand on POWER10.
1646 <sync>: Enable SC2 operand on POWER10.
1647
a501eb44
SH		 16482020-05-19 Stafford Horne <shorne@gmail.com>
1649
1650 PR 25184
1651 * or1k-asm.c: Regenerate.
1652 * or1k-desc.c: Regenerate.
1653 * or1k-desc.h: Regenerate.
1654 * or1k-dis.c: Regenerate.
1655 * or1k-ibld.c: Regenerate.
1656 * or1k-opc.c: Regenerate.
1657 * or1k-opc.h: Regenerate.
1658 * or1k-opinst.c: Regenerate.
1659
3b646889
AM		 16602020-05-11 Alan Modra <amodra@gmail.com>
1661
1662 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1663 xsmaxcqp, xsmincqp.
1664
9cc4ce88
AM		 16652020-05-11 Alan Modra <amodra@gmail.com>
1666
1667 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1668 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1669
5d57bc3f
AM		 16702020-05-11 Alan Modra <amodra@gmail.com>
1671
1672 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1673
66ef5847
AM		 16742020-05-11 Alan Modra <amodra@gmail.com>
1675
1676 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1677 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1678
4f3e9537
PB		 16792020-05-11 Peter Bergner <bergner@linux.ibm.com>
1680
1681 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1682 mnemonics.
1683
ec40e91c
AM		 16842020-05-11 Alan Modra <amodra@gmail.com>
1685
1686 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1687 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1688 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1689 (prefix_opcodes): Add xxeval.
1690
d7e97a76
AM		 16912020-05-11 Alan Modra <amodra@gmail.com>
1692
1693 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1694 xxgenpcvwm, xxgenpcvdm.
1695
fdefed7c
AM		 16962020-05-11 Alan Modra <amodra@gmail.com>
1697
1698 * ppc-opc.c (MP, VXVAM_MASK): Define.
1699 (VXVAPS_MASK): Use VXVA_MASK.
1700 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1701 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1702 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1703 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1704
aa3c112f
AM		 17052020-05-11 Alan Modra <amodra@gmail.com>
1706 Peter Bergner <bergner@linux.ibm.com>
1707
1708 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1709 New functions.
1710 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1711 YMSK2, XA6a, XA6ap, XB6a entries.
1712 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1713 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1714 (PPCVSX4): Define.
1715 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1716 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1717 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1718 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1719 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1720 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1721 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1722 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1723 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1724 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1725 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1726 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1727 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1728 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1729
6edbfd3b
AM		 17302020-05-11 Alan Modra <amodra@gmail.com>
1731
1732 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1733 (insert_xts, extract_xts): New functions.
1734 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1735 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1736 (VXRC_MASK, VXSH_MASK): Define.
1737 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1738 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1739 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1740 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1741 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1742 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1743 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1744
c7d7aea2
AM		 17452020-05-11 Alan Modra <amodra@gmail.com>
1746
1747 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1748 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1749 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1750 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1751 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1752
94ba9882
AM		 17532020-05-11 Alan Modra <amodra@gmail.com>
1754
1755 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1756 (XTP, DQXP, DQXP_MASK): Define.
1757 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1758 (prefix_opcodes): Add plxvp and pstxvp.
1759
f4791f1a
AM		 17602020-05-11 Alan Modra <amodra@gmail.com>
1761
1762 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1763 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1764 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1765
3ff0a5ba
PB		 17662020-05-11 Peter Bergner <bergner@linux.ibm.com>
1767
1768 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1769
afef4fe9
PB		 17702020-05-11 Peter Bergner <bergner@linux.ibm.com>
1771
1772 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1773 (L1OPT): Define.
1774 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1775
1224c05d
PB		 17762020-05-11 Peter Bergner <bergner@linux.ibm.com>
1777
1778 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1779
6bbb0c05
AM		 17802020-05-11 Alan Modra <amodra@gmail.com>
1781
1782 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1783
7c1f4227
AM		 17842020-05-11 Alan Modra <amodra@gmail.com>
1785
1786 * ppc-dis.c (ppc_opts): Add "power10" entry.
1787 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1788 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1789
73199c2b
NC		 17902020-05-11 Nick Clifton <nickc@redhat.com>
1791
1792 * po/fr.po: Updated French translation.
1793
09c1e68a
AC		 17942020-04-30 Alex Coplan <alex.coplan@arm.com>
1795
1796 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1797 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1798 (operand_general_constraint_met_p): validate
1799 AARCH64_OPND_UNDEFINED.
1800 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1801 for FLD_imm16_2.
1802 * aarch64-asm-2.c: Regenerated.
1803 * aarch64-dis-2.c: Regenerated.
1804 * aarch64-opc-2.c: Regenerated.
1805
9654d51a
NC		 18062020-04-29 Nick Clifton <nickc@redhat.com>
1807
1808 PR 22699
1809 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1810 and SETRC insns.
1811
c2e71e57
NC		 18122020-04-29 Nick Clifton <nickc@redhat.com>
1813
1814 * po/sv.po: Updated Swedish translation.
1815
5c936ef5
NC		 18162020-04-29 Nick Clifton <nickc@redhat.com>
1817
1818 PR 22699
1819 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1820 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1821 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1822 IMM0_8U case.
1823
bb2a1453
AS		 18242020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1825
1826 PR 25848
1827 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1828 cmpi only on m68020up and cpu32.
1829
c2e5c986
SD		 18302020-04-20 Sudakshina Das <sudi.das@arm.com>
1831
1832 * aarch64-asm.c (aarch64_ins_none): New.
1833 * aarch64-asm.h (ins_none): New declaration.
1834 * aarch64-dis.c (aarch64_ext_none): New.
1835 * aarch64-dis.h (ext_none): New declaration.
1836 * aarch64-opc.c (aarch64_print_operand): Update case for
1837 AARCH64_OPND_BARRIER_PSB.
1838 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1839 (AARCH64_OPERANDS): Update inserter/extracter for
1840 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1841 * aarch64-asm-2.c: Regenerated.
1842 * aarch64-dis-2.c: Regenerated.
1843 * aarch64-opc-2.c: Regenerated.
1844
8a6e1d1d
SD		 18452020-04-20 Sudakshina Das <sudi.das@arm.com>
1846
1847 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1848 (aarch64_feature_ras, RAS): Likewise.
1849 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1850 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1851 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1852 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1853 * aarch64-asm-2.c: Regenerated.
1854 * aarch64-dis-2.c: Regenerated.
1855 * aarch64-opc-2.c: Regenerated.
1856
e409955d
FS		 18572020-04-17 Fredrik Strupe <fredrik@strupe.net>
1858
1859 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1860 (print_insn_neon): Support disassembly of conditional
1861 instructions.
1862
c54a9b56
DF		 18632020-02-16 David Faust <david.faust@oracle.com>
1864
1865 * bpf-desc.c: Regenerate.
1866 * bpf-desc.h: Likewise.
1867 * bpf-opc.c: Regenerate.
1868 * bpf-opc.h: Likewise.
1869
bb651e8b
CL		 18702020-04-07 Lili Cui <lili.cui@intel.com>
1871
1872 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1873 (prefix_table): New instructions (see prefixes above).
1874 (rm_table): Likewise
1875 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1876 CPU_ANY_TSXLDTRK_FLAGS.
1877 (cpu_flags): Add CpuTSXLDTRK.
1878 * i386-opc.h (enum): Add CpuTSXLDTRK.
1879 (i386_cpu_flags): Add cputsxldtrk.
1880 * i386-opc.tbl: Add XSUSPLDTRK insns.
1881 * i386-init.h: Regenerate.
1882 * i386-tbl.h: Likewise.
1883
4b27d27c
L		 18842020-04-02 Lili Cui <lili.cui@intel.com>
1885
1886 * i386-dis.c (prefix_table): New instructions serialize.
1887 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1888 CPU_ANY_SERIALIZE_FLAGS.
1889 (cpu_flags): Add CpuSERIALIZE.
1890 * i386-opc.h (enum): Add CpuSERIALIZE.
1891 (i386_cpu_flags): Add cpuserialize.
1892 * i386-opc.tbl: Add SERIALIZE insns.
1893 * i386-init.h: Regenerate.
1894 * i386-tbl.h: Likewise.
1895
832a5807
AM		 18962020-03-26 Alan Modra <amodra@gmail.com>
1897
1898 * disassemble.h (opcodes_assert): Declare.
1899 (OPCODES_ASSERT): Define.
1900 * disassemble.c: Don't include assert.h. Include opintl.h.
1901 (opcodes_assert): New function.
1902 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1903 (bfd_h8_disassemble): Reduce size of data array. Correctly
1904 calculate maxlen. Omit insn decoding when insn length exceeds
1905 maxlen. Exit from nibble loop when looking for E, before
1906 accessing next data byte. Move processing of E outside loop.
1907 Replace tests of maxlen in loop with assertions.
1908
4c4addbe
AM		 19092020-03-26 Alan Modra <amodra@gmail.com>
1910
1911 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1912
a18cd0ca
AM		 19132020-03-25 Alan Modra <amodra@gmail.com>
1914
1915 * z80-dis.c (suffix): Init mybuf.
1916
57cb32b3
AM		 19172020-03-22 Alan Modra <amodra@gmail.com>
1918
1919 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1920 successflly read from section.
1921
beea5cc1
AM		 19222020-03-22 Alan Modra <amodra@gmail.com>
1923
1924 * arc-dis.c (find_format): Use ISO C string concatenation rather
1925 than line continuation within a string. Don't access needs_limm
1926 before testing opcode != NULL.
1927
03704c77
AM		 19282020-03-22 Alan Modra <amodra@gmail.com>
1929
1930 * ns32k-dis.c (print_insn_arg): Update comment.
1931 (print_insn_ns32k): Reduce size of index_offset array, and
1932 initialize, passing -1 to print_insn_arg for args that are not
1933 an index. Don't exit arg loop early. Abort on bad arg number.
1934
d1023b5d
AM		 19352020-03-22 Alan Modra <amodra@gmail.com>
1936
1937 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1938 * s12z-opc.c: Formatting.
1939 (operands_f): Return an int.
1940 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1941 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1942 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1943 (exg_sex_discrim): Likewise.
1944 (create_immediate_operand, create_bitfield_operand),
1945 (create_register_operand_with_size, create_register_all_operand),
1946 (create_register_all16_operand, create_simple_memory_operand),
1947 (create_memory_operand, create_memory_auto_operand): Don't
1948 segfault on malloc failure.
1949 (z_ext24_decode): Return an int status, negative on fail, zero
1950 on success.
1951 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1952 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1953 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1954 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1955 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1956 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1957 (loop_primitive_decode, shift_decode, psh_pul_decode),
1958 (bit_field_decode): Similarly.
1959 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1960 to return value, update callers.
1961 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1962 Don't segfault on NULL operand.
1963 (decode_operation): Return OP_INVALID on first fail.
1964 (decode_s12z): Check all reads, returning -1 on fail.
1965
340f3ac8
AM		 19662020-03-20 Alan Modra <amodra@gmail.com>
1967
1968 * metag-dis.c (print_insn_metag): Don't ignore status from
1969 read_memory_func.
1970
fe90ae8a
AM		 19712020-03-20 Alan Modra <amodra@gmail.com>
1972
1973 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1974 Initialize parts of buffer not written when handling a possible
1975 2-byte insn at end of section. Don't attempt decoding of such
1976 an insn by the 4-byte machinery.
1977
833d919c
AM		 19782020-03-20 Alan Modra <amodra@gmail.com>
1979
1980 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1981 partially filled buffer. Prevent lookup of 4-byte insns when
1982 only VLE 2-byte insns are possible due to section size. Print
1983 ".word" rather than ".long" for 2-byte leftovers.
1984
327ef784
NC		 19852020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1986
1987 PR 25641
1988 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1989
1673df32
JB		 19902020-03-13 Jan Beulich <jbeulich@suse.com>
1991
1992 * i386-dis.c (X86_64_0D): Rename to ...
1993 (X86_64_0E): ... this.
1994
384f3689
L		 19952020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1996
1997 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1998 * Makefile.in: Regenerated.
1999
865e2027
JB		 20002020-03-09 Jan Beulich <jbeulich@suse.com>
2001
2002 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2003 3-operand pseudos.
2004 * i386-tbl.h: Re-generate.
2005
2f13234b
JB		 20062020-03-09 Jan Beulich <jbeulich@suse.com>
2007
2008 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2009 vprot*, vpsha*, and vpshl*.
2010 * i386-tbl.h: Re-generate.
2011
3fabc179
JB		 20122020-03-09 Jan Beulich <jbeulich@suse.com>
2013
2014 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2015 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2016 * i386-tbl.h: Re-generate.
2017
3677e4c1
JB		 20182020-03-09 Jan Beulich <jbeulich@suse.com>
2019
2020 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2021 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2022 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2023 * i386-tbl.h: Re-generate.
2024
4c4898e8
JB		 20252020-03-09 Jan Beulich <jbeulich@suse.com>
2026
2027 * i386-gen.c (struct template_arg, struct template_instance,
2028 struct template_param, struct template, templates,
2029 parse_template, expand_templates): New.
2030 (process_i386_opcodes): Various local variables moved to
2031 expand_templates. Call parse_template and expand_templates.
2032 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2033 * i386-tbl.h: Re-generate.
2034
bc49bfd8
JB		 20352020-03-06 Jan Beulich <jbeulich@suse.com>
2036
2037 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2038 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2039 register and memory source templates. Replace VexW= by VexW*
2040 where applicable.
2041 * i386-tbl.h: Re-generate.
2042
4873e243
JB		 20432020-03-06 Jan Beulich <jbeulich@suse.com>
2044
2045 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2046 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2047 * i386-tbl.h: Re-generate.
2048
672a349b
JB		 20492020-03-06 Jan Beulich <jbeulich@suse.com>
2050
2051 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2052 * i386-tbl.h: Re-generate.
2053
4ed21b58
JB		 20542020-03-06 Jan Beulich <jbeulich@suse.com>
2055
2056 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2057 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2058 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2059 VexW0 on SSE2AVX variants.
2060 (vmovq): Drop NoRex64 from XMM/XMM variants.
2061 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2062 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2063 applicable use VexW0.
2064 * i386-tbl.h: Re-generate.
2065
643bb870
JB		 20662020-03-06 Jan Beulich <jbeulich@suse.com>
2067
2068 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2069 * i386-opc.h (Rex64): Delete.
2070 (struct i386_opcode_modifier): Remove rex64 field.
2071 * i386-opc.tbl (crc32): Drop Rex64.
2072 Replace Rex64 with Size64 everywhere else.
2073 * i386-tbl.h: Re-generate.
2074
a23b33b3
JB		 20752020-03-06 Jan Beulich <jbeulich@suse.com>
2076
2077 * i386-dis.c (OP_E_memory): Exclude recording of used address
2078 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2079 addressed memory operands for MPX insns.
2080
a0497384
JB		 20812020-03-06 Jan Beulich <jbeulich@suse.com>
2082
2083 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2084 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2085 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2086 (ptwrite): Split into non-64-bit and 64-bit forms.
2087 * i386-tbl.h: Re-generate.
2088
b630c145
JB		 20892020-03-06 Jan Beulich <jbeulich@suse.com>
2090
2091 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2092 template.
2093 * i386-tbl.h: Re-generate.
2094
a847e322
JB		 20952020-03-04 Jan Beulich <jbeulich@suse.com>
2096
2097 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2098 (prefix_table): Move vmmcall here. Add vmgexit.
2099 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2100 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2101 (cpu_flags): Add CpuSEV_ES entry.
2102 * i386-opc.h (CpuSEV_ES): New.
2103 (union i386_cpu_flags): Add cpusev_es field.
2104 * i386-opc.tbl (vmgexit): New.
2105 * i386-init.h, i386-tbl.h: Re-generate.
2106
3cd7f3e3
L		 21072020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2108
2109 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2110 with MnemonicSize.
2111 * i386-opc.h (IGNORESIZE): New.
2112 (DEFAULTSIZE): Likewise.
2113 (IgnoreSize): Removed.
2114 (DefaultSize): Likewise.
2115 (MnemonicSize): New.
2116 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2117 mnemonicsize.
2118 * i386-opc.tbl (IgnoreSize): New.
2119 (DefaultSize): Likewise.
2120 * i386-tbl.h: Regenerated.
2121
b8ba1385
SB		 21222020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2123
2124 PR 25627
2125 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2126 instructions.
2127
10d97a0f
L		 21282020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2129
2130 PR gas/25622
2131 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2132 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2133 * i386-tbl.h: Regenerated.
2134
dc1e8a47
AM		 21352020-02-26 Alan Modra <amodra@gmail.com>
2136
2137 * aarch64-asm.c: Indent labels correctly.
2138 * aarch64-dis.c: Likewise.
2139 * aarch64-gen.c: Likewise.
2140 * aarch64-opc.c: Likewise.
2141 * alpha-dis.c: Likewise.
2142 * i386-dis.c: Likewise.
2143 * nds32-asm.c: Likewise.
2144 * nfp-dis.c: Likewise.
2145 * visium-dis.c: Likewise.
2146
265b4673
CZ		 21472020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2148
2149 * arc-regs.h (int_vector_base): Make it available for all ARC
2150 CPUs.
2151
bd0cf5a6
NC		 21522020-02-20 Nelson Chu <nelson.chu@sifive.com>
2153
2154 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2155 changed.
2156
fa164239
JW		 21572020-02-19 Nelson Chu <nelson.chu@sifive.com>
2158
2159 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2160 c.mv/c.li if rs1 is zero.
2161
272a84b1
L		 21622020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2163
2164 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2165 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2166 CPU_POPCNT_FLAGS.
2167 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2168 * i386-opc.h (CpuABM): Removed.
2169 (CpuPOPCNT): New.
2170 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2171 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2172 popcnt. Remove CpuABM from lzcnt.
2173 * i386-init.h: Regenerated.
2174 * i386-tbl.h: Likewise.
2175
1f730c46
JB		 21762020-02-17 Jan Beulich <jbeulich@suse.com>
2177
2178 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2179 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2180 VexW1 instead of open-coding them.
2181 * i386-tbl.h: Re-generate.
2182
c8f8eebc
JB		 21832020-02-17 Jan Beulich <jbeulich@suse.com>
2184
2185 * i386-opc.tbl (AddrPrefixOpReg): Define.
2186 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2187 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2188 templates. Drop NoRex64.
2189 * i386-tbl.h: Re-generate.
2190
b9915cbc
JB		 21912020-02-17 Jan Beulich <jbeulich@suse.com>
2192
2193 PR gas/6518
2194 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2195 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2196 into Intel syntax instance (with Unpsecified) and AT&T one
2197 (without).
2198 (vcvtneps2bf16): Likewise, along with folding the two so far
2199 separate ones.
2200 * i386-tbl.h: Re-generate.
2201
ce504911
L		 22022020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2203
2204 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2205 CPU_ANY_SSE4A_FLAGS.
2206
dabec65d
AM		 22072020-02-17 Alan Modra <amodra@gmail.com>
2208
2209 * i386-gen.c (cpu_flag_init): Correct last change.
2210
af5c13b0
L		 22112020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2212
2213 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2214 CPU_ANY_SSE4_FLAGS.
2215
6867aac0
L		 22162020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2217
2218 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2219 (movzx): Likewise.
2220
65fca059
JB		 22212020-02-14 Jan Beulich <jbeulich@suse.com>
2222
2223 PR gas/25438
2224 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2225 destination for Cpu64-only variant.
2226 (movzx): Fold patterns.
2227 * i386-tbl.h: Re-generate.
2228
7deea9aa
JB		 22292020-02-13 Jan Beulich <jbeulich@suse.com>
2230
2231 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2232 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2233 CPU_ANY_SSE4_FLAGS entry.
2234 * i386-init.h: Re-generate.
2235
6c0946d0
JB		 22362020-02-12 Jan Beulich <jbeulich@suse.com>
2237
2238 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2239 with Unspecified, making the present one AT&T syntax only.
2240 * i386-tbl.h: Re-generate.
2241
ddb56fe6
JB		 22422020-02-12 Jan Beulich <jbeulich@suse.com>
2243
2244 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2245 * i386-tbl.h: Re-generate.
2246
5990e377
JB		 22472020-02-12 Jan Beulich <jbeulich@suse.com>
2248
2249 PR gas/24546
2250 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2251 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2252 Amd64 and Intel64 templates.
2253 (call, jmp): Likewise for far indirect variants. Dro
2254 Unspecified.
2255 * i386-tbl.h: Re-generate.
2256
50128d0c
JB		 22572020-02-11 Jan Beulich <jbeulich@suse.com>
2258
2259 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2260 * i386-opc.h (ShortForm): Delete.
2261 (struct i386_opcode_modifier): Remove shortform field.
2262 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2263 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2264 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2265 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2266 Drop ShortForm.
2267 * i386-tbl.h: Re-generate.
2268
1e05b5c4
JB		 22692020-02-11 Jan Beulich <jbeulich@suse.com>
2270
2271 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2272 fucompi): Drop ShortForm from operand-less templates.
2273 * i386-tbl.h: Re-generate.
2274
2f5dd314
AM		 22752020-02-11 Alan Modra <amodra@gmail.com>
2276
2277 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2278 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2279 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2280 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2281 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2282
5aae9ae9
MM		 22832020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2284
2285 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2286 (cde_opcodes): Add VCX* instructions.
2287
4934a27c
MM		 22882020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2289 Matthew Malcomson <matthew.malcomson@arm.com>
2290
2291 * arm-dis.c (struct cdeopcode32): New.
2292 (CDE_OPCODE): New macro.
2293 (cde_opcodes): New disassembly table.
2294 (regnames): New option to table.
2295 (cde_coprocs): New global variable.
2296 (print_insn_cde): New
2297 (print_insn_thumb32): Use print_insn_cde.
2298 (parse_arm_disassembler_options): Parse coprocN args.
2299
4b5aaf5f
L		 23002020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2301
2302 PR gas/25516
2303 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2304 with ISA64.
2305 * i386-opc.h (AMD64): Removed.
2306 (Intel64): Likewose.
2307 (AMD64): New.
2308 (INTEL64): Likewise.
2309 (INTEL64ONLY): Likewise.
2310 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2311 * i386-opc.tbl (Amd64): New.
2312 (Intel64): Likewise.
2313 (Intel64Only): Likewise.
2314 Replace AMD64 with Amd64. Update sysenter/sysenter with
2315 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2316 * i386-tbl.h: Regenerated.
2317
9fc0b501
SB		 23182020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2319
2320 PR 25469
2321 * z80-dis.c: Add support for GBZ80 opcodes.
2322
c5d7be0c
AM		 23232020-02-04 Alan Modra <amodra@gmail.com>
2324
2325 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2326
44e4546f
AM		 23272020-02-03 Alan Modra <amodra@gmail.com>
2328
2329 * m32c-ibld.c: Regenerate.
2330
b2b1453a
AM		 23312020-02-01 Alan Modra <amodra@gmail.com>
2332
2333 * frv-ibld.c: Regenerate.
2334
4102be5c
JB		 23352020-01-31 Jan Beulich <jbeulich@suse.com>
2336
2337 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2338 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2339 (OP_E_memory): Replace xmm_mdq_mode case label by
2340 vex_scalar_w_dq_mode one.
2341 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2342
825bd36c
JB		 23432020-01-31 Jan Beulich <jbeulich@suse.com>
2344
2345 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2346 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2347 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2348 (intel_operand_size): Drop vex_w_dq_mode case label.
2349
c3036ed0
RS		 23502020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2351
2352 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2353 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2354
0c115f84
AM		 23552020-01-30 Alan Modra <amodra@gmail.com>
2356
2357 * m32c-ibld.c: Regenerate.
2358
bd434cc4
JM		 23592020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2360
2361 * bpf-opc.c: Regenerate.
2362
aeab2b26
JB		 23632020-01-30 Jan Beulich <jbeulich@suse.com>
2364
2365 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2366 (dis386): Use them to replace C2/C3 table entries.
2367 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2368 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2369 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2370 * i386-tbl.h: Re-generate.
2371
62b3f548
JB		 23722020-01-30 Jan Beulich <jbeulich@suse.com>
2373
2374 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2375 forms.
2376 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2377 DefaultSize.
2378 * i386-tbl.h: Re-generate.
2379
1bd8ae10
AM		 23802020-01-30 Alan Modra <amodra@gmail.com>
2381
2382 * tic4x-dis.c (tic4x_dp): Make unsigned.
2383
bc31405e
L		 23842020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2385 Jan Beulich <jbeulich@suse.com>
2386
2387 PR binutils/25445
2388 * i386-dis.c (MOVSXD_Fixup): New function.
2389 (movsxd_mode): New enum.
2390 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2391 (intel_operand_size): Handle movsxd_mode.
2392 (OP_E_register): Likewise.
2393 (OP_G): Likewise.
2394 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2395 register on movsxd. Add movsxd with 16-bit destination register
2396 for AMD64 and Intel64 ISAs.
2397 * i386-tbl.h: Regenerated.
2398
7568c93b
TC		 23992020-01-27 Tamar Christina <tamar.christina@arm.com>
2400
2401 PR 25403
2402 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2403 * aarch64-asm-2.c: Regenerate
2404 * aarch64-dis-2.c: Likewise.
2405 * aarch64-opc-2.c: Likewise.
2406
c006a730
JB		 24072020-01-21 Jan Beulich <jbeulich@suse.com>
2408
2409 * i386-opc.tbl (sysret): Drop DefaultSize.
2410 * i386-tbl.h: Re-generate.
2411
c906a69a
JB		 24122020-01-21 Jan Beulich <jbeulich@suse.com>
2413
2414 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2415 Dword.
2416 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2417 * i386-tbl.h: Re-generate.
2418
26916852
NC		 24192020-01-20 Nick Clifton <nickc@redhat.com>
2420
2421 * po/de.po: Updated German translation.
2422 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2423 * po/uk.po: Updated Ukranian translation.
2424
4d6cbb64
AM		 24252020-01-20 Alan Modra <amodra@gmail.com>
2426
2427 * hppa-dis.c (fput_const): Remove useless cast.
2428
2bddb71a
AM		 24292020-01-20 Alan Modra <amodra@gmail.com>
2430
2431 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2432
1b1bb2c6
NC		 24332020-01-18 Nick Clifton <nickc@redhat.com>
2434
2435 * configure: Regenerate.
2436 * po/opcodes.pot: Regenerate.
2437
ae774686
NC		 24382020-01-18 Nick Clifton <nickc@redhat.com>
2439
2440 Binutils 2.34 branch created.
2441
07f1f3aa
CB		 24422020-01-17 Christian Biesinger <cbiesinger@google.com>
2443
2444 * opintl.h: Fix spelling error (seperate).
2445
42e04b36
L		 24462020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2447
2448 * i386-opc.tbl: Add {vex} pseudo prefix.
2449 * i386-tbl.h: Regenerated.
2450
2da2eaf4
AV		 24512020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2452
2453 PR 25376
2454 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2455 (neon_opcodes): Likewise.
2456 (select_arm_features): Make sure we enable MVE bits when selecting
2457 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2458 any architecture.
2459
d0849eed
JB		 24602020-01-16 Jan Beulich <jbeulich@suse.com>
2461
2462 * i386-opc.tbl: Drop stale comment from XOP section.
2463
9cf70a44
JB		 24642020-01-16 Jan Beulich <jbeulich@suse.com>
2465
2466 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2467 (extractps): Add VexWIG to SSE2AVX forms.
2468 * i386-tbl.h: Re-generate.
2469
4814632e
JB		 24702020-01-16 Jan Beulich <jbeulich@suse.com>
2471
2472 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2473 Size64 from and use VexW1 on SSE2AVX forms.
2474 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2475 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2476 * i386-tbl.h: Re-generate.
2477
aad09917
AM		 24782020-01-15 Alan Modra <amodra@gmail.com>
2479
2480 * tic4x-dis.c (tic4x_version): Make unsigned long.
2481 (optab, optab_special, registernames): New file scope vars.
2482 (tic4x_print_register): Set up registernames rather than
2483 malloc'd registertable.
2484 (tic4x_disassemble): Delete optable and optable_special. Use
2485 optab and optab_special instead. Throw away old optab,
2486 optab_special and registernames when info->mach changes.
2487
7a6bf3be
SB		 24882020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2489
2490 PR 25377
2491 * z80-dis.c (suffix): Use .db instruction to generate double
2492 prefix.
2493
ca1eaac0
AM		 24942020-01-14 Alan Modra <amodra@gmail.com>
2495
2496 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2497 values to unsigned before shifting.
2498
1d67fe3b
TT		 24992020-01-13 Thomas Troeger <tstroege@gmx.de>
2500
2501 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2502 flow instructions.
2503 (print_insn_thumb16, print_insn_thumb32): Likewise.
2504 (print_insn): Initialize the insn info.
2505 * i386-dis.c (print_insn): Initialize the insn info fields, and
2506 detect jumps.
2507
5e4f7e05
CZ		 25082012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2509
2510 * arc-opc.c (C_NE): Make it required.
2511
b9fe6b8a
CZ		 25122012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2513
2514 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2515 reserved register name.
2516
90dee485
AM		 25172020-01-13 Alan Modra <amodra@gmail.com>
2518
2519 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2520 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2521
febda64f
AM		 25222020-01-13 Alan Modra <amodra@gmail.com>
2523
2524 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2525 result of wasm_read_leb128 in a uint64_t and check that bits
2526 are not lost when copying to other locals. Use uint32_t for
2527 most locals. Use PRId64 when printing int64_t.
2528
df08b588
AM		 25292020-01-13 Alan Modra <amodra@gmail.com>
2530
2531 * score-dis.c: Formatting.
2532 * score7-dis.c: Formatting.
2533
b2c759ce
AM		 25342020-01-13 Alan Modra <amodra@gmail.com>
2535
2536 * score-dis.c (print_insn_score48): Use unsigned variables for
2537 unsigned values. Don't left shift negative values.
2538 (print_insn_score32): Likewise.
2539 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2540
5496abe1
AM		 25412020-01-13 Alan Modra <amodra@gmail.com>
2542
2543 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2544
202e762b
AM		 25452020-01-13 Alan Modra <amodra@gmail.com>
2546
2547 * fr30-ibld.c: Regenerate.
2548
7ef412cf
AM		 25492020-01-13 Alan Modra <amodra@gmail.com>
2550
2551 * xgate-dis.c (print_insn): Don't left shift signed value.
2552 (ripBits): Formatting, use 1u.
2553
7f578b95
AM		 25542020-01-10 Alan Modra <amodra@gmail.com>
2555
2556 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2557 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2558
441af85b
AM		 25592020-01-10 Alan Modra <amodra@gmail.com>
2560
2561 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2562 and XRREG value earlier to avoid a shift with negative exponent.
2563 * m10200-dis.c (disassemble): Similarly.
2564
bce58db4
NC		 25652020-01-09 Nick Clifton <nickc@redhat.com>
2566
2567 PR 25224
2568 * z80-dis.c (ld_ii_ii): Use correct cast.
2569
40c75bc8
SB		 25702020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2571
2572 PR 25224
2573 * z80-dis.c (ld_ii_ii): Use character constant when checking
2574 opcode byte value.
2575
d835a58b
JB		 25762020-01-09 Jan Beulich <jbeulich@suse.com>
2577
2578 * i386-dis.c (SEP_Fixup): New.
2579 (SEP): Define.
2580 (dis386_twobyte): Use it for sysenter/sysexit.
2581 (enum x86_64_isa): Change amd64 enumerator to value 1.
2582 (OP_J): Compare isa64 against intel64 instead of amd64.
2583 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2584 forms.
2585 * i386-tbl.h: Re-generate.
2586
030a2e78
AM		 25872020-01-08 Alan Modra <amodra@gmail.com>
2588
2589 * z8k-dis.c: Include libiberty.h
2590 (instr_data_s): Make max_fetched unsigned.
2591 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2592 Don't exceed byte_info bounds.
2593 (output_instr): Make num_bytes unsigned.
2594 (unpack_instr): Likewise for nibl_count and loop.
2595 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2596 idx unsigned.
2597 * z8k-opc.h: Regenerate.
2598
bb82aefe
SV		 25992020-01-07 Shahab Vahedi <shahab@synopsys.com>
2600
2601 * arc-tbl.h (llock): Use 'LLOCK' as class.
2602 (llockd): Likewise.
2603 (scond): Use 'SCOND' as class.
2604 (scondd): Likewise.
2605 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2606 (scondd): Likewise.
2607
cc6aa1a6
AM		 26082020-01-06 Alan Modra <amodra@gmail.com>
2609
2610 * m32c-ibld.c: Regenerate.
2611
660e62b1
AM		 26122020-01-06 Alan Modra <amodra@gmail.com>
2613
2614 PR 25344
2615 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2616 Peek at next byte to prevent recursion on repeated prefix bytes.
2617 Ensure uninitialised "mybuf" is not accessed.
2618 (print_insn_z80): Don't zero n_fetch and n_used here,..
2619 (print_insn_z80_buf): ..do it here instead.
2620
c9ae58fe
AM		 26212020-01-04 Alan Modra <amodra@gmail.com>
2622
2623 * m32r-ibld.c: Regenerate.
2624
5f57d4ec
AM		 26252020-01-04 Alan Modra <amodra@gmail.com>
2626
2627 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2628
2c5c1196
AM		 26292020-01-04 Alan Modra <amodra@gmail.com>
2630
2631 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2632
2e98c6c5
AM		 26332020-01-04 Alan Modra <amodra@gmail.com>
2634
2635 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2636
567dfba2
JB		 26372020-01-03 Jan Beulich <jbeulich@suse.com>
2638
5437a02a
JB		 2639 * aarch64-tbl.h (aarch64_opcode_table): Use
2640 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2641
26422020-01-03 Jan Beulich <jbeulich@suse.com>
2643
2644 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2645 forms of SUDOT and USDOT.
2646
8c45011a
JB		 26472020-01-03 Jan Beulich <jbeulich@suse.com>
2648
5437a02a 2649 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2650 uzip{1,2}.
2651 * opcodes/aarch64-dis-2.c: Re-generate.
2652
f4950f76
JB		 26532020-01-03 Jan Beulich <jbeulich@suse.com>
2654
5437a02a 2655 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2656 FMMLA encoding.
2657 * opcodes/aarch64-dis-2.c: Re-generate.
2658
6655dba2
SB		 26592020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2660
2661 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2662
b14ce8bf
AM		 26632020-01-01 Alan Modra <amodra@gmail.com>
2664
2665 Update year range in copyright notice of all files.
2666
0b114740 2667For older changes see ChangeLog-2019
3499769a 2668\f
0b114740 2669Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2670
2671Copying and distribution of this file, with or without modification,
2672are permitted in any medium without royalty provided the copyright
2673notice and this notice are preserved.
2674
2675Local Variables:
2676mode: change-log
2677left-margin: 8
2678fill-column: 74
2679version-control: never
2680End:
GDB Binutils - Deliverables
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