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AArch64: Refactor err_type.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1d482394
TC		 12018-10-03 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
4 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
5
7e84b55d
TC		 62018-10-03 Tamar Christina <tamar.christina@arm.com>
7
8 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
9 * aarch64-dis.c (insn_sequence): New.
10
eae424ae
TC		 112018-10-03 Tamar Christina <tamar.christina@arm.com>
12
13 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
14 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
15 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
16 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
17 constraints.
18 (_SVE_INSNC): New.
19 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
20 constraints.
21 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
22 F_SCAN flags.
23 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
24 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
25 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
26 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
27 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
28 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
29 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
30
64a336ac
PD		 312018-10-02 Palmer Dabbelt <palmer@sifive.com>
32
33 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
34
6031ac35
SL		 352018-09-23 Sandra Loosemore <sandra@codesourcery.com>
36
37 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
38 are used when extracting signed fields and converting them to
39 potentially 64-bit types.
40
f24ff6e9
SM		 412018-09-21 Simon Marchi <simon.marchi@ericsson.com>
42
43 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
44 * Makefile.in: Re-generate.
45 * aclocal.m4: Re-generate.
46 * configure: Re-generate.
47 * configure.ac: Remove check for -Wno-missing-field-initializers.
48 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
49 (csky_v2_opcodes): Likewise.
50
53b6d6f5
MR		 512018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
52
53 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
54
fbaf61ad
NC		 552018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
56
57 * nds32-asm.c (operand_fields): Remove the unused fields.
58 (nds32_opcodes): Remove the unused instructions.
59 * nds32-dis.c (nds32_ex9_info): Removed.
60 (nds32_parse_opcode): Updated.
61 (print_insn_nds32): Likewise.
62 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
63 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
64 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
65 build_opcode_hash_table): New functions.
66 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
67 nds32_opcode_table): New.
68 (hw_ktabs): Declare it to a pointer rather than an array.
69 (build_hash_table): Removed.
70 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
71 SYN_ROPT and upadte HW_GPR and HW_INT.
72 * nds32-dis.c (keywords): Remove const.
73 (match_field): New function.
74 (nds32_parse_opcode): Updated.
75 * disassemble.c (disassemble_init_for_target):
76 Add disassemble_init_nds32.
77 * nds32-dis.c (eum map_type): New.
78 (nds32_private_data): Likewise.
79 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
80 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
81 (print_insn_nds32): Updated.
82 * nds32-asm.c (parse_aext_reg): Add new parameter.
83 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
84 are allowed to use.
85 All callers changed.
86 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
87 (operand_fields): Add new fields.
88 (nds32_opcodes): Add new instructions.
89 (keyword_aridxi_mx): New keyword.
90 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
91 and NASM_ATTR_ZOL.
92 (ALU2_1, ALU2_2, ALU2_3): New macros.
93 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
94
4e2b1898
JW		 952018-09-17 Kito Cheng <kito@andestech.com>
96
97 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
98
04e2a182
L		 992018-09-17 H.J. Lu <hongjiu.lu@intel.com>
100
101 PR gas/23670
102 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
103 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
104 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
105 (EVEX_LEN_0F7E_P_1): Likewise.
106 (EVEX_LEN_0F7E_P_2): Likewise.
107 (EVEX_LEN_0FD6_P_2): Likewise.
108 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
109 (EVEX_LEN_TABLE): Likewise.
110 (EVEX_LEN_0F6E_P_2): New enum.
111 (EVEX_LEN_0F7E_P_1): Likewise.
112 (EVEX_LEN_0F7E_P_2): Likewise.
113 (EVEX_LEN_0FD6_P_2): Likewise.
114 (evex_len_table): New.
115 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
116 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
117 * i386-tbl.h: Regenerated.
118
d5f787c2
L		 1192018-09-17 H.J. Lu <hongjiu.lu@intel.com>
120
121 PR gas/23665
122 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
123 VEX_LEN_0F7E_P_2 entries.
124 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
125 * i386-tbl.h: Regenerated.
126
ec6f095a
L		 1272018-09-17 H.J. Lu <hongjiu.lu@intel.com>
128
129 * i386-dis.c (VZERO_Fixup): Removed.
130 (VZERO): Likewise.
131 (VEX_LEN_0F10_P_1): Likewise.
132 (VEX_LEN_0F10_P_3): Likewise.
133 (VEX_LEN_0F11_P_1): Likewise.
134 (VEX_LEN_0F11_P_3): Likewise.
135 (VEX_LEN_0F2E_P_0): Likewise.
136 (VEX_LEN_0F2E_P_2): Likewise.
137 (VEX_LEN_0F2F_P_0): Likewise.
138 (VEX_LEN_0F2F_P_2): Likewise.
139 (VEX_LEN_0F51_P_1): Likewise.
140 (VEX_LEN_0F51_P_3): Likewise.
141 (VEX_LEN_0F52_P_1): Likewise.
142 (VEX_LEN_0F53_P_1): Likewise.
143 (VEX_LEN_0F58_P_1): Likewise.
144 (VEX_LEN_0F58_P_3): Likewise.
145 (VEX_LEN_0F59_P_1): Likewise.
146 (VEX_LEN_0F59_P_3): Likewise.
147 (VEX_LEN_0F5A_P_1): Likewise.
148 (VEX_LEN_0F5A_P_3): Likewise.
149 (VEX_LEN_0F5C_P_1): Likewise.
150 (VEX_LEN_0F5C_P_3): Likewise.
151 (VEX_LEN_0F5D_P_1): Likewise.
152 (VEX_LEN_0F5D_P_3): Likewise.
153 (VEX_LEN_0F5E_P_1): Likewise.
154 (VEX_LEN_0F5E_P_3): Likewise.
155 (VEX_LEN_0F5F_P_1): Likewise.
156 (VEX_LEN_0F5F_P_3): Likewise.
157 (VEX_LEN_0FC2_P_1): Likewise.
158 (VEX_LEN_0FC2_P_3): Likewise.
159 (VEX_LEN_0F3A0A_P_2): Likewise.
160 (VEX_LEN_0F3A0B_P_2): Likewise.
161 (VEX_W_0F10_P_0): Likewise.
162 (VEX_W_0F10_P_1): Likewise.
163 (VEX_W_0F10_P_2): Likewise.
164 (VEX_W_0F10_P_3): Likewise.
165 (VEX_W_0F11_P_0): Likewise.
166 (VEX_W_0F11_P_1): Likewise.
167 (VEX_W_0F11_P_2): Likewise.
168 (VEX_W_0F11_P_3): Likewise.
169 (VEX_W_0F12_P_0_M_0): Likewise.
170 (VEX_W_0F12_P_0_M_1): Likewise.
171 (VEX_W_0F12_P_1): Likewise.
172 (VEX_W_0F12_P_2): Likewise.
173 (VEX_W_0F12_P_3): Likewise.
174 (VEX_W_0F13_M_0): Likewise.
175 (VEX_W_0F14): Likewise.
176 (VEX_W_0F15): Likewise.
177 (VEX_W_0F16_P_0_M_0): Likewise.
178 (VEX_W_0F16_P_0_M_1): Likewise.
179 (VEX_W_0F16_P_1): Likewise.
180 (VEX_W_0F16_P_2): Likewise.
181 (VEX_W_0F17_M_0): Likewise.
182 (VEX_W_0F28): Likewise.
183 (VEX_W_0F29): Likewise.
184 (VEX_W_0F2B_M_0): Likewise.
185 (VEX_W_0F2E_P_0): Likewise.
186 (VEX_W_0F2E_P_2): Likewise.
187 (VEX_W_0F2F_P_0): Likewise.
188 (VEX_W_0F2F_P_2): Likewise.
189 (VEX_W_0F50_M_0): Likewise.
190 (VEX_W_0F51_P_0): Likewise.
191 (VEX_W_0F51_P_1): Likewise.
192 (VEX_W_0F51_P_2): Likewise.
193 (VEX_W_0F51_P_3): Likewise.
194 (VEX_W_0F52_P_0): Likewise.
195 (VEX_W_0F52_P_1): Likewise.
196 (VEX_W_0F53_P_0): Likewise.
197 (VEX_W_0F53_P_1): Likewise.
198 (VEX_W_0F58_P_0): Likewise.
199 (VEX_W_0F58_P_1): Likewise.
200 (VEX_W_0F58_P_2): Likewise.
201 (VEX_W_0F58_P_3): Likewise.
202 (VEX_W_0F59_P_0): Likewise.
203 (VEX_W_0F59_P_1): Likewise.
204 (VEX_W_0F59_P_2): Likewise.
205 (VEX_W_0F59_P_3): Likewise.
206 (VEX_W_0F5A_P_0): Likewise.
207 (VEX_W_0F5A_P_1): Likewise.
208 (VEX_W_0F5A_P_3): Likewise.
209 (VEX_W_0F5B_P_0): Likewise.
210 (VEX_W_0F5B_P_1): Likewise.
211 (VEX_W_0F5B_P_2): Likewise.
212 (VEX_W_0F5C_P_0): Likewise.
213 (VEX_W_0F5C_P_1): Likewise.
214 (VEX_W_0F5C_P_2): Likewise.
215 (VEX_W_0F5C_P_3): Likewise.
216 (VEX_W_0F5D_P_0): Likewise.
217 (VEX_W_0F5D_P_1): Likewise.
218 (VEX_W_0F5D_P_2): Likewise.
219 (VEX_W_0F5D_P_3): Likewise.
220 (VEX_W_0F5E_P_0): Likewise.
221 (VEX_W_0F5E_P_1): Likewise.
222 (VEX_W_0F5E_P_2): Likewise.
223 (VEX_W_0F5E_P_3): Likewise.
224 (VEX_W_0F5F_P_0): Likewise.
225 (VEX_W_0F5F_P_1): Likewise.
226 (VEX_W_0F5F_P_2): Likewise.
227 (VEX_W_0F5F_P_3): Likewise.
228 (VEX_W_0F60_P_2): Likewise.
229 (VEX_W_0F61_P_2): Likewise.
230 (VEX_W_0F62_P_2): Likewise.
231 (VEX_W_0F63_P_2): Likewise.
232 (VEX_W_0F64_P_2): Likewise.
233 (VEX_W_0F65_P_2): Likewise.
234 (VEX_W_0F66_P_2): Likewise.
235 (VEX_W_0F67_P_2): Likewise.
236 (VEX_W_0F68_P_2): Likewise.
237 (VEX_W_0F69_P_2): Likewise.
238 (VEX_W_0F6A_P_2): Likewise.
239 (VEX_W_0F6B_P_2): Likewise.
240 (VEX_W_0F6C_P_2): Likewise.
241 (VEX_W_0F6D_P_2): Likewise.
242 (VEX_W_0F6F_P_1): Likewise.
243 (VEX_W_0F6F_P_2): Likewise.
244 (VEX_W_0F70_P_1): Likewise.
245 (VEX_W_0F70_P_2): Likewise.
246 (VEX_W_0F70_P_3): Likewise.
247 (VEX_W_0F71_R_2_P_2): Likewise.
248 (VEX_W_0F71_R_4_P_2): Likewise.
249 (VEX_W_0F71_R_6_P_2): Likewise.
250 (VEX_W_0F72_R_2_P_2): Likewise.
251 (VEX_W_0F72_R_4_P_2): Likewise.
252 (VEX_W_0F72_R_6_P_2): Likewise.
253 (VEX_W_0F73_R_2_P_2): Likewise.
254 (VEX_W_0F73_R_3_P_2): Likewise.
255 (VEX_W_0F73_R_6_P_2): Likewise.
256 (VEX_W_0F73_R_7_P_2): Likewise.
257 (VEX_W_0F74_P_2): Likewise.
258 (VEX_W_0F75_P_2): Likewise.
259 (VEX_W_0F76_P_2): Likewise.
260 (VEX_W_0F77_P_0): Likewise.
261 (VEX_W_0F7C_P_2): Likewise.
262 (VEX_W_0F7C_P_3): Likewise.
263 (VEX_W_0F7D_P_2): Likewise.
264 (VEX_W_0F7D_P_3): Likewise.
265 (VEX_W_0F7E_P_1): Likewise.
266 (VEX_W_0F7F_P_1): Likewise.
267 (VEX_W_0F7F_P_2): Likewise.
268 (VEX_W_0FAE_R_2_M_0): Likewise.
269 (VEX_W_0FAE_R_3_M_0): Likewise.
270 (VEX_W_0FC2_P_0): Likewise.
271 (VEX_W_0FC2_P_1): Likewise.
272 (VEX_W_0FC2_P_2): Likewise.
273 (VEX_W_0FC2_P_3): Likewise.
274 (VEX_W_0FD0_P_2): Likewise.
275 (VEX_W_0FD0_P_3): Likewise.
276 (VEX_W_0FD1_P_2): Likewise.
277 (VEX_W_0FD2_P_2): Likewise.
278 (VEX_W_0FD3_P_2): Likewise.
279 (VEX_W_0FD4_P_2): Likewise.
280 (VEX_W_0FD5_P_2): Likewise.
281 (VEX_W_0FD6_P_2): Likewise.
282 (VEX_W_0FD7_P_2_M_1): Likewise.
283 (VEX_W_0FD8_P_2): Likewise.
284 (VEX_W_0FD9_P_2): Likewise.
285 (VEX_W_0FDA_P_2): Likewise.
286 (VEX_W_0FDB_P_2): Likewise.
287 (VEX_W_0FDC_P_2): Likewise.
288 (VEX_W_0FDD_P_2): Likewise.
289 (VEX_W_0FDE_P_2): Likewise.
290 (VEX_W_0FDF_P_2): Likewise.
291 (VEX_W_0FE0_P_2): Likewise.
292 (VEX_W_0FE1_P_2): Likewise.
293 (VEX_W_0FE2_P_2): Likewise.
294 (VEX_W_0FE3_P_2): Likewise.
295 (VEX_W_0FE4_P_2): Likewise.
296 (VEX_W_0FE5_P_2): Likewise.
297 (VEX_W_0FE6_P_1): Likewise.
298 (VEX_W_0FE6_P_2): Likewise.
299 (VEX_W_0FE6_P_3): Likewise.
300 (VEX_W_0FE7_P_2_M_0): Likewise.
301 (VEX_W_0FE8_P_2): Likewise.
302 (VEX_W_0FE9_P_2): Likewise.
303 (VEX_W_0FEA_P_2): Likewise.
304 (VEX_W_0FEB_P_2): Likewise.
305 (VEX_W_0FEC_P_2): Likewise.
306 (VEX_W_0FED_P_2): Likewise.
307 (VEX_W_0FEE_P_2): Likewise.
308 (VEX_W_0FEF_P_2): Likewise.
309 (VEX_W_0FF0_P_3_M_0): Likewise.
310 (VEX_W_0FF1_P_2): Likewise.
311 (VEX_W_0FF2_P_2): Likewise.
312 (VEX_W_0FF3_P_2): Likewise.
313 (VEX_W_0FF4_P_2): Likewise.
314 (VEX_W_0FF5_P_2): Likewise.
315 (VEX_W_0FF6_P_2): Likewise.
316 (VEX_W_0FF7_P_2): Likewise.
317 (VEX_W_0FF8_P_2): Likewise.
318 (VEX_W_0FF9_P_2): Likewise.
319 (VEX_W_0FFA_P_2): Likewise.
320 (VEX_W_0FFB_P_2): Likewise.
321 (VEX_W_0FFC_P_2): Likewise.
322 (VEX_W_0FFD_P_2): Likewise.
323 (VEX_W_0FFE_P_2): Likewise.
324 (VEX_W_0F3800_P_2): Likewise.
325 (VEX_W_0F3801_P_2): Likewise.
326 (VEX_W_0F3802_P_2): Likewise.
327 (VEX_W_0F3803_P_2): Likewise.
328 (VEX_W_0F3804_P_2): Likewise.
329 (VEX_W_0F3805_P_2): Likewise.
330 (VEX_W_0F3806_P_2): Likewise.
331 (VEX_W_0F3807_P_2): Likewise.
332 (VEX_W_0F3808_P_2): Likewise.
333 (VEX_W_0F3809_P_2): Likewise.
334 (VEX_W_0F380A_P_2): Likewise.
335 (VEX_W_0F380B_P_2): Likewise.
336 (VEX_W_0F3817_P_2): Likewise.
337 (VEX_W_0F381C_P_2): Likewise.
338 (VEX_W_0F381D_P_2): Likewise.
339 (VEX_W_0F381E_P_2): Likewise.
340 (VEX_W_0F3820_P_2): Likewise.
341 (VEX_W_0F3821_P_2): Likewise.
342 (VEX_W_0F3822_P_2): Likewise.
343 (VEX_W_0F3823_P_2): Likewise.
344 (VEX_W_0F3824_P_2): Likewise.
345 (VEX_W_0F3825_P_2): Likewise.
346 (VEX_W_0F3828_P_2): Likewise.
347 (VEX_W_0F3829_P_2): Likewise.
348 (VEX_W_0F382A_P_2_M_0): Likewise.
349 (VEX_W_0F382B_P_2): Likewise.
350 (VEX_W_0F3830_P_2): Likewise.
351 (VEX_W_0F3831_P_2): Likewise.
352 (VEX_W_0F3832_P_2): Likewise.
353 (VEX_W_0F3833_P_2): Likewise.
354 (VEX_W_0F3834_P_2): Likewise.
355 (VEX_W_0F3835_P_2): Likewise.
356 (VEX_W_0F3837_P_2): Likewise.
357 (VEX_W_0F3838_P_2): Likewise.
358 (VEX_W_0F3839_P_2): Likewise.
359 (VEX_W_0F383A_P_2): Likewise.
360 (VEX_W_0F383B_P_2): Likewise.
361 (VEX_W_0F383C_P_2): Likewise.
362 (VEX_W_0F383D_P_2): Likewise.
363 (VEX_W_0F383E_P_2): Likewise.
364 (VEX_W_0F383F_P_2): Likewise.
365 (VEX_W_0F3840_P_2): Likewise.
366 (VEX_W_0F3841_P_2): Likewise.
367 (VEX_W_0F38DB_P_2): Likewise.
368 (VEX_W_0F3A08_P_2): Likewise.
369 (VEX_W_0F3A09_P_2): Likewise.
370 (VEX_W_0F3A0A_P_2): Likewise.
371 (VEX_W_0F3A0B_P_2): Likewise.
372 (VEX_W_0F3A0C_P_2): Likewise.
373 (VEX_W_0F3A0D_P_2): Likewise.
374 (VEX_W_0F3A0E_P_2): Likewise.
375 (VEX_W_0F3A0F_P_2): Likewise.
376 (VEX_W_0F3A21_P_2): Likewise.
377 (VEX_W_0F3A40_P_2): Likewise.
378 (VEX_W_0F3A41_P_2): Likewise.
379 (VEX_W_0F3A42_P_2): Likewise.
380 (VEX_W_0F3A62_P_2): Likewise.
381 (VEX_W_0F3A63_P_2): Likewise.
382 (VEX_W_0F3ADF_P_2): Likewise.
383 (VEX_LEN_0F77_P_0): New.
384 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
385 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
386 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
387 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
388 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
389 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
390 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
391 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
392 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
393 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
394 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
395 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
396 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
397 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
398 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
399 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
400 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
401 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
402 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
403 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
404 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
405 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
406 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
407 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
408 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
409 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
410 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
411 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
412 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
413 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
414 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
415 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
416 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
417 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
418 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
419 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
420 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
421 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
422 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
423 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
424 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
425 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
426 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
427 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
428 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
429 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
430 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
431 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
432 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
433 (vex_table): Update VEX 0F28 and 0F29 entries.
434 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
435 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
436 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
437 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
438 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
439 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
440 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
441 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
442 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
443 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
444 VEX_LEN_0F3A0B_P_2 entries.
445 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
446 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
447 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
448 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
449 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
450 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
451 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
452 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
453 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
454 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
455 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
456 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
457 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
458 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
459 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
460 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
461 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
462 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
463 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
464 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
465 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
466 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
467 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
468 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
469 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
470 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
471 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
472 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
473 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
474 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
475 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
476 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
477 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
478 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
479 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
480 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
481 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
482 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
483 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
484 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
485 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
486 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
487 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
488 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
489 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
490 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
491 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
492 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
493 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
494 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
495 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
496 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
497 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
498 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
499 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
500 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
501 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
502 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
503 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
504 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
505 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
506 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
507 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
508 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
509 VEX_W_0F3ADF_P_2 entries.
510 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
511 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
512 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
513
6fa52824
L		 5142018-09-17 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-opc.tbl (VexWIG): New.
517 Replace VexW=3 with VexWIG.
518
db4cc665
L		 5192018-09-15 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
522 * i386-tbl.h: Regenerated.
523
3c374143
L		 5242018-09-15 H.J. Lu <hongjiu.lu@intel.com>
525
526 PR gas/23665
527 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
528 VEX_LEN_0FD6_P_2 entries.
529 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
530 * i386-tbl.h: Regenerated.
531
6865c043
L		 5322018-09-14 H.J. Lu <hongjiu.lu@intel.com>
533
534 PR gas/23642
535 * i386-opc.h (VEXWIG): New.
536 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
537 * i386-tbl.h: Regenerated.
538
70df6fc9
L		 5392018-09-14 H.J. Lu <hongjiu.lu@intel.com>
540
541 PR binutils/23655
542 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
543 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
544 * i386-dis.c (EXxEVexR64): New.
545 (evex_rounding_64_mode): Likewise.
546 (OP_Rounding): Handle evex_rounding_64_mode.
547
d20dee9e
L		 5482018-09-14 H.J. Lu <hongjiu.lu@intel.com>
549
550 PR binutils/23655
551 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
552 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
553 * i386-dis.c (Edqa): New.
554 (dqa_mode): Likewise.
555 (intel_operand_size): Handle dqa_mode as m_mode.
556 (OP_E_register): Handle dqa_mode as dq_mode.
557 (OP_E_memory): Set shift for dqa_mode based on address_mode.
558
5074ad8a
L		 5592018-09-14 H.J. Lu <hongjiu.lu@intel.com>
560
561 * i386-dis.c (OP_E_memory): Reformat.
562
556059dd
JB		 5632018-09-14 Jan Beulich <jbeulich@suse.com>
564
565 * i386-opc.tbl (crc32): Fold byte and word forms.
566 * i386-tbl.h: Re-generate.
567
41d1ab6a
L		 5682018-09-13 H.J. Lu <hongjiu.lu@intel.com>
569
570 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
571 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
572 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
573 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
574 * i386-tbl.h: Regenerated.
575
57f6375e
JB		 5762018-09-13 Jan Beulich <jbeulich@suse.com>
577
578 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
579 meaningless.
580 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
581 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
582 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
583 * i386-tbl.h: Re-generate.
584
2589a7e5
JB		 5852018-09-13 Jan Beulich <jbeulich@suse.com>
586
587 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
588 AVX512_4VNNIW insns.
589 * i386-tbl.h: Re-generate.
590
a760eb41
JB		 5912018-09-13 Jan Beulich <jbeulich@suse.com>
592
593 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
594 meaningless.
595 * i386-tbl.h: Re-generate.
596
e9042658
JB		 5972018-09-13 Jan Beulich <jbeulich@suse.com>
598
599 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
600 meaningless.
601 * i386-tbl.h: Re-generate.
602
9caa306f
JB		 6032018-09-13 Jan Beulich <jbeulich@suse.com>
604
605 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
606 meaningless.
607 * i386-tbl.h: Re-generate.
608
fb6ce599
JB		 6092018-09-13 Jan Beulich <jbeulich@suse.com>
610
611 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
612 meaningless.
613 * i386-tbl.h: Re-generate.
614
6a8da886
JB		 6152018-09-13 Jan Beulich <jbeulich@suse.com>
616
617 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
618 meaningless.
619 * i386-tbl.h: Re-generate.
620
c7f27919
JB		 6212018-09-13 Jan Beulich <jbeulich@suse.com>
622
623 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
624 * i386-tbl.h: Re-generate.
625
0f407ee9
JB		 6262018-09-13 Jan Beulich <jbeulich@suse.com>
627
628 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
629 * i386-tbl.h: Re-generate.
630
2fbbbee5
JB		 6312018-09-13 Jan Beulich <jbeulich@suse.com>
632
633 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
634 meaningless.
635 * i386-tbl.h: Re-generate.
636
2b02b9a2
JB		 6372018-09-13 Jan Beulich <jbeulich@suse.com>
638
639 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
640 meaningless.
641 * i386-tbl.h: Re-generate.
642
963c68aa
JB		 6432018-09-13 Jan Beulich <jbeulich@suse.com>
644
645 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
646 * i386-tbl.h: Re-generate.
647
64e025c3
JB		 6482018-09-13 Jan Beulich <jbeulich@suse.com>
649
650 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
651 * i386-tbl.h: Re-generate.
652
47603f88
JB		 6532018-09-13 Jan Beulich <jbeulich@suse.com>
654
655 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
656 * i386-tbl.h: Re-generate.
657
0001cfd0
JB		 6582018-09-13 Jan Beulich <jbeulich@suse.com>
659
660 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
661 meaningless.
662 * i386-tbl.h: Re-generate.
663
be4b452e
JB		 6642018-09-13 Jan Beulich <jbeulich@suse.com>
665
666 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
667 meaningless.
668 * i386-tbl.h: Re-generate.
669
d09a1394
JB		 6702018-09-13 Jan Beulich <jbeulich@suse.com>
671
672 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
673 meaningless.
674 * i386-tbl.h: Re-generate.
675
07599e13
JB		 6762018-09-13 Jan Beulich <jbeulich@suse.com>
677
678 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
679 * i386-tbl.h: Re-generate.
680
1ee3e487
JB		 6812018-09-13 Jan Beulich <jbeulich@suse.com>
682
683 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
684 * i386-tbl.h: Re-generate.
685
a5f580e5
JB		 6862018-09-13 Jan Beulich <jbeulich@suse.com>
687
688 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
689 * i386-tbl.h: Re-generate.
690
49d5d12d
JB		 6912018-09-13 Jan Beulich <jbeulich@suse.com>
692
693 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
694 (vpbroadcastw, rdpid): Drop NoRex64.
695 * i386-tbl.h: Re-generate.
696
f5eb1d70
JB		 6972018-09-13 Jan Beulich <jbeulich@suse.com>
698
699 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
700 store templates, adding D.
701 * i386-tbl.h: Re-generate.
702
dbbc8b7e
JB		 7032018-09-13 Jan Beulich <jbeulich@suse.com>
704
705 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
706 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
707 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
708 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
709 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
710 Fold load and store templates where possible, adding D. Drop
711 IgnoreSize where it was pointlessly present. Drop redundant
712 *word.
713 * i386-tbl.h: Re-generate.
714
d276ec69
JB		 7152018-09-13 Jan Beulich <jbeulich@suse.com>
716
717 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
718 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
719 (intel_operand_size): Handle v_bndmk_mode.
720 (OP_E_memory): Likewise. Produce (bad) when also riprel.
721
9da4dfd6
JD		 7222018-09-08 John Darrington <john@darrington.wattle.id.au>
723
724 * disassemble.c (ARCH_s12z): Define if ARCH_all.
725
be192bc2
JW		 7262018-08-31 Kito Cheng <kito@andestech.com>
727
728 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
729 compressed floating point instructions.
730
43135d3b
JW		 7312018-08-30 Kito Cheng <kito@andestech.com>
732
733 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
734 riscv_opcode.xlen_requirement.
735 * riscv-opc.c (riscv_opcodes): Update for struct change.
736
df28970f
MA		 7372018-08-29 Martin Aberg <maberg@gaisler.com>
738
739 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
740 psr (PWRPSR) instruction.
741
9108bc33
CX		 7422018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
743
744 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
745
bd782c07
CX		 7462018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
747
748 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
749
ac8cb70f
CX		 7502018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
751
752 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
753 loongson3a as an alias of gs464 for compatibility.
754 * mips-opc.c (mips_opcodes): Change Comments.
755
a693765e
CX		 7562018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
757
758 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
759 option.
760 (print_mips_disassembler_options): Document -M loongson-ext.
761 * mips-opc.c (LEXT2): New macro.
762 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
763
bdc6c06e
CX		 7642018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
765
766 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
767 descriptors.
768 (parse_mips_ase_option): Handle -M loongson-ext option.
769 (print_mips_disassembler_options): Document -M loongson-ext.
770 * mips-opc.c (IL3A): Delete.
771 * mips-opc.c (LEXT): New macro.
772 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
773 instructions.
774
716c08de
CX		 7752018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
776
777 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
778 descriptors.
779 (parse_mips_ase_option): Handle -M loongson-cam option.
780 (print_mips_disassembler_options): Document -M loongson-cam.
781 * mips-opc.c (LCAM): New macro.
782 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
783 instructions.
784
9cf7e568
AM		 7852018-08-21 Alan Modra <amodra@gmail.com>
786
787 * ppc-dis.c (operand_value_powerpc): Init "invalid".
788 (skip_optional_operands): Count optional operands, and update
789 ppc_optional_operand_value call.
790 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
791 (extract_vlensi): Likewise.
792 (extract_fxm): Return default value for missing optional operand.
793 (extract_ls, extract_raq, extract_tbr): Likewise.
794 (insert_sxl, extract_sxl): New functions.
795 (insert_esync, extract_esync): Remove Power9 handling and simplify.
796 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
797 flag and extra entry.
798 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
799 extract_sxl.
800
d203b41a 8012018-08-20 Alan Modra <amodra@gmail.com>
f4107842 802
d203b41a 803 * sh-opc.h (MASK): Simplify.
f4107842 804
08a8fe2f 8052018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 806
d203b41a
AM		 807 * s12z-dis.c (bm_decode): Deal with cases where the mode is
808 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 809 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 810
08a8fe2f 8112018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 812
813 * s12z.h: Delete.
7ba3ba91 814
1bc60e56
L		 8152018-08-14 H.J. Lu <hongjiu.lu@intel.com>
816
817 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
818 address with the addr32 prefix and without base nor index
819 registers.
820
d871f3f4
L		 8212018-08-11 H.J. Lu <hongjiu.lu@intel.com>
822
823 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
824 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
825 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
826 (cpu_flags): Add CpuCMOV and CpuFXSR.
827 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
828 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
829 * i386-init.h: Regenerated.
830 * i386-tbl.h: Likewise.
831
b6523c37 8322018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
833
834 * arc-regs.h: Update auxiliary registers.
835
e968fc9b
JB		 8362018-08-06 Jan Beulich <jbeulich@suse.com>
837
838 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
839 (RegIP, RegIZ): Define.
840 * i386-reg.tbl: Adjust comments.
841 (rip): Use Qword instead of BaseIndex. Use RegIP.
842 (eip): Use Dword instead of BaseIndex. Use RegIP.
843 (riz): Add Qword. Use RegIZ.
844 (eiz): Add Dword. Use RegIZ.
845 * i386-tbl.h: Re-generate.
846
dbf8be89
JB		 8472018-08-03 Jan Beulich <jbeulich@suse.com>
848
849 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
850 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
851 vpmovzxdq, vpmovzxwd): Remove NoRex64.
852 * i386-tbl.h: Re-generate.
853
c48dadc9
JB		 8542018-08-03 Jan Beulich <jbeulich@suse.com>
855
856 * i386-gen.c (operand_types): Remove Mem field.
857 * i386-opc.h (union i386_operand_type): Remove mem field.
858 * i386-init.h, i386-tbl.h: Re-generate.
859
cb86a42a
AM		 8602018-08-01 Alan Modra <amodra@gmail.com>
861
862 * po/POTFILES.in: Regenerate.
863
07cc0450
NC		 8642018-07-31 Nick Clifton <nickc@redhat.com>
865
866 * po/sv.po: Updated Swedish translation.
867
1424ad86
JB		 8682018-07-31 Jan Beulich <jbeulich@suse.com>
869
870 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
871 * i386-init.h, i386-tbl.h: Re-generate.
872
ae2387fe
JB		 8732018-07-31 Jan Beulich <jbeulich@suse.com>
874
875 * i386-opc.h (ZEROING_MASKING) Rename to ...
876 (DYNAMIC_MASKING): ... this. Adjust comment.
877 * i386-opc.tbl (MaskingMorZ): Define.
878 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
879 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
880 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
881 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
882 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
883 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
884 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
885 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
886 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
887
6ff00b5e
JB		 8882018-07-31 Jan Beulich <jbeulich@suse.com>
889
890 * i386-opc.tbl: Use element rather than vector size for AVX512*
891 scatter/gather insns.
892 * i386-tbl.h: Re-generate.
893
e951d5ca
JB		 8942018-07-31 Jan Beulich <jbeulich@suse.com>
895
896 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
897 (cpu_flags): Drop CpuVREX.
898 * i386-opc.h (CpuVREX): Delete.
899 (union i386_cpu_flags): Remove cpuvrex.
900 * i386-init.h, i386-tbl.h: Re-generate.
901
eb41b248
JW		 9022018-07-30 Jim Wilson <jimw@sifive.com>
903
904 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
905 fields.
906 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
907
b8891f8d
AJ		 9082018-07-30 Andrew Jenner <andrew@codesourcery.com>
909
910 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
911 * Makefile.in: Regenerated.
912 * configure.ac: Add C-SKY.
913 * configure: Regenerated.
914 * csky-dis.c: New file.
915 * csky-opc.h: New file.
916 * disassemble.c (ARCH_csky): Define.
917 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
918 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
919
16065af1
AM		 9202018-07-27 Alan Modra <amodra@gmail.com>
921
922 * ppc-opc.c (insert_sprbat): Correct function parameter and
923 return type.
924 (extract_sprbat): Likewise, variable too.
925
fa758a70
AC		 9262018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
927 Alan Modra <amodra@gmail.com>
928
929 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
930 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
931 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
932 support disjointed BAT.
933 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
934 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
935 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
936
4a1b91ea
L		 9372018-07-25 H.J. Lu <hongjiu.lu@intel.com>
938 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
939
940 * i386-gen.c (adjust_broadcast_modifier): New function.
941 (process_i386_opcode_modifier): Add an argument for operands.
942 Adjust the Broadcast value based on operands.
943 (output_i386_opcode): Pass operand_types to
944 process_i386_opcode_modifier.
945 (process_i386_opcodes): Pass NULL as operands to
946 process_i386_opcode_modifier.
947 * i386-opc.h (BYTE_BROADCAST): New.
948 (WORD_BROADCAST): Likewise.
949 (DWORD_BROADCAST): Likewise.
950 (QWORD_BROADCAST): Likewise.
951 (i386_opcode_modifier): Expand broadcast to 3 bits.
952 * i386-tbl.h: Regenerated.
953
67ce483b
AM		 9542018-07-24 Alan Modra <amodra@gmail.com>
955
956 PR 23430
957 * or1k-desc.h: Regenerate.
958
4174bfff
JB		 9592018-07-24 Jan Beulich <jbeulich@suse.com>
960
961 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
962 vcvtusi2ss, and vcvtusi2sd.
963 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
964 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
965 * i386-tbl.h: Re-generate.
966
04e65276
CZ		 9672018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
968
969 * arc-opc.c (extract_w6): Fix extending the sign.
970
47e6f81c
CZ		 9712018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
972
973 * arc-tbl.h (vewt): Allow it for ARC EM family.
974
bb71536f
AM		 9752018-07-23 Alan Modra <amodra@gmail.com>
976
977 PR 23419
978 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
979 opcode variants for mtspr/mfspr encodings.
980
8095d2f7
CX		 9812018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
982 Maciej W. Rozycki <macro@mips.com>
983
984 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
985 loongson3a descriptors.
986 (parse_mips_ase_option): Handle -M loongson-mmi option.
987 (print_mips_disassembler_options): Document -M loongson-mmi.
988 * mips-opc.c (LMMI): New macro.
989 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
990 instructions.
991
5f32791e
JB		 9922018-07-19 Jan Beulich <jbeulich@suse.com>
993
994 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
995 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
996 IgnoreSize and [XYZ]MMword where applicable.
997 * i386-tbl.h: Re-generate.
998
625cbd7a
JB		 9992018-07-19 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1002 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1003 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1004 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1005 * i386-tbl.h: Re-generate.
1006
86b15c32
JB		 10072018-07-19 Jan Beulich <jbeulich@suse.com>
1008
1009 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1010 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1011 VPCLMULQDQ templates into their respective AVX512VL counterparts
1012 where possible, using Disp8ShiftVL and CheckRegSize instead of
1013 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1014 * i386-tbl.h: Re-generate.
1015
cf769ed5
JB		 10162018-07-19 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1019 AVX512VL counterparts where possible, using Disp8ShiftVL and
1020 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1021 IgnoreSize) as appropriate.
1022 * i386-tbl.h: Re-generate.
1023
8282b7ad
JB		 10242018-07-19 Jan Beulich <jbeulich@suse.com>
1025
1026 * i386-opc.tbl: Fold AVX512BW templates into their respective
1027 AVX512VL counterparts where possible, using Disp8ShiftVL and
1028 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1029 IgnoreSize) as appropriate.
1030 * i386-tbl.h: Re-generate.
1031
755908cc
JB		 10322018-07-19 Jan Beulich <jbeulich@suse.com>
1033
1034 * i386-opc.tbl: Fold AVX512CD templates into their respective
1035 AVX512VL counterparts where possible, using Disp8ShiftVL and
1036 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1037 IgnoreSize) as appropriate.
1038 * i386-tbl.h: Re-generate.
1039
7091c612
JB		 10402018-07-19 Jan Beulich <jbeulich@suse.com>
1041
1042 * i386-opc.h (DISP8_SHIFT_VL): New.
1043 * i386-opc.tbl (Disp8ShiftVL): Define.
1044 (various): Fold AVX512VL templates into their respective
1045 AVX512F counterparts where possible, using Disp8ShiftVL and
1046 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1047 IgnoreSize) as appropriate.
1048 * i386-tbl.h: Re-generate.
1049
c30be56e
JB		 10502018-07-19 Jan Beulich <jbeulich@suse.com>
1051
1052 * Makefile.am: Change dependencies and rule for
1053 $(srcdir)/i386-init.h.
1054 * Makefile.in: Re-generate.
1055 * i386-gen.c (process_i386_opcodes): New local variable
1056 "marker". Drop opening of input file. Recognize marker and line
1057 number directives.
1058 * i386-opc.tbl (OPCODE_I386_H): Define.
1059 (i386-opc.h): Include it.
1060 (None): Undefine.
1061
11a322db
L		 10622018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1063
1064 PR gas/23418
1065 * i386-opc.h (Byte): Update comments.
1066 (Word): Likewise.
1067 (Dword): Likewise.
1068 (Fword): Likewise.
1069 (Qword): Likewise.
1070 (Tbyte): Likewise.
1071 (Xmmword): Likewise.
1072 (Ymmword): Likewise.
1073 (Zmmword): Likewise.
1074 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1075 vcvttps2uqq.
1076 * i386-tbl.h: Regenerated.
1077
cde3679e
NC		 10782018-07-12 Sudakshina Das <sudi.das@arm.com>
1079
1080 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1081 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1082 * aarch64-asm-2.c: Regenerate.
1083 * aarch64-dis-2.c: Regenerate.
1084 * aarch64-opc-2.c: Regenerate.
1085
45a28947
TC		 10862018-07-12 Tamar Christina <tamar.christina@arm.com>
1087
1088 PR binutils/23192
1089 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1090 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1091 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1092 sqdmulh, sqrdmulh): Use Em16.
1093
c597cc3d
SD		 10942018-07-11 Sudakshina Das <sudi.das@arm.com>
1095
1096 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1097 csdb together with them.
1098 (thumb32_opcodes): Likewise.
1099
a79eaed6
JB		 11002018-07-11 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1103 requiring 32-bit registers as operands 2 and 3. Improve
1104 comments.
1105 (mwait, mwaitx): Fold templates. Improve comments.
1106 OPERAND_TYPE_INOUTPORTREG.
1107 * i386-tbl.h: Re-generate.
1108
2fb5be8d
JB		 11092018-07-11 Jan Beulich <jbeulich@suse.com>
1110
1111 * i386-gen.c (operand_type_init): Remove
1112 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1113 OPERAND_TYPE_INOUTPORTREG.
1114 * i386-init.h: Re-generate.
1115
7f5cad30
JB		 11162018-07-11 Jan Beulich <jbeulich@suse.com>
1117
1118 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1119 (wrssq, wrussq): Add Qword.
1120 * i386-tbl.h: Re-generate.
1121
f0a85b07
JB		 11222018-07-11 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-opc.h: Rename OTMax to OTNum.
1125 (OTNumOfUints): Adjust calculation.
1126 (OTUnused): Directly alias to OTNum.
1127
9dcb0ba4
MR		 11282018-07-09 Maciej W. Rozycki <macro@mips.com>
1129
1130 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1131 `reg_xys'.
1132 (lea_reg_xys): Likewise.
1133 (print_insn_loop_primitive): Rename `reg' local variable to
1134 `reg_dxy'.
1135
f311ba7e
TC		 11362018-07-06 Tamar Christina <tamar.christina@arm.com>
1137
1138 PR binutils/23242
1139 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1140
cba05feb
TC		 11412018-07-06 Tamar Christina <tamar.christina@arm.com>
1142
1143 PR binutils/23369
1144 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1145 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1146
471b9d15
MR		 11472018-07-02 Maciej W. Rozycki <macro@mips.com>
1148
1149 PR tdep/8282
1150 * mips-dis.c (mips_option_arg_t): New enumeration.
1151 (mips_options): New variable.
1152 (disassembler_options_mips): New function.
1153 (print_mips_disassembler_options): Reimplement in terms of
1154 `disassembler_options_mips'.
1155 * arm-dis.c (disassembler_options_arm): Adapt to using the
1156 `disasm_options_and_args_t' structure.
1157 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1158 * s390-dis.c (disassembler_options_s390): Likewise.
1159
c0c468d5
TP		 11602018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1161
1162 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1163 expected result.
1164 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1165 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1166 * testsuite/ld-arm/tls-longplt.d: Likewise.
1167
369c9167
TC		 11682018-06-29 Tamar Christina <tamar.christina@arm.com>
1169
1170 PR binutils/23192
1171 * aarch64-asm-2.c: Regenerate.
1172 * aarch64-dis-2.c: Likewise.
1173 * aarch64-opc-2.c: Likewise.
1174 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1175 * aarch64-opc.c (operand_general_constraint_met_p,
1176 aarch64_print_operand): Likewise.
1177 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1178 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1179 fmlal2, fmlsl2.
1180 (AARCH64_OPERANDS): Add Em2.
1181
30aa1306
NC		 11822018-06-26 Nick Clifton <nickc@redhat.com>
1183
1184 * po/uk.po: Updated Ukranian translation.
1185 * po/de.po: Updated German translation.
1186 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1187
eca4b721
NC		 11882018-06-26 Nick Clifton <nickc@redhat.com>
1189
1190 * nfp-dis.c: Fix spelling mistake.
1191
71300e2c
NC		 11922018-06-24 Nick Clifton <nickc@redhat.com>
1193
1194 * configure: Regenerate.
1195 * po/opcodes.pot: Regenerate.
1196
719d8288
NC		 11972018-06-24 Nick Clifton <nickc@redhat.com>
1198
1199 2.31 branch created.
1200
514cd3a0
TC		 12012018-06-19 Tamar Christina <tamar.christina@arm.com>
1202
1203 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1204 * aarch64-asm-2.c: Regenerate.
1205 * aarch64-dis-2.c: Likewise.
1206
385e4d0f
MR		 12072018-06-21 Maciej W. Rozycki <macro@mips.com>
1208
1209 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1210 `-M ginv' option description.
1211
160d1b3d
SH		 12122018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1213
1214 PR gas/23305
1215 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1216 la and lla.
1217
d0ac1c44
SM		 12182018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1219
1220 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1221 * configure.ac: Remove AC_PREREQ.
1222 * Makefile.in: Re-generate.
1223 * aclocal.m4: Re-generate.
1224 * configure: Re-generate.
1225
6f20c942
FS		 12262018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1227
1228 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1229 mips64r6 descriptors.
1230 (parse_mips_ase_option): Handle -Mginv option.
1231 (print_mips_disassembler_options): Document -Mginv.
1232 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1233 (GINV): New macro.
1234 (mips_opcodes): Define ginvi and ginvt.
1235
730c3174
SE		 12362018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1237 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1238
1239 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1240 * mips-opc.c (CRC, CRC64): New macros.
1241 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1242 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1243 crc32cd for CRC64.
1244
cb366992
EB		 12452018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1246
1247 PR 20319
1248 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1249 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1250
ce72cd46
AM		 12512018-06-06 Alan Modra <amodra@gmail.com>
1252
1253 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1254 setjmp. Move init for some other vars later too.
1255
4b8e28c7
MF		 12562018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1257
1258 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1259 (dis_private): Add new fields for property section tracking.
1260 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1261 (xtensa_instruction_fits): New functions.
1262 (fetch_data): Bump minimal fetch size to 4.
1263 (print_insn_xtensa): Make struct dis_private static.
1264 Load and prepare property table on section change.
1265 Don't disassemble literals. Don't disassemble instructions that
1266 cross property table boundaries.
1267
55e99962
L		 12682018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1269
1270 * configure: Regenerated.
1271
733bd0ab
JB		 12722018-06-01 Jan Beulich <jbeulich@suse.com>
1273
1274 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1275 * i386-tbl.h: Re-generate.
1276
dfd27d41
JB		 12772018-06-01 Jan Beulich <jbeulich@suse.com>
1278
1279 * i386-opc.tbl (sldt, str): Add NoRex64.
1280 * i386-tbl.h: Re-generate.
1281
64795710
JB		 12822018-06-01 Jan Beulich <jbeulich@suse.com>
1283
1284 * i386-opc.tbl (invpcid): Add Oword.
1285 * i386-tbl.h: Re-generate.
1286
030157d8
AM		 12872018-06-01 Alan Modra <amodra@gmail.com>
1288
1289 * sysdep.h (_bfd_error_handler): Don't declare.
1290 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1291 * rl78-decode.opc: Likewise.
1292 * msp430-decode.c: Regenerate.
1293 * rl78-decode.c: Regenerate.
1294
a9660a6f
AP		 12952018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1296
1297 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1298 * i386-init.h : Regenerated.
1299
277eb7f6
AM		 13002018-05-25 Alan Modra <amodra@gmail.com>
1301
1302 * Makefile.in: Regenerate.
1303 * po/POTFILES.in: Regenerate.
1304
98553ad3
PB		 13052018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1306
1307 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1308 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1309 (insert_bab, extract_bab, insert_btab, extract_btab,
1310 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1311 (BAT, BBA VBA RBS XB6S): Delete macros.
1312 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1313 (BB, BD, RBX, XC6): Update for new macros.
1314 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1315 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1316 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1317 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1318
7b4ae824
JD		 13192018-05-18 John Darrington <john@darrington.wattle.id.au>
1320
1321 * Makefile.am: Add support for s12z architecture.
1322 * configure.ac: Likewise.
1323 * disassemble.c: Likewise.
1324 * disassemble.h: Likewise.
1325 * Makefile.in: Regenerate.
1326 * configure: Regenerate.
1327 * s12z-dis.c: New file.
1328 * s12z.h: New file.
1329
29e0f0a1
AM		 13302018-05-18 Alan Modra <amodra@gmail.com>
1331
1332 * nfp-dis.c: Don't #include libbfd.h.
1333 (init_nfp3200_priv): Use bfd_get_section_contents.
1334 (nit_nfp6000_mecsr_sec): Likewise.
1335
809276d2
NC		 13362018-05-17 Nick Clifton <nickc@redhat.com>
1337
1338 * po/zh_CN.po: Updated simplified Chinese translation.
1339
ff329288
TC		 13402018-05-16 Tamar Christina <tamar.christina@arm.com>
1341
1342 PR binutils/23109
1343 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1344 * aarch64-dis-2.c: Regenerate.
1345
f9830ec1
TC		 13462018-05-15 Tamar Christina <tamar.christina@arm.com>
1347
1348 PR binutils/21446
1349 * aarch64-asm.c (opintl.h): Include.
1350 (aarch64_ins_sysreg): Enforce read/write constraints.
1351 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1352 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1353 (F_REG_READ, F_REG_WRITE): New.
1354 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1355 AARCH64_OPND_SYSREG.
1356 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1357 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1358 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1359 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1360 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1361 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1362 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1363 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1364 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1365 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1366 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1367 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1368 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1369 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1370 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1371 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1372 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1373
7d02540a
TC		 13742018-05-15 Tamar Christina <tamar.christina@arm.com>
1375
1376 PR binutils/21446
1377 * aarch64-dis.c (no_notes: New.
1378 (parse_aarch64_dis_option): Support notes.
1379 (aarch64_decode_insn, print_operands): Likewise.
1380 (print_aarch64_disassembler_options): Document notes.
1381 * aarch64-opc.c (aarch64_print_operand): Support notes.
1382
561a72d4
TC		 13832018-05-15 Tamar Christina <tamar.christina@arm.com>
1384
1385 PR binutils/21446
1386 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1387 and take error struct.
1388 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1389 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1390 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1391 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1392 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1393 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1394 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1395 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1396 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1397 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1398 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1399 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1400 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1401 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1402 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1403 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1404 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1405 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1406 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1407 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1408 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1409 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1410 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1411 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1412 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1413 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1414 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1415 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1416 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1417 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1418 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1419 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1420 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1421 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1422 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1423 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1424 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1425 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1426 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1427 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1428 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1429 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1430 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1431 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1432 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1433 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1434 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1435 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1436 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1437 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1438 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1439 (determine_disassembling_preference, aarch64_decode_insn,
1440 print_insn_aarch64_word, print_insn_data): Take errors struct.
1441 (print_insn_aarch64): Use errors.
1442 * aarch64-asm-2.c: Regenerate.
1443 * aarch64-dis-2.c: Regenerate.
1444 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1445 boolean in aarch64_insert_operan.
1446 (print_operand_extractor): Likewise.
1447 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1448
1678bd35
FT		 14492018-05-15 Francois H. Theron <francois.theron@netronome.com>
1450
1451 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1452
06cfb1c8
L		 14532018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1454
1455 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1456
84f9f8c3
AM		 14572018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1458
1459 * cr16-opc.c (cr16_instruction): Comment typo fix.
1460 * hppa-dis.c (print_insn_hppa): Likewise.
1461
e6f372ba
JW		 14622018-05-08 Jim Wilson <jimw@sifive.com>
1463
1464 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1465 (match_c_slli64, match_srxi_as_c_srxi): New.
1466 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1467 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1468 <c.slli, c.srli, c.srai>: Use match_s_slli.
1469 <c.slli64, c.srli64, c.srai64>: New.
1470
f413a913
AM		 14712018-05-08 Alan Modra <amodra@gmail.com>
1472
1473 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1474 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1475 partition opcode space for index lookup.
1476
a87a6478
PB		 14772018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1478
1479 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1480 <insn_length>: ...with this. Update usage.
1481 Remove duplicate call to *info->memory_error_func.
1482
c0a30a9f
L		 14832018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1484 H.J. Lu <hongjiu.lu@intel.com>
1485
1486 * i386-dis.c (Gva): New.
1487 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1488 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1489 (prefix_table): New instructions (see prefix above).
1490 (mod_table): New instructions (see prefix above).
1491 (OP_G): Handle va_mode.
1492 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1493 CPU_MOVDIR64B_FLAGS.
1494 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1495 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1496 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1497 * i386-opc.tbl: Add movidir{i,64b}.
1498 * i386-init.h: Regenerated.
1499 * i386-tbl.h: Likewise.
1500
75c0a438
L		 15012018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1502
1503 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1504 AddrPrefixOpReg.
1505 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1506 (AddrPrefixOpReg): This.
1507 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1508 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1509
2ceb7719
PB		 15102018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1511
1512 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1513 (vle_num_opcodes): Likewise.
1514 (spe2_num_opcodes): Likewise.
1515 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1516 initialization loop.
1517 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1518 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1519 only once.
1520
b3ac5c6c
TC		 15212018-05-01 Tamar Christina <tamar.christina@arm.com>
1522
1523 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1524
fe944acf
FT		 15252018-04-30 Francois H. Theron <francois.theron@netronome.com>
1526
1527 Makefile.am: Added nfp-dis.c.
1528 configure.ac: Added bfd_nfp_arch.
1529 disassemble.h: Added print_insn_nfp prototype.
1530 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1531 nfp-dis.c: New, for NFP support.
1532 po/POTFILES.in: Added nfp-dis.c to the list.
1533 Makefile.in: Regenerate.
1534 configure: Regenerate.
1535
e2195274
JB		 15362018-04-26 Jan Beulich <jbeulich@suse.com>
1537
1538 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1539 templates into their base ones.
1540 * i386-tlb.h: Re-generate.
1541
59ef5df4
JB		 15422018-04-26 Jan Beulich <jbeulich@suse.com>
1543
1544 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1545 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1546 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1547 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1548 * i386-init.h: Re-generate.
1549
6e041cf4
JB		 15502018-04-26 Jan Beulich <jbeulich@suse.com>
1551
1552 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1553 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1554 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1555 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1556 comment.
1557 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1558 and CpuRegMask.
1559 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1560 CpuRegMask: Delete.
1561 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1562 cpuregzmm, and cpuregmask.
1563 * i386-init.h: Re-generate.
1564 * i386-tbl.h: Re-generate.
1565
0e0eea78
JB		 15662018-04-26 Jan Beulich <jbeulich@suse.com>
1567
1568 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1569 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1570 * i386-init.h: Re-generate.
1571
2f1bada2
JB		 15722018-04-26 Jan Beulich <jbeulich@suse.com>
1573
1574 * i386-gen.c (VexImmExt): Delete.
1575 * i386-opc.h (VexImmExt, veximmext): Delete.
1576 * i386-opc.tbl: Drop all VexImmExt uses.
1577 * i386-tlb.h: Re-generate.
1578
bacd1457
JB		 15792018-04-25 Jan Beulich <jbeulich@suse.com>
1580
1581 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1582 register-only forms.
1583 * i386-tlb.h: Re-generate.
1584
10bba94b
TC		 15852018-04-25 Tamar Christina <tamar.christina@arm.com>
1586
1587 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1588
c48935d7
IT		 15892018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1590
1591 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1592 PREFIX_0F1C.
1593 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1594 (cpu_flags): Add CpuCLDEMOTE.
1595 * i386-init.h: Regenerate.
1596 * i386-opc.h (enum): Add CpuCLDEMOTE,
1597 (i386_cpu_flags): Add cpucldemote.
1598 * i386-opc.tbl: Add cldemote.
1599 * i386-tbl.h: Regenerate.
1600
211dc24b
AM		 16012018-04-16 Alan Modra <amodra@gmail.com>
1602
1603 * Makefile.am: Remove sh5 and sh64 support.
1604 * configure.ac: Likewise.
1605 * disassemble.c: Likewise.
1606 * disassemble.h: Likewise.
1607 * sh-dis.c: Likewise.
1608 * sh64-dis.c: Delete.
1609 * sh64-opc.c: Delete.
1610 * sh64-opc.h: Delete.
1611 * Makefile.in: Regenerate.
1612 * configure: Regenerate.
1613 * po/POTFILES.in: Regenerate.
1614
a9a4b302
AM		 16152018-04-16 Alan Modra <amodra@gmail.com>
1616
1617 * Makefile.am: Remove w65 support.
1618 * configure.ac: Likewise.
1619 * disassemble.c: Likewise.
1620 * disassemble.h: Likewise.
1621 * w65-dis.c: Delete.
1622 * w65-opc.h: Delete.
1623 * Makefile.in: Regenerate.
1624 * configure: Regenerate.
1625 * po/POTFILES.in: Regenerate.
1626
04cb01fd
AM		 16272018-04-16 Alan Modra <amodra@gmail.com>
1628
1629 * configure.ac: Remove we32k support.
1630 * configure: Regenerate.
1631
c2bf1eec
AM		 16322018-04-16 Alan Modra <amodra@gmail.com>
1633
1634 * Makefile.am: Remove m88k support.
1635 * configure.ac: Likewise.
1636 * disassemble.c: Likewise.
1637 * disassemble.h: Likewise.
1638 * m88k-dis.c: Delete.
1639 * Makefile.in: Regenerate.
1640 * configure: Regenerate.
1641 * po/POTFILES.in: Regenerate.
1642
6793974d
AM		 16432018-04-16 Alan Modra <amodra@gmail.com>
1644
1645 * Makefile.am: Remove i370 support.
1646 * configure.ac: Likewise.
1647 * disassemble.c: Likewise.
1648 * disassemble.h: Likewise.
1649 * i370-dis.c: Delete.
1650 * i370-opc.c: Delete.
1651 * Makefile.in: Regenerate.
1652 * configure: Regenerate.
1653 * po/POTFILES.in: Regenerate.
1654
e82aa794
AM		 16552018-04-16 Alan Modra <amodra@gmail.com>
1656
1657 * Makefile.am: Remove h8500 support.
1658 * configure.ac: Likewise.
1659 * disassemble.c: Likewise.
1660 * disassemble.h: Likewise.
1661 * h8500-dis.c: Delete.
1662 * h8500-opc.h: Delete.
1663 * Makefile.in: Regenerate.
1664 * configure: Regenerate.
1665 * po/POTFILES.in: Regenerate.
1666
fceadf09
AM		 16672018-04-16 Alan Modra <amodra@gmail.com>
1668
1669 * configure.ac: Remove tahoe support.
1670 * configure: Regenerate.
1671
ae1d3843
L		 16722018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1673
1674 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1675 umwait.
1676 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1677 64-bit mode.
1678 * i386-tbl.h: Regenerated.
1679
de89d0a3
IT		 16802018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1681
1682 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1683 PREFIX_MOD_1_0FAE_REG_6.
1684 (va_mode): New.
1685 (OP_E_register): Use va_mode.
1686 * i386-dis-evex.h (prefix_table):
1687 New instructions (see prefixes above).
1688 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1689 (cpu_flags): Likewise.
1690 * i386-opc.h (enum): Likewise.
1691 (i386_cpu_flags): Likewise.
1692 * i386-opc.tbl: Add umonitor, umwait, tpause.
1693 * i386-init.h: Regenerate.
1694 * i386-tbl.h: Likewise.
1695
a8eb42a8
AM		 16962018-04-11 Alan Modra <amodra@gmail.com>
1697
1698 * opcodes/i860-dis.c: Delete.
1699 * opcodes/i960-dis.c: Delete.
1700 * Makefile.am: Remove i860 and i960 support.
1701 * configure.ac: Likewise.
1702 * disassemble.c: Likewise.
1703 * disassemble.h: Likewise.
1704 * Makefile.in: Regenerate.
1705 * configure: Regenerate.
1706 * po/POTFILES.in: Regenerate.
1707
caf0678c
L		 17082018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1709
1710 PR binutils/23025
1711 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1712 to 0.
1713 (print_insn): Clear vex instead of vex.evex.
1714
4fb0d2b9
NC		 17152018-04-04 Nick Clifton <nickc@redhat.com>
1716
1717 * po/es.po: Updated Spanish translation.
1718
c39e5b26
JB		 17192018-03-28 Jan Beulich <jbeulich@suse.com>
1720
1721 * i386-gen.c (opcode_modifiers): Delete VecESize.
1722 * i386-opc.h (VecESize): Delete.
1723 (struct i386_opcode_modifier): Delete vecesize.
1724 * i386-opc.tbl: Drop VecESize.
1725 * i386-tlb.h: Re-generate.
1726
8e6e0792
JB		 17272018-03-28 Jan Beulich <jbeulich@suse.com>
1728
1729 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1730 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1731 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1732 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1733 * i386-tlb.h: Re-generate.
1734
9f123b91
JB		 17352018-03-28 Jan Beulich <jbeulich@suse.com>
1736
1737 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1738 Fold AVX512 forms
1739 * i386-tlb.h: Re-generate.
1740
9646c87b
JB		 17412018-03-28 Jan Beulich <jbeulich@suse.com>
1742
1743 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1744 (vex_len_table): Drop Y for vcvt*2si.
1745 (putop): Replace plain 'Y' handling by abort().
1746
c8d59609
NC		 17472018-03-28 Nick Clifton <nickc@redhat.com>
1748
1749 PR 22988
1750 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1751 instructions with only a base address register.
1752 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1753 handle AARHC64_OPND_SVE_ADDR_R.
1754 (aarch64_print_operand): Likewise.
1755 * aarch64-asm-2.c: Regenerate.
1756 * aarch64_dis-2.c: Regenerate.
1757 * aarch64-opc-2.c: Regenerate.
1758
b8c169f3
JB		 17592018-03-22 Jan Beulich <jbeulich@suse.com>
1760
1761 * i386-opc.tbl: Drop VecESize from register only insn forms and
1762 memory forms not allowing broadcast.
1763 * i386-tlb.h: Re-generate.
1764
96bc132a
JB		 17652018-03-22 Jan Beulich <jbeulich@suse.com>
1766
1767 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1768 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1769 sha256*): Drop Disp<N>.
1770
9f79e886
JB		 17712018-03-22 Jan Beulich <jbeulich@suse.com>
1772
1773 * i386-dis.c (EbndS, bnd_swap_mode): New.
1774 (prefix_table): Use EbndS.
1775 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1776 * i386-opc.tbl (bndmov): Move misplaced Load.
1777 * i386-tlb.h: Re-generate.
1778
d6793fa1
JB		 17792018-03-22 Jan Beulich <jbeulich@suse.com>
1780
1781 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1782 templates allowing memory operands and folded ones for register
1783 only flavors.
1784 * i386-tlb.h: Re-generate.
1785
f7768225
JB		 17862018-03-22 Jan Beulich <jbeulich@suse.com>
1787
1788 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1789 256-bit templates. Drop redundant leftover Disp<N>.
1790 * i386-tlb.h: Re-generate.
1791
0e35537d
JW		 17922018-03-14 Kito Cheng <kito.cheng@gmail.com>
1793
1794 * riscv-opc.c (riscv_insn_types): New.
1795
b4a3689a
NC		 17962018-03-13 Nick Clifton <nickc@redhat.com>
1797
1798 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1799
d3d50934
L		 18002018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1801
1802 * i386-opc.tbl: Add Optimize to clr.
1803 * i386-tbl.h: Regenerated.
1804
bd5dea88
L		 18052018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1806
1807 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1808 * i386-opc.h (OldGcc): Removed.
1809 (i386_opcode_modifier): Remove oldgcc.
1810 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1811 instructions for old (<= 2.8.1) versions of gcc.
1812 * i386-tbl.h: Regenerated.
1813
e771e7c9
JB		 18142018-03-08 Jan Beulich <jbeulich@suse.com>
1815
1816 * i386-opc.h (EVEXDYN): New.
1817 * i386-opc.tbl: Fold various AVX512VL templates.
1818 * i386-tlb.h: Re-generate.
1819
ed438a93
JB		 18202018-03-08 Jan Beulich <jbeulich@suse.com>
1821
1822 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1823 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1824 vpexpandd, vpexpandq): Fold AFX512VF templates.
1825 * i386-tlb.h: Re-generate.
1826
454172a9
JB		 18272018-03-08 Jan Beulich <jbeulich@suse.com>
1828
1829 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1830 Fold 128- and 256-bit VEX-encoded templates.
1831 * i386-tlb.h: Re-generate.
1832
36824150
JB		 18332018-03-08 Jan Beulich <jbeulich@suse.com>
1834
1835 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1836 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1837 vpexpandd, vpexpandq): Fold AVX512F templates.
1838 * i386-tlb.h: Re-generate.
1839
e7f5c0a9
JB		 18402018-03-08 Jan Beulich <jbeulich@suse.com>
1841
1842 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1843 64-bit templates. Drop Disp<N>.
1844 * i386-tlb.h: Re-generate.
1845
25a4277f
JB		 18462018-03-08 Jan Beulich <jbeulich@suse.com>
1847
1848 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1849 and 256-bit templates.
1850 * i386-tlb.h: Re-generate.
1851
d2224064
JB		 18522018-03-08 Jan Beulich <jbeulich@suse.com>
1853
1854 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1855 * i386-tlb.h: Re-generate.
1856
1b193f0b
JB		 18572018-03-08 Jan Beulich <jbeulich@suse.com>
1858
1859 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1860 Drop NoAVX.
1861 * i386-tlb.h: Re-generate.
1862
f2f6a710
JB		 18632018-03-08 Jan Beulich <jbeulich@suse.com>
1864
1865 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1866 * i386-tlb.h: Re-generate.
1867
38e314eb
JB		 18682018-03-08 Jan Beulich <jbeulich@suse.com>
1869
1870 * i386-gen.c (opcode_modifiers): Delete FloatD.
1871 * i386-opc.h (FloatD): Delete.
1872 (struct i386_opcode_modifier): Delete floatd.
1873 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1874 FloatD by D.
1875 * i386-tlb.h: Re-generate.
1876
d53e6b98
JB		 18772018-03-08 Jan Beulich <jbeulich@suse.com>
1878
1879 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1880
2907c2f5
JB		 18812018-03-08 Jan Beulich <jbeulich@suse.com>
1882
1883 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1884 * i386-tlb.h: Re-generate.
1885
73053c1f
JB		 18862018-03-08 Jan Beulich <jbeulich@suse.com>
1887
1888 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1889 forms.
1890 * i386-tlb.h: Re-generate.
1891
52fe4420
AM		 18922018-03-07 Alan Modra <amodra@gmail.com>
1893
1894 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1895 bfd_arch_rs6000.
1896 * disassemble.h (print_insn_rs6000): Delete.
1897 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1898 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1899 (print_insn_rs6000): Delete.
1900
a6743a54
AM		 19012018-03-03 Alan Modra <amodra@gmail.com>
1902
1903 * sysdep.h (opcodes_error_handler): Define.
1904 (_bfd_error_handler): Declare.
1905 * Makefile.am: Remove stray #.
1906 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1907 EDIT" comment.
1908 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1909 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1910 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1911 opcodes_error_handler to print errors. Standardize error messages.
1912 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1913 and include opintl.h.
1914 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1915 * i386-gen.c: Standardize error messages.
1916 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1917 * Makefile.in: Regenerate.
1918 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1919 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1920 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1921 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1922 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1923 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1924 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1925 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1926 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1927 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1928 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1929 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1930 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1931
8305403a
L		 19322018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1933
1934 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1935 vpsub[bwdq] instructions.
1936 * i386-tbl.h: Regenerated.
1937
e184813f
AM		 19382018-03-01 Alan Modra <amodra@gmail.com>
1939
1940 * configure.ac (ALL_LINGUAS): Sort.
1941 * configure: Regenerate.
1942
5b616bef
TP		 19432018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1944
1945 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1946 macro by assignements.
1947
b6f8c7c4
L		 19482018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1949
1950 PR gas/22871
1951 * i386-gen.c (opcode_modifiers): Add Optimize.
1952 * i386-opc.h (Optimize): New enum.
1953 (i386_opcode_modifier): Add optimize.
1954 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1955 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1956 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1957 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1958 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1959 vpxord and vpxorq.
1960 * i386-tbl.h: Regenerated.
1961
e95b887f
AM		 19622018-02-26 Alan Modra <amodra@gmail.com>
1963
1964 * crx-dis.c (getregliststring): Allocate a large enough buffer
1965 to silence false positive gcc8 warning.
1966
0bccfb29
JW		 19672018-02-22 Shea Levy <shea@shealevy.com>
1968
1969 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1970
6b6b6807
L		 19712018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1972
1973 * i386-opc.tbl: Add {rex},
1974 * i386-tbl.h: Regenerated.
1975
75f31665
MR		 19762018-02-20 Maciej W. Rozycki <macro@mips.com>
1977
1978 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1979 (mips16_opcodes): Replace `M' with `m' for "restore".
1980
e207bc53
TP		 19812018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1982
1983 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1984
87993319
MR		 19852018-02-13 Maciej W. Rozycki <macro@mips.com>
1986
1987 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1988 variable to `function_index'.
1989
68d20676
NC		 19902018-02-13 Nick Clifton <nickc@redhat.com>
1991
1992 PR 22823
1993 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1994 about truncation of printing.
1995
d2159fdc
HW		 19962018-02-12 Henry Wong <henry@stuffedcow.net>
1997
1998 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1999
f174ef9f
NC		 20002018-02-05 Nick Clifton <nickc@redhat.com>
2001
2002 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2003
be3a8dca
IT		 20042018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2005
2006 * i386-dis.c (enum): Add pconfig.
2007 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2008 (cpu_flags): Add CpuPCONFIG.
2009 * i386-opc.h (enum): Add CpuPCONFIG.
2010 (i386_cpu_flags): Add cpupconfig.
2011 * i386-opc.tbl: Add PCONFIG instruction.
2012 * i386-init.h: Regenerate.
2013 * i386-tbl.h: Likewise.
2014
3233d7d0
IT		 20152018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2016
2017 * i386-dis.c (enum): Add PREFIX_0F09.
2018 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2019 (cpu_flags): Add CpuWBNOINVD.
2020 * i386-opc.h (enum): Add CpuWBNOINVD.
2021 (i386_cpu_flags): Add cpuwbnoinvd.
2022 * i386-opc.tbl: Add WBNOINVD instruction.
2023 * i386-init.h: Regenerate.
2024 * i386-tbl.h: Likewise.
2025
e925c834
JW		 20262018-01-17 Jim Wilson <jimw@sifive.com>
2027
2028 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2029
d777820b
IT		 20302018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2031
2032 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2033 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2034 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2035 (cpu_flags): Add CpuIBT, CpuSHSTK.
2036 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2037 (i386_cpu_flags): Add cpuibt, cpushstk.
2038 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2039 * i386-init.h: Regenerate.
2040 * i386-tbl.h: Likewise.
2041
f6efed01
NC		 20422018-01-16 Nick Clifton <nickc@redhat.com>
2043
2044 * po/pt_BR.po: Updated Brazilian Portugese translation.
2045 * po/de.po: Updated German translation.
2046
2721d702
JW		 20472018-01-15 Jim Wilson <jimw@sifive.com>
2048
2049 * riscv-opc.c (match_c_nop): New.
2050 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2051
616dcb87
NC		 20522018-01-15 Nick Clifton <nickc@redhat.com>
2053
2054 * po/uk.po: Updated Ukranian translation.
2055
3957a496
NC		 20562018-01-13 Nick Clifton <nickc@redhat.com>
2057
2058 * po/opcodes.pot: Regenerated.
2059
769c7ea5
NC		 20602018-01-13 Nick Clifton <nickc@redhat.com>
2061
2062 * configure: Regenerate.
2063
faf766e3
NC		 20642018-01-13 Nick Clifton <nickc@redhat.com>
2065
2066 2.30 branch created.
2067
888a89da
IT		 20682018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2069
2070 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2071 * i386-tbl.h: Regenerate.
2072
cbda583a
JB		 20732018-01-10 Jan Beulich <jbeulich@suse.com>
2074
2075 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2076 * i386-tbl.h: Re-generate.
2077
c9e92278
JB		 20782018-01-10 Jan Beulich <jbeulich@suse.com>
2079
2080 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2081 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2082 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2083 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2084 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2085 Disp8MemShift of AVX512VL forms.
2086 * i386-tbl.h: Re-generate.
2087
35fd2b2b
JW		 20882018-01-09 Jim Wilson <jimw@sifive.com>
2089
2090 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2091 then the hi_addr value is zero.
2092
91d8b670
JG		 20932018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2094
2095 * arm-dis.c (arm_opcodes): Add csdb.
2096 (thumb32_opcodes): Add csdb.
2097
be2e7d95
JG		 20982018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2099
2100 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2101 * aarch64-asm-2.c: Regenerate.
2102 * aarch64-dis-2.c: Regenerate.
2103 * aarch64-opc-2.c: Regenerate.
2104
704a705d
L		 21052018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2106
2107 PR gas/22681
2108 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2109 Remove AVX512 vmovd with 64-bit operands.
2110 * i386-tbl.h: Regenerated.
2111
35eeb78f
JW		 21122018-01-05 Jim Wilson <jimw@sifive.com>
2113
2114 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2115 jalr.
2116
219d1afa
AM		 21172018-01-03 Alan Modra <amodra@gmail.com>
2118
2119 Update year range in copyright notice of all files.
2120
1508bbf5
JB		 21212018-01-02 Jan Beulich <jbeulich@suse.com>
2122
2123 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2124 and OPERAND_TYPE_REGZMM entries.
2125
1e563868 2126For older changes see ChangeLog-2017
3499769a 2127\f
1e563868 2128Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2129
2130Copying and distribution of this file, with or without modification,
2131are permitted in any medium without royalty provided the copyright
2132notice and this notice are preserved.
2133
2134Local Variables:
2135mode: change-log
2136left-margin: 8
2137fill-column: 74
2138version-control: never
2139End:
GDB Binutils - Deliverables
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