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[ARC] ISA alignment.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2b848ebd
CZ		 12016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc-ext-tbl.h (EXTINSN2OPF): Define.
4 (EXTINSN2OP): Use EXTINSN2OPF.
5 (bspeekm, bspop, modapp): New extension instructions.
6 * arc-opc.c (F_DNZ_ND): Define.
7 (F_DNZ_D): Likewise.
8 (F_SIZEB1): Changed.
9 (C_DNZ_D): Define.
10 (C_HARD): Changed.
11 * arc-tbl.h (dbnz): New instruction.
12 (prealloc): Allow it for ARC EM.
13 (xbfu): Likewise.
14
ad43e107
RS		 152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
16
17 * aarch64-opc.c (print_immediate_offset_address): Print spaces
18 after commas in addresses.
19 (aarch64_print_operand): Likewise.
20
ab3b8fcf
RS		 212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
22
23 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
24 rather than "should be" or "expected to be" in error messages.
25
bb7eff52
RS		 262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
27
28 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
29 (print_mnemonic_name): ...here.
30 (print_comment): New function.
31 (print_aarch64_insn): Call it.
32 * aarch64-opc.c (aarch64_conds): Add SVE names.
33 (aarch64_print_operand): Print alternative condition names in
34 a comment.
35
c0890d26
RS		 362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
37
38 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
39 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
40 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
41 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
42 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
43 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
44 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
45 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
46 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
47 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
48 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
49 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
50 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
51 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
52 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
53 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
54 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
55 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
56 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
57 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
58 (OP_SVE_XWU, OP_SVE_XXU): New macros.
59 (aarch64_feature_sve): New variable.
60 (SVE): New macro.
61 (_SVE_INSN): Likewise.
62 (aarch64_opcode_table): Add SVE instructions.
63 * aarch64-opc.h (extract_fields): Declare.
64 * aarch64-opc-2.c: Regenerate.
65 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
66 * aarch64-asm-2.c: Regenerate.
67 * aarch64-dis.c (extract_fields): Make global.
68 (do_misc_decoding): Handle the new SVE aarch64_ops.
69 * aarch64-dis-2.c: Regenerate.
70
116b6019
RS		 712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
72
73 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
74 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
75 aarch64_field_kinds.
76 * aarch64-opc.c (fields): Add corresponding entries.
77 * aarch64-asm.c (aarch64_get_variant): New function.
78 (aarch64_encode_variant_using_iclass): Likewise.
79 (aarch64_opcode_encode): Call it.
80 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
81 (aarch64_opcode_decode): Call it.
82
047cd301
RS		 832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
84
85 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
86 and FP register operands.
87 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
88 (FLD_SVE_Vn): New aarch64_field_kinds.
89 * aarch64-opc.c (fields): Add corresponding entries.
90 (aarch64_print_operand): Handle the new SVE core and FP register
91 operands.
92 * aarch64-opc-2.c: Regenerate.
93 * aarch64-asm-2.c: Likewise.
94 * aarch64-dis-2.c: Likewise.
95
165d4950
RS		 962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
97
98 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
99 immediate operands.
100 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
101 * aarch64-opc.c (fields): Add corresponding entry.
102 (operand_general_constraint_met_p): Handle the new SVE FP immediate
103 operands.
104 (aarch64_print_operand): Likewise.
105 * aarch64-opc-2.c: Regenerate.
106 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
107 (ins_sve_float_zero_one): New inserters.
108 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
109 (aarch64_ins_sve_float_half_two): Likewise.
110 (aarch64_ins_sve_float_zero_one): Likewise.
111 * aarch64-asm-2.c: Regenerate.
112 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
113 (ext_sve_float_zero_one): New extractors.
114 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
115 (aarch64_ext_sve_float_half_two): Likewise.
116 (aarch64_ext_sve_float_zero_one): Likewise.
117 * aarch64-dis-2.c: Regenerate.
118
e950b345
RS		 1192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
120
121 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
122 integer immediate operands.
123 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
124 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
125 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
126 * aarch64-opc.c (fields): Add corresponding entries.
127 (operand_general_constraint_met_p): Handle the new SVE integer
128 immediate operands.
129 (aarch64_print_operand): Likewise.
130 (aarch64_sve_dupm_mov_immediate_p): New function.
131 * aarch64-opc-2.c: Regenerate.
132 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
133 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
134 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
135 (aarch64_ins_limm): ...here.
136 (aarch64_ins_inv_limm): New function.
137 (aarch64_ins_sve_aimm): Likewise.
138 (aarch64_ins_sve_asimm): Likewise.
139 (aarch64_ins_sve_limm_mov): Likewise.
140 (aarch64_ins_sve_shlimm): Likewise.
141 (aarch64_ins_sve_shrimm): Likewise.
142 * aarch64-asm-2.c: Regenerate.
143 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
144 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
145 * aarch64-dis.c (decode_limm): New function, split out from...
146 (aarch64_ext_limm): ...here.
147 (aarch64_ext_inv_limm): New function.
148 (decode_sve_aimm): Likewise.
149 (aarch64_ext_sve_aimm): Likewise.
150 (aarch64_ext_sve_asimm): Likewise.
151 (aarch64_ext_sve_limm_mov): Likewise.
152 (aarch64_top_bit): Likewise.
153 (aarch64_ext_sve_shlimm): Likewise.
154 (aarch64_ext_sve_shrimm): Likewise.
155 * aarch64-dis-2.c: Regenerate.
156
98907a70
RS		 1572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
158
159 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
160 operands.
161 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
162 the AARCH64_MOD_MUL_VL entry.
163 (value_aligned_p): Cope with non-power-of-two alignments.
164 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
165 (print_immediate_offset_address): Likewise.
166 (aarch64_print_operand): Likewise.
167 * aarch64-opc-2.c: Regenerate.
168 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
169 (ins_sve_addr_ri_s9xvl): New inserters.
170 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
171 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
172 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
173 * aarch64-asm-2.c: Regenerate.
174 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
175 (ext_sve_addr_ri_s9xvl): New extractors.
176 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
177 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
178 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
179 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
180 * aarch64-dis-2.c: Regenerate.
181
4df068de
RS		 1822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
183
184 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
185 address operands.
186 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
187 (FLD_SVE_xs_22): New aarch64_field_kinds.
188 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
189 (get_operand_specific_data): New function.
190 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
191 FLD_SVE_xs_14 and FLD_SVE_xs_22.
192 (operand_general_constraint_met_p): Handle the new SVE address
193 operands.
194 (sve_reg): New array.
195 (get_addr_sve_reg_name): New function.
196 (aarch64_print_operand): Handle the new SVE address operands.
197 * aarch64-opc-2.c: Regenerate.
198 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
199 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
200 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
201 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
202 (aarch64_ins_sve_addr_rr_lsl): Likewise.
203 (aarch64_ins_sve_addr_rz_xtw): Likewise.
204 (aarch64_ins_sve_addr_zi_u5): Likewise.
205 (aarch64_ins_sve_addr_zz): Likewise.
206 (aarch64_ins_sve_addr_zz_lsl): Likewise.
207 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
208 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
209 * aarch64-asm-2.c: Regenerate.
210 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
211 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
212 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
213 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
214 (aarch64_ext_sve_addr_ri_u6): Likewise.
215 (aarch64_ext_sve_addr_rr_lsl): Likewise.
216 (aarch64_ext_sve_addr_rz_xtw): Likewise.
217 (aarch64_ext_sve_addr_zi_u5): Likewise.
218 (aarch64_ext_sve_addr_zz): Likewise.
219 (aarch64_ext_sve_addr_zz_lsl): Likewise.
220 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
221 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
222 * aarch64-dis-2.c: Regenerate.
223
2442d846
RS		 2242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
225
226 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
227 AARCH64_OPND_SVE_PATTERN_SCALED.
228 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
229 * aarch64-opc.c (fields): Add a corresponding entry.
230 (set_multiplier_out_of_range_error): New function.
231 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
232 (operand_general_constraint_met_p): Handle
233 AARCH64_OPND_SVE_PATTERN_SCALED.
234 (print_register_offset_address): Use PRIi64 to print the
235 shift amount.
236 (aarch64_print_operand): Likewise. Handle
237 AARCH64_OPND_SVE_PATTERN_SCALED.
238 * aarch64-opc-2.c: Regenerate.
239 * aarch64-asm.h (ins_sve_scale): New inserter.
240 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
241 * aarch64-asm-2.c: Regenerate.
242 * aarch64-dis.h (ext_sve_scale): New inserter.
243 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
244 * aarch64-dis-2.c: Regenerate.
245
245d2e3f
RS		 2462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
247
248 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
249 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
250 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
251 (FLD_SVE_prfop): Likewise.
252 * aarch64-opc.c: Include libiberty.h.
253 (aarch64_sve_pattern_array): New variable.
254 (aarch64_sve_prfop_array): Likewise.
255 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
256 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
257 AARCH64_OPND_SVE_PRFOP.
258 * aarch64-asm-2.c: Regenerate.
259 * aarch64-dis-2.c: Likewise.
260 * aarch64-opc-2.c: Likewise.
261
d50c751e
RS		 2622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
263
264 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
265 AARCH64_OPND_QLF_P_[ZM].
266 (aarch64_print_operand): Print /z and /m where appropriate.
267
f11ad6bc
RS		 2682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
269
270 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
271 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
272 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
273 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
274 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
275 * aarch64-opc.c (fields): Add corresponding entries here.
276 (operand_general_constraint_met_p): Check that SVE register lists
277 have the correct length. Check the ranges of SVE index registers.
278 Check for cases where p8-p15 are used in 3-bit predicate fields.
279 (aarch64_print_operand): Handle the new SVE operands.
280 * aarch64-opc-2.c: Regenerate.
281 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
282 * aarch64-asm.c (aarch64_ins_sve_index): New function.
283 (aarch64_ins_sve_reglist): Likewise.
284 * aarch64-asm-2.c: Regenerate.
285 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
286 * aarch64-dis.c (aarch64_ext_sve_index): New function.
287 (aarch64_ext_sve_reglist): Likewise.
288 * aarch64-dis-2.c: Regenerate.
289
0c608d6b
RS		 2902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
291
292 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
293 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
294 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
295 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
296 tied operands.
297
01dbfe4c
RS		 2982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
299
300 * aarch64-opc.c (get_offset_int_reg_name): New function.
301 (print_immediate_offset_address): Likewise.
302 (print_register_offset_address): Take the base and offset
303 registers as parameters.
304 (aarch64_print_operand): Update caller accordingly. Use
305 print_immediate_offset_address.
306
72e9f319
RS		 3072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
308
309 * aarch64-opc.c (BANK): New macro.
310 (R32, R64): Take a register number as argument
311 (int_reg): Use BANK.
312
8a7f0c1b
RS		 3132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
314
315 * aarch64-opc.c (print_register_list): Add a prefix parameter.
316 (aarch64_print_operand): Update accordingly.
317
aa2aa4c6
RS		 3182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
319
320 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
321 for FPIMM.
322 * aarch64-asm.h (ins_fpimm): New inserter.
323 * aarch64-asm.c (aarch64_ins_fpimm): New function.
324 * aarch64-asm-2.c: Regenerate.
325 * aarch64-dis.h (ext_fpimm): New extractor.
326 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
327 (aarch64_ext_fpimm): New function.
328 * aarch64-dis-2.c: Regenerate.
329
b5464a68
RS		 3302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
331
332 * aarch64-asm.c: Include libiberty.h.
333 (insert_fields): New function.
334 (aarch64_ins_imm): Use it.
335 * aarch64-dis.c (extract_fields): New function.
336 (aarch64_ext_imm): Use it.
337
42408347
RS		 3382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
339
340 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
341 with an esize parameter.
342 (operand_general_constraint_met_p): Update accordingly.
343 Fix misindented code.
344 * aarch64-asm.c (aarch64_ins_limm): Update call to
345 aarch64_logical_immediate_p.
346
4989adac
RS		 3472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
348
349 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
350
bd11d5d8
RS		 3512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
352
353 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
354
f807f43d
CZ		 3552016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
356
357 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
358
fd486b63
PB		 3592016-09-14 Peter Bergner <bergner@vnet.ibm.com>
360
361 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
362 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
363 xor3>: Delete mnemonics.
364 <cp_abort>: Rename mnemonic from ...
365 <cpabort>: ...to this.
366 <setb>: Change to a X form instruction.
367 <sync>: Change to 1 operand form.
368 <copy>: Delete mnemonic.
369 <copy_first>: Rename mnemonic from ...
370 <copy>: ...to this.
371 <paste, paste.>: Delete mnemonics.
372 <paste_last>: Rename mnemonic from ...
373 <paste.>: ...to this.
374
dce08442
AK		 3752016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
376
377 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
378
952c3f51
AK		 3792016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
380
381 * s390-mkopc.c (main): Support alternate arch strings.
382
8b71537b
PS		 3832016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
384
385 * s390-opc.txt: Fix kmctr instruction type.
386
5b64d091
L		 3872016-09-07 H.J. Lu <hongjiu.lu@intel.com>
388
389 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
390 * i386-init.h: Regenerated.
391
7763838e
CM		 3922016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
393
394 * opcodes/arc-dis.c (print_insn_arc): Changed.
395
1b8b6532
JM		 3962016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
397
398 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
399 camellia_fl.
400
1a336194
TP		 4012016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
402
403 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
404 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
405 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
406
6b40c462
L		 4072016-08-24 H.J. Lu <hongjiu.lu@intel.com>
408
409 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
410 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
411 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
412 PREFIX_MOD_3_0FAE_REG_4.
413 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
414 PREFIX_MOD_3_0FAE_REG_4.
415 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
416 (cpu_flags): Add CpuPTWRITE.
417 * i386-opc.h (CpuPTWRITE): New.
418 (i386_cpu_flags): Add cpuptwrite.
419 * i386-opc.tbl: Add ptwrite instruction.
420 * i386-init.h: Regenerated.
421 * i386-tbl.h: Likewise.
422
ab548d2d
AK		 4232016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
424
425 * arc-dis.h: Wrap around in extern "C".
426
344bde0a
RS		 4272016-08-23 Richard Sandiford <richard.sandiford@arm.com>
428
429 * aarch64-tbl.h (V8_2_INSN): New macro.
430 (aarch64_opcode_table): Use it.
431
5ce912d8
RS		 4322016-08-23 Richard Sandiford <richard.sandiford@arm.com>
433
434 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
435 CORE_INSN, __FP_INSN and SIMD_INSN.
436
9d30b0bd
RS		 4372016-08-23 Richard Sandiford <richard.sandiford@arm.com>
438
439 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
440 (aarch64_opcode_table): Update uses accordingly.
441
dfdaec14
AJ		 4422016-07-25 Andrew Jenner <andrew@codesourcery.com>
443 Kwok Cheung Yeung <kcy@codesourcery.com>
444
445 opcodes/
446 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
447 'e_cmplwi' to 'e_cmpli' instead.
448 (OPVUPRT, OPVUPRT_MASK): Define.
449 (powerpc_opcodes): Add E200Z4 insns.
450 (vle_opcodes): Add context save/restore insns.
451
7bd374a4
MR		 4522016-07-27 Maciej W. Rozycki <macro@imgtec.com>
453
454 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
455 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
456 "j".
457
db18dbab
GM		 4582016-07-27 Graham Markall <graham.markall@embecosm.com>
459
460 * arc-nps400-tbl.h: Change block comments to GNU format.
461 * arc-dis.c: Add new globals addrtypenames,
462 addrtypenames_max, and addtypeunknown.
463 (get_addrtype): New function.
464 (print_insn_arc): Print colons and address types when
465 required.
466 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
467 define insert and extract functions for all address types.
468 (arc_operands): Add operands for colon and all address
469 types.
470 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
471 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
472 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
473 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
474 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
475 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
476
fecd57f9
L		 4772016-07-21 H.J. Lu <hongjiu.lu@intel.com>
478
479 * configure: Regenerated.
480
37fd5ef3
CZ		 4812016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
482
483 * arc-dis.c (skipclass): New structure.
484 (decodelist): New variable.
485 (is_compatible_p): New function.
486 (new_element): Likewise.
487 (skip_class_p): Likewise.
488 (find_format_from_table): Use skip_class_p function.
489 (find_format): Decode first the extension instructions.
490 (print_insn_arc): Select either ARCEM or ARCHS based on elf
491 e_flags.
492 (parse_option): New function.
493 (parse_disassembler_options): Likewise.
494 (print_arc_disassembler_options): Likewise.
495 (print_insn_arc): Use parse_disassembler_options function. Proper
496 select ARCv2 cpu variant.
497 * disassemble.c (disassembler_usage): Add ARC disassembler
498 options.
499
92281a5b
MR		 5002016-07-13 Maciej W. Rozycki <macro@imgtec.com>
501
502 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
503 annotation from the "nal" entry and reorder it beyond "bltzal".
504
6e7ced37
JM		 5052016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
506
507 * sparc-opc.c (ldtxa): New macro.
508 (sparc_opcodes): Use the macro defined above to add entries for
509 the LDTXA instructions.
510 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
511 instruction.
512
2f831b9a 5132016-07-07 James Bowman <james.bowman@ftdichip.com>
514
515 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
516 and "jmpc".
517
c07315e0
JB		 5182016-07-01 Jan Beulich <jbeulich@suse.com>
519
520 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
521 (movzb): Adjust to cover all permitted suffixes.
522 (movzw): New.
523 * i386-tbl.h: Re-generate.
524
9243100a
JB		 5252016-07-01 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
528 (lgdt): Remove Tbyte from non-64-bit variant.
529 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
530 xsaves64, xsavec64): Remove Disp16.
531 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
532 Remove Disp32S from non-64-bit variants. Remove Disp16 from
533 64-bit variants.
534 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
535 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
536 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
537 64-bit variants.
538 * i386-tbl.h: Re-generate.
539
8325cc63
JB		 5402016-07-01 Jan Beulich <jbeulich@suse.com>
541
542 * i386-opc.tbl (xlat): Remove RepPrefixOk.
543 * i386-tbl.h: Re-generate.
544
838441e4
YQ		 5452016-06-30 Yao Qi <yao.qi@linaro.org>
546
547 * arm-dis.c (print_insn): Fix typo in comment.
548
dab26bf4
RS		 5492016-06-28 Richard Sandiford <richard.sandiford@arm.com>
550
551 * aarch64-opc.c (operand_general_constraint_met_p): Check the
552 range of ldst_elemlist operands.
553 (print_register_list): Use PRIi64 to print the index.
554 (aarch64_print_operand): Likewise.
555
5703197e
TS		 5562016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
557
558 * mcore-opc.h: Remove sentinal.
559 * mcore-dis.c (print_insn_mcore): Adjust.
560
ce440d63
GM		 5612016-06-23 Graham Markall <graham.markall@embecosm.com>
562
563 * arc-opc.c: Correct description of availability of NPS400
564 features.
565
6fd3a02d
PB		 5662016-06-22 Peter Bergner <bergner@vnet.ibm.com>
567
568 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
569 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
570 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
571 xor3>: New mnemonics.
572 <setb>: Change to a VX form instruction.
573 (insert_sh6): Add support for rldixor.
574 (extract_sh6): Likewise.
575
6b477896
TS		 5762016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
577
578 * arc-ext.h: Wrap in extern C.
579
bdd582db
GM		 5802016-06-21 Graham Markall <graham.markall@embecosm.com>
581
582 * arc-dis.c (arc_insn_length): Add comment on instruction length.
583 Use same method for determining instruction length on ARC700 and
584 NPS-400.
585 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
586 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
587 with the NPS400 subclass.
588 * arc-opc.c: Likewise.
589
96074adc
JM		 5902016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
591
592 * sparc-opc.c (rdasr): New macro.
593 (wrasr): Likewise.
594 (rdpr): Likewise.
595 (wrpr): Likewise.
596 (rdhpr): Likewise.
597 (wrhpr): Likewise.
598 (sparc_opcodes): Use the macros above to fix and expand the
599 definition of read/write instructions from/to
600 asr/privileged/hyperprivileged instructions.
601 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
602 %hva_mask_nz. Prefer softint_set and softint_clear over
603 set_softint and clear_softint.
604 (print_insn_sparc): Support %ver in Rd.
605
7a10c22f
JM		 6062016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
607
608 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
609 architecture according to the hardware capabilities they require.
610
4f26fb3a
JM		 6112016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
612
613 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
614 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
615 bfd_mach_sparc_v9{c,d,e,v,m}.
616 * sparc-opc.c (MASK_V9C): Define.
617 (MASK_V9D): Likewise.
618 (MASK_V9E): Likewise.
619 (MASK_V9V): Likewise.
620 (MASK_V9M): Likewise.
621 (v6): Add MASK_V9{C,D,E,V,M}.
622 (v6notlet): Likewise.
623 (v7): Likewise.
624 (v8): Likewise.
625 (v9): Likewise.
626 (v9andleon): Likewise.
627 (v9a): Likewise.
628 (v9b): Likewise.
629 (v9c): Define.
630 (v9d): Likewise.
631 (v9e): Likewise.
632 (v9v): Likewise.
633 (v9m): Likewise.
634 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
635
3ee6e4fb
NC		 6362016-06-15 Nick Clifton <nickc@redhat.com>
637
638 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
639 constants to match expected behaviour.
640 (nds32_parse_opcode): Likewise. Also for whitespace.
641
02f3be19
AB		 6422016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
643
644 * arc-opc.c (extract_rhv1): Extract value from insn.
645
6f9f37ed 6462016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 647
648 * arc-nps400-tbl.h: Add ldbit instruction.
649 * arc-opc.c: Add flag classes required for ldbit.
650
6f9f37ed 6512016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 652
653 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
654 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
655 support the above instructions.
656
6f9f37ed 6572016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 658
659 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
660 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
661 csma, cbba, zncv, and hofs.
662 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
663 support the above instructions.
664
6652016-06-06 Graham Markall <graham.markall@embecosm.com>
666
667 * arc-nps400-tbl.h: Add andab and orab instructions.
668
6692016-06-06 Graham Markall <graham.markall@embecosm.com>
670
671 * arc-nps400-tbl.h: Add addl-like instructions.
672
6732016-06-06 Graham Markall <graham.markall@embecosm.com>
674
675 * arc-nps400-tbl.h: Add mxb and imxb instructions.
676
6772016-06-06 Graham Markall <graham.markall@embecosm.com>
678
679 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
680 instructions.
681
b2cc3f6f
AK		 6822016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
683
684 * s390-dis.c (option_use_insn_len_bits_p): New file scope
685 variable.
686 (init_disasm): Handle new command line option "insnlength".
687 (print_s390_disassembler_options): Mention new option in help
688 output.
689 (print_insn_s390): Use the encoded insn length when dumping
690 unknown instructions.
691
1857fe72
DC		 6922016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
693
694 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
695 to the address and set as symbol address for LDS/ STS immediate operands.
696
14b57c7c
AM		 6972016-06-07 Alan Modra <amodra@gmail.com>
698
699 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
700 cpu for "vle" to e500.
701 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
702 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
703 (PPCNONE): Delete, substitute throughout.
704 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
705 except for major opcode 4 and 31.
706 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
707
4d1464f2
MW		 7082016-06-07 Matthew Wahab <matthew.wahab@arm.com>
709
710 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
711 ARM_EXT_RAS in relevant entries.
712
026122a6
PB		 7132016-06-03 Peter Bergner <bergner@vnet.ibm.com>
714
715 PR binutils/20196
716 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
717 opcodes for E6500.
718
07f5af7d
L		 7192016-06-03 H.J. Lu <hongjiu.lu@intel.com>
720
721 PR binutis/18386
722 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
723 (indir_v_mode): New.
724 Add comments for '&'.
725 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
726 (putop): Handle '&'.
727 (intel_operand_size): Handle indir_v_mode.
728 (OP_E_register): Likewise.
729 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
730 64-bit indirect call/jmp for AMD64.
731 * i386-tbl.h: Regenerated
732
4eb6f892
AB		 7332016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
734
735 * arc-dis.c (struct arc_operand_iterator): New structure.
736 (find_format_from_table): All the old content from find_format,
737 with some minor adjustments, and parameter renaming.
738 (find_format_long_instructions): New function.
739 (find_format): Rewritten.
740 (arc_insn_length): Add LSB parameter.
741 (extract_operand_value): New function.
742 (operand_iterator_next): New function.
743 (print_insn_arc): Use new functions to find opcode, and iterator
744 over operands.
745 * arc-opc.c (insert_nps_3bit_dst_short): New function.
746 (extract_nps_3bit_dst_short): New function.
747 (insert_nps_3bit_src2_short): New function.
748 (extract_nps_3bit_src2_short): New function.
749 (insert_nps_bitop1_size): New function.
750 (extract_nps_bitop1_size): New function.
751 (insert_nps_bitop2_size): New function.
752 (extract_nps_bitop2_size): New function.
753 (insert_nps_bitop_mod4_msb): New function.
754 (extract_nps_bitop_mod4_msb): New function.
755 (insert_nps_bitop_mod4_lsb): New function.
756 (extract_nps_bitop_mod4_lsb): New function.
757 (insert_nps_bitop_dst_pos3_pos4): New function.
758 (extract_nps_bitop_dst_pos3_pos4): New function.
759 (insert_nps_bitop_ins_ext): New function.
760 (extract_nps_bitop_ins_ext): New function.
761 (arc_operands): Add new operands.
762 (arc_long_opcodes): New global array.
763 (arc_num_long_opcodes): New global.
764 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
765
1fe0971e
TS		 7662016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
767
768 * nds32-asm.h: Add extern "C".
769 * sh-opc.h: Likewise.
770
315f180f
GM		 7712016-06-01 Graham Markall <graham.markall@embecosm.com>
772
773 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
774 0,b,limm to the rflt instruction.
775
a2b5fccc
TS		 7762016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
777
778 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
779 constant.
780
0cbd0046
L		 7812016-05-29 H.J. Lu <hongjiu.lu@intel.com>
782
783 PR gas/20145
784 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
785 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
786 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
787 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
788 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
789 * i386-init.h: Regenerated.
790
1848e567
L		 7912016-05-27 H.J. Lu <hongjiu.lu@intel.com>
792
793 PR gas/20145
794 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
795 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
796 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
797 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
798 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
799 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
800 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
801 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
802 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
803 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
804 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
805 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
806 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
807 CpuRegMask for AVX512.
808 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
809 and CpuRegMask.
810 (set_bitfield_from_cpu_flag_init): New function.
811 (set_bitfield): Remove const on f. Call
812 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
813 * i386-opc.h (CpuRegMMX): New.
814 (CpuRegXMM): Likewise.
815 (CpuRegYMM): Likewise.
816 (CpuRegZMM): Likewise.
817 (CpuRegMask): Likewise.
818 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
819 and cpuregmask.
820 * i386-init.h: Regenerated.
821 * i386-tbl.h: Likewise.
822
e92bae62
L		 8232016-05-27 H.J. Lu <hongjiu.lu@intel.com>
824
825 PR gas/20154
826 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
827 (opcode_modifiers): Add AMD64 and Intel64.
828 (main): Properly verify CpuMax.
829 * i386-opc.h (CpuAMD64): Removed.
830 (CpuIntel64): Likewise.
831 (CpuMax): Set to CpuNo64.
832 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
833 (AMD64): New.
834 (Intel64): Likewise.
835 (i386_opcode_modifier): Add amd64 and intel64.
836 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
837 on call and jmp.
838 * i386-init.h: Regenerated.
839 * i386-tbl.h: Likewise.
840
e89c5eaa
L		 8412016-05-27 H.J. Lu <hongjiu.lu@intel.com>
842
843 PR gas/20154
844 * i386-gen.c (main): Fail if CpuMax is incorrect.
845 * i386-opc.h (CpuMax): Set to CpuIntel64.
846 * i386-tbl.h: Regenerated.
847
77d66e7b
NC		 8482016-05-27 Nick Clifton <nickc@redhat.com>
849
850 PR target/20150
851 * msp430-dis.c (msp430dis_read_two_bytes): New function.
852 (msp430dis_opcode_unsigned): New function.
853 (msp430dis_opcode_signed): New function.
854 (msp430_singleoperand): Use the new opcode reading functions.
855 Only disassenmble bytes if they were successfully read.
856 (msp430_doubleoperand): Likewise.
857 (msp430_branchinstr): Likewise.
858 (msp430x_callx_instr): Likewise.
859 (print_insn_msp430): Check that it is safe to read bytes before
860 attempting disassembly. Use the new opcode reading functions.
861
19dfcc89
PB		 8622016-05-26 Peter Bergner <bergner@vnet.ibm.com>
863
864 * ppc-opc.c (CY): New define. Document it.
865 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
866
f3ad7637
L		 8672016-05-25 H.J. Lu <hongjiu.lu@intel.com>
868
869 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
870 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
871 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
872 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
873 CPU_ANY_AVX_FLAGS.
874 * i386-init.h: Regenerated.
875
f1360d58
L		 8762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
877
878 PR gas/20141
879 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
880 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
881 * i386-init.h: Regenerated.
882
293f5f65
L		 8832016-05-25 H.J. Lu <hongjiu.lu@intel.com>
884
885 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
886 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
887 * i386-init.h: Regenerated.
888
d9eca1df
CZ		 8892016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
890
891 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
892 information.
893 (print_insn_arc): Set insn_type information.
894 * arc-opc.c (C_CC): Add F_CLASS_COND.
895 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
896 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
897 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
898 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
899 (brne, brne_s, jeq_s, jne_s): Likewise.
900
87789e08
CZ		 9012016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
902
903 * arc-tbl.h (neg): New instruction variant.
904
c810e0b8
CZ		 9052016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
906
907 * arc-dis.c (find_format, find_format, get_auxreg)
908 (print_insn_arc): Changed.
909 * arc-ext.h (INSERT_XOP): Likewise.
910
3d207518
TS		 9112016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
912
913 * tic54x-dis.c (sprint_mmr): Adjust.
914 * tic54x-opc.c: Likewise.
915
514e58b7
AM		 9162016-05-19 Alan Modra <amodra@gmail.com>
917
918 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
919
e43de63c
AM		 9202016-05-19 Alan Modra <amodra@gmail.com>
921
922 * ppc-opc.c: Formatting.
923 (NSISIGNOPT): Define.
924 (powerpc_opcodes <subis>): Use NSISIGNOPT.
925
1401d2fe
MR		 9262016-05-18 Maciej W. Rozycki <macro@imgtec.com>
927
928 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
929 replacing references to `micromips_ase' throughout.
930 (_print_insn_mips): Don't use file-level microMIPS annotation to
931 determine the disassembly mode with the symbol table.
932
1178da44
PB		 9332016-05-13 Peter Bergner <bergner@vnet.ibm.com>
934
935 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
936
8f4f9071
MF		 9372016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
938
939 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
940 mips64r6.
941 * mips-opc.c (D34): New macro.
942 (mips_builtin_opcodes): Define bposge32c for DSPr3.
943
8bc52696
AF		 9442016-05-10 Alexander Fomin <alexander.fomin@intel.com>
945
946 * i386-dis.c (prefix_table): Add RDPID instruction.
947 * i386-gen.c (cpu_flag_init): Add RDPID flag.
948 (cpu_flags): Add RDPID bitfield.
949 * i386-opc.h (enum): Add RDPID element.
950 (i386_cpu_flags): Add RDPID field.
951 * i386-opc.tbl: Add RDPID instruction.
952 * i386-init.h: Regenerate.
953 * i386-tbl.h: Regenerate.
954
39d911fc
TP		 9552016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
956
957 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
958 branch type of a symbol.
959 (print_insn): Likewise.
960
16a1fa25
TP		 9612016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
962
963 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
964 Mainline Security Extensions instructions.
965 (thumb_opcodes): Add entries for narrow ARMv8-M Security
966 Extensions instructions.
967 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
968 instructions.
969 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
970 special registers.
971
d751b79e
JM		 9722016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
973
974 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
975
945e0f82
CZ		 9762016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
977
978 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
979 (arcExtMap_genOpcode): Likewise.
980 * arc-opc.c (arg_32bit_rc): Define new variable.
981 (arg_32bit_u6): Likewise.
982 (arg_32bit_limm): Likewise.
983
20f55f38
SN		 9842016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
985
986 * aarch64-gen.c (VERIFIER): Define.
987 * aarch64-opc.c (VERIFIER): Define.
988 (verify_ldpsw): Use static linkage.
989 * aarch64-opc.h (verify_ldpsw): Remove.
990 * aarch64-tbl.h: Use VERIFIER for verifiers.
991
4bd13cde
NC		 9922016-04-28 Nick Clifton <nickc@redhat.com>
993
994 PR target/19722
995 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
996 * aarch64-opc.c (verify_ldpsw): New function.
997 * aarch64-opc.h (verify_ldpsw): New prototype.
998 * aarch64-tbl.h: Add initialiser for verifier field.
999 (LDPSW): Set verifier to verify_ldpsw.
1000
c0f92bf9
L		 10012016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1002
1003 PR binutils/19983
1004 PR binutils/19984
1005 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1006 smaller than address size.
1007
e6c7cdec
TS		 10082016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1009
1010 * alpha-dis.c: Regenerate.
1011 * crx-dis.c: Likewise.
1012 * disassemble.c: Likewise.
1013 * epiphany-opc.c: Likewise.
1014 * fr30-opc.c: Likewise.
1015 * frv-opc.c: Likewise.
1016 * ip2k-opc.c: Likewise.
1017 * iq2000-opc.c: Likewise.
1018 * lm32-opc.c: Likewise.
1019 * lm32-opinst.c: Likewise.
1020 * m32c-opc.c: Likewise.
1021 * m32r-opc.c: Likewise.
1022 * m32r-opinst.c: Likewise.
1023 * mep-opc.c: Likewise.
1024 * mt-opc.c: Likewise.
1025 * or1k-opc.c: Likewise.
1026 * or1k-opinst.c: Likewise.
1027 * tic80-opc.c: Likewise.
1028 * xc16x-opc.c: Likewise.
1029 * xstormy16-opc.c: Likewise.
1030
537aefaf
AB		 10312016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1032
1033 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1034 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1035 calcsd, and calcxd instructions.
1036 * arc-opc.c (insert_nps_bitop_size): Delete.
1037 (extract_nps_bitop_size): Delete.
1038 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1039 (extract_nps_qcmp_m3): Define.
1040 (extract_nps_qcmp_m2): Define.
1041 (extract_nps_qcmp_m1): Define.
1042 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1043 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1044 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1045 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1046 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1047 NPS_QCMP_M3.
1048
c8f785f2
AB		 10492016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1050
1051 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1052
6fd8e7c2
L		 10532016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1054
1055 * Makefile.in: Regenerated with automake 1.11.6.
1056 * aclocal.m4: Likewise.
1057
4b0c052e
AB		 10582016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1059
1060 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1061 instructions.
1062 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1063 (extract_nps_cmem_uimm16): New function.
1064 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1065
cb040366
AB		 10662016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1067
1068 * arc-dis.c (arc_insn_length): New function.
1069 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1070 (find_format): Change insnLen parameter to unsigned.
1071
accc0180
NC		 10722016-04-13 Nick Clifton <nickc@redhat.com>
1073
1074 PR target/19937
1075 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1076 the LD.B and LD.BU instructions.
1077
f36e33da
CZ		 10782016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1079
1080 * arc-dis.c (find_format): Check for extension flags.
1081 (print_flags): New function.
1082 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1083 .extAuxRegister.
1084 * arc-ext.c (arcExtMap_coreRegName): Use
1085 LAST_EXTENSION_CORE_REGISTER.
1086 (arcExtMap_coreReadWrite): Likewise.
1087 (dump_ARC_extmap): Update printing.
1088 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1089 (arc_aux_regs): Add cpu field.
1090 * arc-regs.h: Add cpu field, lower case name aux registers.
1091
1c2e355e
CZ		 10922016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1093
1094 * arc-tbl.h: Add rtsc, sleep with no arguments.
1095
b99747ae
CZ		 10962016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1097
1098 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1099 Initialize.
1100 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1101 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1102 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1103 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1104 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1105 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1106 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1107 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1108 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1109 (arc_opcode arc_opcodes): Null terminate the array.
1110 (arc_num_opcodes): Remove.
1111 * arc-ext.h (INSERT_XOP): Define.
1112 (extInstruction_t): Likewise.
1113 (arcExtMap_instName): Delete.
1114 (arcExtMap_insn): New function.
1115 (arcExtMap_genOpcode): Likewise.
1116 * arc-ext.c (ExtInstruction): Remove.
1117 (create_map): Zero initialize instruction fields.
1118 (arcExtMap_instName): Remove.
1119 (arcExtMap_insn): New function.
1120 (dump_ARC_extmap): More info while debuging.
1121 (arcExtMap_genOpcode): New function.
1122 * arc-dis.c (find_format): New function.
1123 (print_insn_arc): Use find_format.
1124 (arc_get_disassembler): Enable dump_ARC_extmap only when
1125 debugging.
1126
92708cec
MR		 11272016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1128
1129 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1130 instruction bits out.
1131
a42a4f84
AB		 11322016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1133
1134 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1135 * arc-opc.c (arc_flag_operands): Add new flags.
1136 (arc_flag_classes): Add new classes.
1137
1328504b
AB		 11382016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1139
1140 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1141
820f03ff
AB		 11422016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1143
1144 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1145 encode1, rflt, crc16, and crc32 instructions.
1146 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1147 (arc_flag_classes): Add C_NPS_R.
1148 (insert_nps_bitop_size_2b): New function.
1149 (extract_nps_bitop_size_2b): Likewise.
1150 (insert_nps_bitop_uimm8): Likewise.
1151 (extract_nps_bitop_uimm8): Likewise.
1152 (arc_operands): Add new operand entries.
1153
8ddf6b2a
CZ		 11542016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1155
b99747ae
CZ		 1156 * arc-regs.h: Add a new subclass field. Add double assist
1157 accumulator register values.
1158 * arc-tbl.h: Use DPA subclass to mark the double assist
1159 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1160 * arc-opc.c (RSP): Define instead of SP.
1161 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1162
589a7d88
JW		 11632016-04-05 Jiong Wang <jiong.wang@arm.com>
1164
1165 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1166
0a191de9 11672016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1168
1169 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1170 NPS_R_SRC1.
1171
0a106562
AB		 11722016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1173
1174 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1175 issues. No functional changes.
1176
bd05ac5f
CZ		 11772016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1178
b99747ae
CZ		 1179 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1180 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1181 (RTT): Remove duplicate.
1182 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1183 (PCT_CONFIG*): Remove.
1184 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1185
9885948f
CZ		 11862016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1187
b99747ae 1188 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1189
f2dd8838
CZ		 11902016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1191
b99747ae
CZ		 1192 * arc-tbl.h (invld07): Remove.
1193 * arc-ext-tbl.h: New file.
1194 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1195 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1196
0d2f91fe
JK		 11972016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1198
1199 Fix -Wstack-usage warnings.
1200 * aarch64-dis.c (print_operands): Substitute size.
1201 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1202
a6b71f42
JM		 12032016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1204
1205 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1206 to get a proper diagnostic when an invalid ASR register is used.
1207
9780e045
NC		 12082016-03-22 Nick Clifton <nickc@redhat.com>
1209
1210 * configure: Regenerate.
1211
e23e8ebe
AB		 12122016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1213
1214 * arc-nps400-tbl.h: New file.
1215 * arc-opc.c: Add top level comment.
1216 (insert_nps_3bit_dst): New function.
1217 (extract_nps_3bit_dst): New function.
1218 (insert_nps_3bit_src2): New function.
1219 (extract_nps_3bit_src2): New function.
1220 (insert_nps_bitop_size): New function.
1221 (extract_nps_bitop_size): New function.
1222 (arc_flag_operands): Add nps400 entries.
1223 (arc_flag_classes): Add nps400 entries.
1224 (arc_operands): Add nps400 entries.
1225 (arc_opcodes): Add nps400 include.
1226
1ae8ab47
AB		 12272016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1228
1229 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1230 the new class enum values.
1231
8699fc3e
AB		 12322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1233
1234 * arc-dis.c (print_insn_arc): Handle nps400.
1235
24740d83
AB		 12362016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1237
1238 * arc-opc.c (BASE): Delete.
1239
8678914f
NC		 12402016-03-18 Nick Clifton <nickc@redhat.com>
1241
1242 PR target/19721
1243 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1244 of MOV insn that aliases an ORR insn.
1245
cc933301
JW		 12462016-03-16 Jiong Wang <jiong.wang@arm.com>
1247
1248 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1249
f86f5863
TS		 12502016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1251
1252 * mcore-opc.h: Add const qualifiers.
1253 * microblaze-opc.h (struct op_code_struct): Likewise.
1254 * sh-opc.h: Likewise.
1255 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1256 (tic4x_print_op): Likewise.
1257
62de1c63
AM		 12582016-03-02 Alan Modra <amodra@gmail.com>
1259
d11698cd 1260 * or1k-desc.h: Regenerate.
62de1c63 1261 * fr30-ibld.c: Regenerate.
c697cf0b 1262 * rl78-decode.c: Regenerate.
62de1c63 1263
020efce5
NC		 12642016-03-01 Nick Clifton <nickc@redhat.com>
1265
1266 PR target/19747
1267 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1268
b0c11777
RL		 12692016-02-24 Renlin Li <renlin.li@arm.com>
1270
1271 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1272 (print_insn_coprocessor): Support fp16 instructions.
1273
3e309328
RL		 12742016-02-24 Renlin Li <renlin.li@arm.com>
1275
1276 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1277 vminnm, vrint(mpna).
1278
8afc7bea
RL		 12792016-02-24 Renlin Li <renlin.li@arm.com>
1280
1281 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1282 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1283
4fd7268a
L		 12842016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1285
1286 * i386-dis.c (print_insn): Parenthesize expression to prevent
1287 truncated addresses.
1288 (OP_J): Likewise.
1289
4670103e
CZ		 12902016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1291 Janek van Oirschot <jvanoirs@synopsys.com>
1292
b99747ae
CZ		 1293 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1294 variable.
4670103e 1295
c1d9289f
NC		 12962016-02-04 Nick Clifton <nickc@redhat.com>
1297
1298 PR target/19561
1299 * msp430-dis.c (print_insn_msp430): Add a special case for
1300 decoding an RRC instruction with the ZC bit set in the extension
1301 word.
1302
a143b004
AB		 13032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1304
1305 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1306 * epiphany-ibld.c: Regenerate.
1307 * fr30-ibld.c: Regenerate.
1308 * frv-ibld.c: Regenerate.
1309 * ip2k-ibld.c: Regenerate.
1310 * iq2000-ibld.c: Regenerate.
1311 * lm32-ibld.c: Regenerate.
1312 * m32c-ibld.c: Regenerate.
1313 * m32r-ibld.c: Regenerate.
1314 * mep-ibld.c: Regenerate.
1315 * mt-ibld.c: Regenerate.
1316 * or1k-ibld.c: Regenerate.
1317 * xc16x-ibld.c: Regenerate.
1318 * xstormy16-ibld.c: Regenerate.
1319
b89807c6
AB		 13202016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1321
1322 * epiphany-dis.c: Regenerated from latest cpu files.
1323
d8c823c8
MM		 13242016-02-01 Michael McConville <mmcco@mykolab.com>
1325
1326 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1327 test bit.
1328
5bc5ae88
RL		 13292016-01-25 Renlin Li <renlin.li@arm.com>
1330
1331 * arm-dis.c (mapping_symbol_for_insn): New function.
1332 (find_ifthen_state): Call mapping_symbol_for_insn().
1333
0bff6e2d
MW		 13342016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1335
1336 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1337 of MSR UAO immediate operand.
1338
100b4f2e
MR		 13392016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1340
1341 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1342 instruction support.
1343
5c14705f
AM		 13442016-01-17 Alan Modra <amodra@gmail.com>
1345
1346 * configure: Regenerate.
1347
4d82fe66
NC		 13482016-01-14 Nick Clifton <nickc@redhat.com>
1349
1350 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1351 instructions that can support stack pointer operations.
1352 * rl78-decode.c: Regenerate.
1353 * rl78-dis.c: Fix display of stack pointer in MOVW based
1354 instructions.
1355
651657fa
MW		 13562016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1357
1358 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1359 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1360 erxtatus_el1 and erxaddr_el1.
1361
105bde57
MW		 13622016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1363
1364 * arm-dis.c (arm_opcodes): Add "esb".
1365 (thumb_opcodes): Likewise.
1366
afa8d405
PB		 13672016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1368
1369 * ppc-opc.c <xscmpnedp>: Delete.
1370 <xvcmpnedp>: Likewise.
1371 <xvcmpnedp.>: Likewise.
1372 <xvcmpnesp>: Likewise.
1373 <xvcmpnesp.>: Likewise.
1374
83c3256e
AS		 13752016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1376
1377 PR gas/13050
1378 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1379 addition to ISA_A.
1380
6f2750fe
AM		 13812016-01-01 Alan Modra <amodra@gmail.com>
1382
1383 Update year range in copyright notice of all files.
1384
3499769a
AM		 1385For older changes see ChangeLog-2015
1386\f
1387Copyright (C) 2016 Free Software Foundation, Inc.
1388
1389Copying and distribution of this file, with or without modification,
1390are permitted in any medium without royalty provided the copyright
1391notice and this notice are preserved.
1392
1393Local Variables:
1394mode: change-log
1395left-margin: 8
1396fill-column: 74
1397version-control: never
1398End:
GDB Binutils - Deliverables
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