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ubsan: m68hc1x: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
000fe1a7
AM		 12019-12-20 Alan Modra <amodra@gmail.com>
2
3 * m68hc11-dis.c (read_memory): Delete forward decls.
4 (print_indexed_operand, print_insn): Likewise.
5 (print_indexed_operand): Formatting. Don't rely on short being
6 exactly 16 bits, make sign extension explicit.
7 (print_insn): Likewise. Avoid signed overflow.
8
f0090188
AM		 92019-12-19 Alan Modra <amodra@gmail.com>
10
11 * vax-dis.c (print_insn_mode): Stop index mode recursion.
12
1d29ab86
DF		 132019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
14
15 PR 25277
16 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
17 fdiv with "mbi_".
18 * microblaze-opc.h (opcodes): Adjust to suit.
19
2480b6fa
AM		 202019-12-18 Alan Modra <amodra@gmail.com>
21
22 * alpha-opc.c (OP): Avoid signed overflow.
23 * arm-dis.c (print_insn): Likewise.
24 * mcore-dis.c (print_insn_mcore): Likewise.
25 * pj-dis.c (get_int): Likewise.
26 * ppc-opc.c (EBD15, EBD15BI): Likewise.
27 * score7-dis.c (s7_print_insn): Likewise.
28 * tic30-dis.c (print_insn_tic30): Likewise.
29 * v850-opc.c (insert_SELID): Likewise.
30 * vax-dis.c (print_insn_vax): Likewise.
31 * arc-ext.c (create_map): Likewise.
32 (struct ExtAuxRegister): Make "address" field unsigned int.
33 (arcExtMap_auxRegName): Pass unsigned address.
34 (dump_ARC_extmap): Adjust.
35 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
36
eb7b5046
AM		 372019-12-17 Alan Modra <amodra@gmail.com>
38
39 * visium-dis.c (print_insn_visium): Avoid signed overflow.
40
29298bf6
AM		 412019-12-17 Alan Modra <amodra@gmail.com>
42
43 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
44 (value_fit_unsigned_field_p): Likewise.
45 (aarch64_wide_constant_p): Likewise.
46 (operand_general_constraint_met_p): Likewise.
47 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
48
e46d79a7
AM		 492019-12-17 Alan Modra <amodra@gmail.com>
50
51 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
52 (print_insn_nds32): Use uint64_t for "given" and "given1".
53
5b660084
AM		 542019-12-17 Alan Modra <amodra@gmail.com>
55
56 * tic80-dis.c: Delete file.
57 * tic80-opc.c: Delete file.
58 * disassemble.c: Remove tic80 support.
59 * disassemble.h: Likewise.
60 * Makefile.am: Likewise.
61 * configure.ac: Likewise.
62 * Makefile.in: Regenerate.
63 * configure: Regenerate.
64 * po/POTFILES.in: Regenerate.
65
62e65990
AM		 662019-12-17 Alan Modra <amodra@gmail.com>
67
68 * bpf-ibld.c: Regenerate.
69
f81e7e2d
AM		 702019-12-16 Alan Modra <amodra@gmail.com>
71
72 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
73 conditional.
74 (aarch64_ext_imm): Avoid signed overflow.
75
488d02fe
AM		 762019-12-16 Alan Modra <amodra@gmail.com>
77
78 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
79
8a92faab
AM		 802019-12-16 Alan Modra <amodra@gmail.com>
81
82 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
83
e6ced26a
AM		 842019-12-16 Alan Modra <amodra@gmail.com>
85
86 * xstormy16-ibld.c: Regenerate.
87
84e098cd
AM		 882019-12-16 Alan Modra <amodra@gmail.com>
89
90 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
91 value adjustment so that it doesn't affect reg field too.
92
36bd8ea7
AM		 932019-12-16 Alan Modra <amodra@gmail.com>
94
95 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
96 (get_number_of_operands, getargtype, getbits, getregname),
97 (getcopregname, getprocregname, gettrapstring, getcinvstring),
98 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
99 (powerof2, match_opcode, make_instruction, print_arguments),
100 (print_arg): Delete forward declarations, moving static to..
101 (getregname, getcopregname, getregliststring): ..these definitions.
102 (build_mask): Return unsigned int mask.
103 (match_opcode): Use unsigned int vars.
104
cedfc774
AM		 1052019-12-16 Alan Modra <amodra@gmail.com>
106
107 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
108
4bdb25fe
AM		 1092019-12-16 Alan Modra <amodra@gmail.com>
110
111 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
112 (struct objdump_disasm_info): Delete.
113 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
114 N32_IMMS to unsigned before shifting left.
115
cf950fd4
AM		 1162019-12-16 Alan Modra <amodra@gmail.com>
117
118 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
119 (print_insn_moxie): Remove unnecessary cast.
120
967354c3
AM		 1212019-12-12 Alan Modra <amodra@gmail.com>
122
123 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
124 mask.
125
1d61b032
AM		 1262019-12-11 Alan Modra <amodra@gmail.com>
127
128 * arc-dis.c (BITS): Don't truncate high bits with shifts.
129 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
130 * tic54x-dis.c (print_instruction): Likewise.
131 * tilegx-opc.c (parse_insn_tilegx): Likewise.
132 * tilepro-opc.c (parse_insn_tilepro): Likewise.
133 * visium-dis.c (disassem_class0): Likewise.
134 * pdp11-dis.c (sign_extend): Likewise.
135 (SIGN_BITS): Delete.
136 * epiphany-ibld.c: Regenerate.
137 * lm32-ibld.c: Regenerate.
138 * m32c-ibld.c: Regenerate.
139
5afa80e9
AM		 1402019-12-11 Alan Modra <amodra@gmail.com>
141
142 * ns32k-dis.c (sign_extend): Correct last patch.
143
5c05618a
AM		 1442019-12-11 Alan Modra <amodra@gmail.com>
145
146 * vax-dis.c (NEXTLONG): Avoid signed overflow.
147
2a81ccbb
AM		 1482019-12-11 Alan Modra <amodra@gmail.com>
149
150 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
151 sign extend using shifts.
152
b84f6152
AM		 1532019-12-11 Alan Modra <amodra@gmail.com>
154
155 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
156
66152f16
AM		 1572019-12-11 Alan Modra <amodra@gmail.com>
158
159 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
160 on NULL registertable entry.
161 (tic4x_hash_opcode): Use unsigned arithmetic.
162
205c426a
AM		 1632019-12-11 Alan Modra <amodra@gmail.com>
164
165 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
166
fb4cb4e2
AM		 1672019-12-11 Alan Modra <amodra@gmail.com>
168
169 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
170 (bit_extract_simple, sign_extend): Likewise.
171
96f1f604
AM		 1722019-12-11 Alan Modra <amodra@gmail.com>
173
174 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
175
8c9b4171
AM		 1762019-12-11 Alan Modra <amodra@gmail.com>
177
178 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
179
334175b6
AM		 1802019-12-11 Alan Modra <amodra@gmail.com>
181
182 * m68k-dis.c (COERCE32): Cast value first.
183 (NEXTLONG, NEXTULONG): Avoid signed overflow.
184
f8a87c78
AM		 1852019-12-11 Alan Modra <amodra@gmail.com>
186
187 * h8300-dis.c (extract_immediate): Avoid signed overflow.
188 (bfd_h8_disassemble): Likewise.
189
159653d8
AM		 1902019-12-11 Alan Modra <amodra@gmail.com>
191
192 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
193 past end of operands array.
194
d93bba9e
AM		 1952019-12-11 Alan Modra <amodra@gmail.com>
196
197 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
198 overflow when collecting bytes of a number.
199
c202f69e
AM		 2002019-12-11 Alan Modra <amodra@gmail.com>
201
202 * cris-dis.c (print_with_operands): Avoid signed integer
203 overflow when collecting bytes of a 32-bit integer.
204
0ef562a4
AM		 2052019-12-11 Alan Modra <amodra@gmail.com>
206
207 * cr16-dis.c (EXTRACT, SBM): Rewrite.
208 (cr16_match_opcode): Delete duplicate bcond test.
209
2fd2b153
AM		 2102019-12-11 Alan Modra <amodra@gmail.com>
211
212 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
213 (SIGNBIT): New.
214 (MASKBITS, SIGNEXTEND): Rewrite.
215 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
216 unsigned arithmetic, instead assign result of SIGNEXTEND back
217 to x.
218 (fmtconst_val): Use 1u in shift expression.
219
a11db3e9
AM		 2202019-12-11 Alan Modra <amodra@gmail.com>
221
222 * arc-dis.c (find_format_from_table): Use ull constant when
223 shifting by up to 32.
224
9d48687b
AM		 2252019-12-11 Alan Modra <amodra@gmail.com>
226
227 PR 25270
228 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
229 false when field is zero for sve_size_tsz_bhs.
230
b8e61daa
AM		 2312019-12-11 Alan Modra <amodra@gmail.com>
232
233 * epiphany-ibld.c: Regenerate.
234
20135676
AM		 2352019-12-10 Alan Modra <amodra@gmail.com>
236
237 PR 24960
238 * disassemble.c (disassemble_free_target): New function.
239
103ebbc3
AM		 2402019-12-10 Alan Modra <amodra@gmail.com>
241
242 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
243 * disassemble.c (disassemble_init_for_target): Likewise.
244 * bpf-dis.c: Regenerate.
245 * epiphany-dis.c: Regenerate.
246 * fr30-dis.c: Regenerate.
247 * frv-dis.c: Regenerate.
248 * ip2k-dis.c: Regenerate.
249 * iq2000-dis.c: Regenerate.
250 * lm32-dis.c: Regenerate.
251 * m32c-dis.c: Regenerate.
252 * m32r-dis.c: Regenerate.
253 * mep-dis.c: Regenerate.
254 * mt-dis.c: Regenerate.
255 * or1k-dis.c: Regenerate.
256 * xc16x-dis.c: Regenerate.
257 * xstormy16-dis.c: Regenerate.
258
6f0e0752
AM		 2592019-12-10 Alan Modra <amodra@gmail.com>
260
261 * ppc-dis.c (private): Delete variable.
262 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
263 (powerpc_init_dialect): Don't use global private.
264
e7c22a69
AM		 2652019-12-10 Alan Modra <amodra@gmail.com>
266
267 * s12z-opc.c: Formatting.
268
0a6aef6b
AM		 2692019-12-08 Alan Modra <amodra@gmail.com>
270
271 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
272 registers.
273
2dc4b12f
JB		 2742019-12-05 Jan Beulich <jbeulich@suse.com>
275
276 * aarch64-tbl.h (aarch64_feature_crypto,
277 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
278 CRYPTO_V8_2_INSN): Delete.
279
378fd436
AM		 2802019-12-05 Alan Modra <amodra@gmail.com>
281
282 PR 25249
283 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
284 (struct string_buf): New.
285 (strbuf): New function.
286 (get_field): Use strbuf rather than strdup of local temp.
287 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
288 (get_field_rfsl, get_field_imm15): Likewise.
289 (get_field_rd, get_field_r1, get_field_r2): Update macros.
290 (get_field_special): Likewise. Don't strcpy spr. Formatting.
291 (print_insn_microblaze): Formatting. Init and pass string_buf to
292 get_field functions.
293
0ba59a29
JB		 2942019-12-04 Jan Beulich <jbeulich@suse.com>
295
296 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
297 * i386-tbl.h: Re-generate.
298
77ad8092
JB		 2992019-12-04 Jan Beulich <jbeulich@suse.com>
300
301 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
302
3036c899
JB		 3032019-12-04 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
306 forms.
307 (xbegin): Drop DefaultSize.
308 * i386-tbl.h: Re-generate.
309
8b301fbb
MI		 3102019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
311
312 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
313 Change the coproc CRC conditions to use the extension
314 feature set, second word, base on ARM_EXT2_CRC.
315
6aa385b9
JB		 3162019-11-14 Jan Beulich <jbeulich@suse.com>
317
318 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
319 * i386-tbl.h: Re-generate.
320
0cfa3eb3
JB		 3212019-11-14 Jan Beulich <jbeulich@suse.com>
322
323 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
324 JumpInterSegment, and JumpAbsolute entries.
325 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
326 JUMP_ABSOLUTE): Define.
327 (struct i386_opcode_modifier): Extend jump field to 3 bits.
328 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
329 fields.
330 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
331 JumpInterSegment): Define.
332 * i386-tbl.h: Re-generate.
333
6f2f06be
JB		 3342019-11-14 Jan Beulich <jbeulich@suse.com>
335
336 * i386-gen.c (operand_type_init): Remove
337 OPERAND_TYPE_JUMPABSOLUTE entry.
338 (opcode_modifiers): Add JumpAbsolute entry.
339 (operand_types): Remove JumpAbsolute entry.
340 * i386-opc.h (JumpAbsolute): Move between enums.
341 (struct i386_opcode_modifier): Add jumpabsolute field.
342 (union i386_operand_type): Remove jumpabsolute field.
343 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
344 * i386-init.h, i386-tbl.h: Re-generate.
345
601e8564
JB		 3462019-11-14 Jan Beulich <jbeulich@suse.com>
347
348 * i386-gen.c (opcode_modifiers): Add AnySize entry.
349 (operand_types): Remove AnySize entry.
350 * i386-opc.h (AnySize): Move between enums.
351 (struct i386_opcode_modifier): Add anysize field.
352 (OTUnused): Un-comment.
353 (union i386_operand_type): Remove anysize field.
354 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
355 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
356 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
357 AnySize.
358 * i386-tbl.h: Re-generate.
359
7722d40a
JW		 3602019-11-12 Nelson Chu <nelson.chu@sifive.com>
361
362 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
363 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
364 use the floating point register (FPR).
365
ce760a76
MI		 3662019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
367
368 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
369 cmode 1101.
370 (is_mve_encoding_conflict): Update cmode conflict checks for
371 MVE_VMVN_IMM.
372
51c8edf6
JB		 3732019-11-12 Jan Beulich <jbeulich@suse.com>
374
375 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
376 entry.
377 (operand_types): Remove EsSeg entry.
378 (main): Replace stale use of OTMax.
379 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
380 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
381 (EsSeg): Delete.
382 (OTUnused): Comment out.
383 (union i386_operand_type): Remove esseg field.
384 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
385 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
386 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
387 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
388 * i386-init.h, i386-tbl.h: Re-generate.
389
474da251
JB		 3902019-11-12 Jan Beulich <jbeulich@suse.com>
391
392 * i386-gen.c (operand_instances): Add RegB entry.
393 * i386-opc.h (enum operand_instance): Add RegB.
394 * i386-opc.tbl (RegC, RegD, RegB): Define.
395 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
396 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
397 monitorx, mwaitx): Drop ImmExt and convert encodings
398 accordingly.
399 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
400 (edx, rdx): Add Instance=RegD.
401 (ebx, rbx): Add Instance=RegB.
402 * i386-tbl.h: Re-generate.
403
75e5731b
JB		 4042019-11-12 Jan Beulich <jbeulich@suse.com>
405
406 * i386-gen.c (operand_type_init): Adjust
407 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
408 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
409 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
410 (operand_instances): New.
411 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
412 (output_operand_type): New parameter "instance". Process it.
413 (process_i386_operand_type): New local variable "instance".
414 (main): Adjust static assertions.
415 * i386-opc.h (INSTANCE_WIDTH): Define.
416 (enum operand_instance): New.
417 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
418 (union i386_operand_type): Replace acc, inoutportreg, and
419 shiftcount by instance.
420 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
421 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
422 Add Instance=.
423 * i386-init.h, i386-tbl.h: Re-generate.
424
91802f3c
JB		 4252019-11-11 Jan Beulich <jbeulich@suse.com>
426
427 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
428 smaxp/sminp entries' "tied_operand" field to 2.
429
4f5fc85d
JB		 4302019-11-11 Jan Beulich <jbeulich@suse.com>
431
432 * aarch64-opc.c (operand_general_constraint_met_p): Replace
433 "index" local variable by that of the already existing "num".
434
dc2be329
L		 4352019-11-08 H.J. Lu <hongjiu.lu@intel.com>
436
437 PR gas/25167
438 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
439 * i386-tbl.h: Regenerated.
440
f74a6307
JB		 4412019-11-08 Jan Beulich <jbeulich@suse.com>
442
443 * i386-gen.c (operand_type_init): Add Class= to
444 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
445 OPERAND_TYPE_REGBND entry.
446 (operand_classes): Add RegMask and RegBND entries.
447 (operand_types): Drop RegMask and RegBND entry.
448 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
449 (RegMask, RegBND): Delete.
450 (union i386_operand_type): Remove regmask and regbnd fields.
451 * i386-opc.tbl (RegMask, RegBND): Define.
452 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
453 Class=RegBND.
454 * i386-init.h, i386-tbl.h: Re-generate.
455
3528c362
JB		 4562019-11-08 Jan Beulich <jbeulich@suse.com>
457
458 * i386-gen.c (operand_type_init): Add Class= to
459 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
460 OPERAND_TYPE_REGZMM entries.
461 (operand_classes): Add RegMMX and RegSIMD entries.
462 (operand_types): Drop RegMMX and RegSIMD entries.
463 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
464 (RegMMX, RegSIMD): Delete.
465 (union i386_operand_type): Remove regmmx and regsimd fields.
466 * i386-opc.tbl (RegMMX): Define.
467 (RegXMM, RegYMM, RegZMM): Add Class=.
468 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
469 Class=RegSIMD.
470 * i386-init.h, i386-tbl.h: Re-generate.
471
4a5c67ed
JB		 4722019-11-08 Jan Beulich <jbeulich@suse.com>
473
474 * i386-gen.c (operand_type_init): Add Class= to
475 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
476 entries.
477 (operand_classes): Add RegCR, RegDR, and RegTR entries.
478 (operand_types): Drop Control, Debug, and Test entries.
479 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
480 (Control, Debug, Test): Delete.
481 (union i386_operand_type): Remove control, debug, and test
482 fields.
483 * i386-opc.tbl (Control, Debug, Test): Define.
484 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
485 Class=RegDR, and Test by Class=RegTR.
486 * i386-init.h, i386-tbl.h: Re-generate.
487
00cee14f
JB		 4882019-11-08 Jan Beulich <jbeulich@suse.com>
489
490 * i386-gen.c (operand_type_init): Add Class= to
491 OPERAND_TYPE_SREG entry.
492 (operand_classes): Add SReg entry.
493 (operand_types): Drop SReg entry.
494 * i386-opc.h (enum operand_class): Add SReg.
495 (SReg): Delete.
496 (union i386_operand_type): Remove sreg field.
497 * i386-opc.tbl (SReg): Define.
498 * i386-reg.tbl: Replace SReg by Class=SReg.
499 * i386-init.h, i386-tbl.h: Re-generate.
500
bab6aec1
JB		 5012019-11-08 Jan Beulich <jbeulich@suse.com>
502
503 * i386-gen.c (operand_type_init): Add Class=. New
504 OPERAND_TYPE_ANYIMM entry.
505 (operand_classes): New.
506 (operand_types): Drop Reg entry.
507 (output_operand_type): New parameter "class". Process it.
508 (process_i386_operand_type): New local variable "class".
509 (main): Adjust static assertions.
510 * i386-opc.h (CLASS_WIDTH): Define.
511 (enum operand_class): New.
512 (Reg): Replace by Class. Adjust comment.
513 (union i386_operand_type): Replace reg by class.
514 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
515 Class=.
516 * i386-reg.tbl: Replace Reg by Class=Reg.
517 * i386-init.h: Re-generate.
518
1f4cd317
MM		 5192019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
520
521 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
522 (aarch64_opcode_table): Add data gathering hint mnemonic.
523 * opcodes/aarch64-dis-2.c: Account for new instruction.
524
616ce08e
MM		 5252019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
526
527 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
528
529
8382113f
MM		 5302019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
531
532 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
533 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
534 aarch64_feature_f64mm): New feature sets.
535 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
536 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
537 instructions.
538 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
539 macros.
540 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
541 (OP_SVE_QQQ): New qualifier.
542 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
543 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
544 the movprfx constraint.
545 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
546 (aarch64_opcode_table): Define new instructions smmla,
547 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
548 uzip{1/2}, trn{1/2}.
549 * aarch64-opc.c (operand_general_constraint_met_p): Handle
550 AARCH64_OPND_SVE_ADDR_RI_S4x32.
551 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
552 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
553 Account for new instructions.
554 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
555 S4x32 operand.
556 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
557
aab2c27d
MM		 5582019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5592019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
560
561 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
562 Armv8.6-A.
563 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
564 (neon_opcodes): Add bfloat SIMD instructions.
565 (print_insn_coprocessor): Add new control character %b to print
566 condition code without checking cp_num.
567 (print_insn_neon): Account for BFloat16 instructions that have no
568 special top-byte handling.
569
33593eaf
MM		 5702019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5712019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
572
573 * arm-dis.c (print_insn_coprocessor,
574 print_insn_generic_coprocessor): Create wrapper functions around
575 the implementation of the print_insn_coprocessor control codes.
576 (print_insn_coprocessor_1): Original print_insn_coprocessor
577 function that now takes which array to look at as an argument.
578 (print_insn_arm): Use both print_insn_coprocessor and
579 print_insn_generic_coprocessor.
580 (print_insn_thumb32): As above.
581
df678013
MM		 5822019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5832019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
584
585 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
586 in reglane special case.
587 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
588 aarch64_find_next_opcode): Account for new instructions.
589 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
590 in reglane special case.
591 * aarch64-opc.c (struct operand_qualifier_data): Add data for
592 new AARCH64_OPND_QLF_S_2H qualifier.
593 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
594 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
595 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
596 sets.
597 (BFLOAT_SVE, BFLOAT): New feature set macros.
598 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
599 instructions.
600 (aarch64_opcode_table): Define new instructions bfdot,
601 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
602 bfcvtn2, bfcvt.
603
8ae2d3d9
MM		 6042019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6052019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
606
607 * aarch64-tbl.h (ARMV8_6): New macro.
608
142861df
JB		 6092019-11-07 Jan Beulich <jbeulich@suse.com>
610
611 * i386-dis.c (prefix_table): Add mcommit.
612 (rm_table): Add rdpru.
613 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
614 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
615 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
616 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
617 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
618 * i386-opc.tbl (mcommit, rdpru): New.
619 * i386-init.h, i386-tbl.h: Re-generate.
620
081e283f
JB		 6212019-11-07 Jan Beulich <jbeulich@suse.com>
622
623 * i386-dis.c (OP_Mwait): Drop local variable "names", use
624 "names32" instead.
625 (OP_Monitor): Drop local variable "op1_names", re-purpose
626 "names" for it instead, and replace former "names" uses by
627 "names32" ones.
628
c050c89a
JB		 6292019-11-07 Jan Beulich <jbeulich@suse.com>
630
631 PR/gas 25167
632 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
633 operand-less forms.
634 * opcodes/i386-tbl.h: Re-generate.
635
7abb8d81
JB		 6362019-11-05 Jan Beulich <jbeulich@suse.com>
637
638 * i386-dis.c (OP_Mwaitx): Delete.
639 (prefix_table): Use OP_Mwait for mwaitx entry.
640 (OP_Mwait): Also handle mwaitx.
641
267b8516
JB		 6422019-11-05 Jan Beulich <jbeulich@suse.com>
643
644 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
645 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
646 (prefix_table): Add respective entries.
647 (rm_table): Link to those entries.
648
f8687e93
JB		 6492019-11-05 Jan Beulich <jbeulich@suse.com>
650
651 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
652 (REG_0F1C_P_0_MOD_0): ... this.
653 (REG_0F1E_MOD_3): Rename to ...
654 (REG_0F1E_P_1_MOD_3): ... this.
655 (RM_0F01_REG_5): Rename to ...
656 (RM_0F01_REG_5_MOD_3): ... this.
657 (RM_0F01_REG_7): Rename to ...
658 (RM_0F01_REG_7_MOD_3): ... this.
659 (RM_0F1E_MOD_3_REG_7): Rename to ...
660 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
661 (RM_0FAE_REG_6): Rename to ...
662 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
663 (RM_0FAE_REG_7): Rename to ...
664 (RM_0FAE_REG_7_MOD_3): ... this.
665 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
666 (PREFIX_0F01_REG_5_MOD_0): ... this.
667 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
668 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
669 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
670 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
671 (PREFIX_0FAE_REG_0): Rename to ...
672 (PREFIX_0FAE_REG_0_MOD_3): ... this.
673 (PREFIX_0FAE_REG_1): Rename to ...
674 (PREFIX_0FAE_REG_1_MOD_3): ... this.
675 (PREFIX_0FAE_REG_2): Rename to ...
676 (PREFIX_0FAE_REG_2_MOD_3): ... this.
677 (PREFIX_0FAE_REG_3): Rename to ...
678 (PREFIX_0FAE_REG_3_MOD_3): ... this.
679 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
680 (PREFIX_0FAE_REG_4_MOD_0): ... this.
681 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
682 (PREFIX_0FAE_REG_4_MOD_3): ... this.
683 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
684 (PREFIX_0FAE_REG_5_MOD_0): ... this.
685 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
686 (PREFIX_0FAE_REG_5_MOD_3): ... this.
687 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
688 (PREFIX_0FAE_REG_6_MOD_0): ... this.
689 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
690 (PREFIX_0FAE_REG_6_MOD_3): ... this.
691 (PREFIX_0FAE_REG_7): Rename to ...
692 (PREFIX_0FAE_REG_7_MOD_0): ... this.
693 (PREFIX_MOD_0_0FC3): Rename to ...
694 (PREFIX_0FC3_MOD_0): ... this.
695 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
696 (PREFIX_0FC7_REG_6_MOD_0): ... this.
697 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
698 (PREFIX_0FC7_REG_6_MOD_3): ... this.
699 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
700 (PREFIX_0FC7_REG_7_MOD_3): ... this.
701 (reg_table, prefix_table, mod_table, rm_table): Adjust
702 accordingly.
703
5103274f
NC		 7042019-11-04 Nick Clifton <nickc@redhat.com>
705
706 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
707 of a v850 system register. Move the v850_sreg_names array into
708 this function.
709 (get_v850_reg_name): Likewise for ordinary register names.
710 (get_v850_vreg_name): Likewise for vector register names.
711 (get_v850_cc_name): Likewise for condition codes.
712 * get_v850_float_cc_name): Likewise for floating point condition
713 codes.
714 (get_v850_cacheop_name): Likewise for cache-ops.
715 (get_v850_prefop_name): Likewise for pref-ops.
716 (disassemble): Use the new accessor functions.
717
1820262b
DB		 7182019-10-30 Delia Burduv <delia.burduv@arm.com>
719
720 * aarch64-opc.c (print_immediate_offset_address): Don't print the
721 immediate for the writeback form of ldraa/ldrab if it is 0.
722 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
723 * aarch64-opc-2.c: Regenerated.
724
3cc17af5
JB		 7252019-10-30 Jan Beulich <jbeulich@suse.com>
726
727 * i386-gen.c (operand_type_shorthands): Delete.
728 (operand_type_init): Expand previous shorthands.
729 (set_bitfield_from_shorthand): Rename back to ...
730 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
731 of operand_type_init[].
732 (set_bitfield): Adjust call to the above function.
733 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
734 RegXMM, RegYMM, RegZMM): Define.
735 * i386-reg.tbl: Expand prior shorthands.
736
a2cebd03
JB		 7372019-10-30 Jan Beulich <jbeulich@suse.com>
738
739 * i386-gen.c (output_i386_opcode): Change order of fields
740 emitted to output.
741 * i386-opc.h (struct insn_template): Move operands field.
742 Convert extension_opcode field to unsigned short.
743 * i386-tbl.h: Re-generate.
744
507916b8
JB		 7452019-10-30 Jan Beulich <jbeulich@suse.com>
746
747 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
748 of W.
749 * i386-opc.h (W): Extend comment.
750 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
751 general purpose variants not allowing for byte operands.
752 * i386-tbl.h: Re-generate.
753
efea62b4
NC		 7542019-10-29 Nick Clifton <nickc@redhat.com>
755
756 * tic30-dis.c (print_branch): Correct size of operand array.
757
9adb2591
NC		 7582019-10-29 Nick Clifton <nickc@redhat.com>
759
760 * d30v-dis.c (print_insn): Check that operand index is valid
761 before attempting to access the operands array.
762
993a00a9
NC		 7632019-10-29 Nick Clifton <nickc@redhat.com>
764
765 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
766 locating the bit to be tested.
767
66a66a17
NC		 7682019-10-29 Nick Clifton <nickc@redhat.com>
769
770 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
771 values.
772 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
773 (print_insn_s12z): Check for illegal size values.
774
1ee3542c
NC		 7752019-10-28 Nick Clifton <nickc@redhat.com>
776
777 * csky-dis.c (csky_chars_to_number): Check for a negative
778 count. Use an unsigned integer to construct the return value.
779
bbf9a0b5
NC		 7802019-10-28 Nick Clifton <nickc@redhat.com>
781
782 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
783 operand buffer. Set value to 15 not 13.
784 (get_register_operand): Use OPERAND_BUFFER_LEN.
785 (get_indirect_operand): Likewise.
786 (print_two_operand): Likewise.
787 (print_three_operand): Likewise.
788 (print_oar_insn): Likewise.
789
d1e304bc
NC		 7902019-10-28 Nick Clifton <nickc@redhat.com>
791
792 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
793 (bit_extract_simple): Likewise.
794 (bit_copy): Likewise.
795 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
796 index_offset array are not accessed.
797
dee33451
NC		 7982019-10-28 Nick Clifton <nickc@redhat.com>
799
800 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
801 operand.
802
27cee81d
NC		 8032019-10-25 Nick Clifton <nickc@redhat.com>
804
805 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
806 access to opcodes.op array element.
807
de6d8dc2
NC		 8082019-10-23 Nick Clifton <nickc@redhat.com>
809
810 * rx-dis.c (get_register_name): Fix spelling typo in error
811 message.
812 (get_condition_name, get_flag_name, get_double_register_name)
813 (get_double_register_high_name, get_double_register_low_name)
814 (get_double_control_register_name, get_double_condition_name)
815 (get_opsize_name, get_size_name): Likewise.
816
6207ed28
NC		 8172019-10-22 Nick Clifton <nickc@redhat.com>
818
819 * rx-dis.c (get_size_name): New function. Provides safe
820 access to name array.
821 (get_opsize_name): Likewise.
822 (print_insn_rx): Use the accessor functions.
823
12234dfd
NC		 8242019-10-16 Nick Clifton <nickc@redhat.com>
825
826 * rx-dis.c (get_register_name): New function. Provides safe
827 access to name array.
828 (get_condition_name, get_flag_name, get_double_register_name)
829 (get_double_register_high_name, get_double_register_low_name)
830 (get_double_control_register_name, get_double_condition_name):
831 Likewise.
832 (print_insn_rx): Use the accessor functions.
833
1d378749
NC		 8342019-10-09 Nick Clifton <nickc@redhat.com>
835
836 PR 25041
837 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
838 instructions.
839
d241b910
JB		 8402019-10-07 Jan Beulich <jbeulich@suse.com>
841
842 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
843 (cmpsd): Likewise. Move EsSeg to other operand.
844 * opcodes/i386-tbl.h: Re-generate.
845
f5c5b7c1
AM		 8462019-09-23 Alan Modra <amodra@gmail.com>
847
848 * m68k-dis.c: Include cpu-m68k.h
849
7beeaeb8
AM		 8502019-09-23 Alan Modra <amodra@gmail.com>
851
852 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
853 "elf/mips.h" earlier.
854
3f9aad11
JB		 8552018-09-20 Jan Beulich <jbeulich@suse.com>
856
857 PR gas/25012
858 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
859 with SReg operand.
860 * i386-tbl.h: Re-generate.
861
fd361982
AM		 8622019-09-18 Alan Modra <amodra@gmail.com>
863
864 * arc-ext.c: Update throughout for bfd section macro changes.
865
e0b2a78c
SM		 8662019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
867
868 * Makefile.in: Re-generate.
869 * configure: Re-generate.
870
7e9ad3a3
JW		 8712019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
872
873 * riscv-opc.c (riscv_opcodes): Change subset field
874 to insn_class field for all instructions.
875 (riscv_insn_types): Likewise.
876
bb695960
PB		 8772019-09-16 Phil Blundell <pb@pbcl.net>
878
879 * configure: Regenerated.
880
8063ab7e
MV		 8812019-09-10 Miod Vallat <miod@online.fr>
882
883 PR 24982
884 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
885
60391a25
PB		 8862019-09-09 Phil Blundell <pb@pbcl.net>
887
888 binutils 2.33 branch created.
889
f44b758d
NC		 8902019-09-03 Nick Clifton <nickc@redhat.com>
891
892 PR 24961
893 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
894 greater than zero before indexing via (bufcnt -1).
895
1e4b5e7d
NC		 8962019-09-03 Nick Clifton <nickc@redhat.com>
897
898 PR 24958
899 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
900 (MAX_SPEC_REG_NAME_LEN): Define.
901 (struct mmix_dis_info): Use defined constants for array lengths.
902 (get_reg_name): New function.
903 (get_sprec_reg_name): New function.
904 (print_insn_mmix): Use new functions.
905
c4a23bf8
SP		 9062019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
907
908 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
909 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
910 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
911
a051e2f3
KT		 9122019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
913
914 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
915 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
916 (aarch64_sys_reg_supported_p): Update checks for the above.
917
08132bdd
SP		 9182019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
919
920 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
921 cases MVE_SQRSHRL and MVE_UQRSHLL.
922 (print_insn_mve): Add case for specifier 'k' to check
923 specific bit of the instruction.
924
d88bdcb4
PA		 9252019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
926
927 PR 24854
928 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
929 encountering an unknown machine type.
930 (print_insn_arc): Handle arc_insn_length returning 0. In error
931 cases return -1 rather than calling abort.
932
bc750500
JB		 9332019-08-07 Jan Beulich <jbeulich@suse.com>
934
935 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
936 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
937 IgnoreSize.
938 * i386-tbl.h: Re-generate.
939
23d188c7
BW		 9402019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
941
942 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
943 instructions.
944
c0d6f62f
JW		 9452019-07-30 Mel Chen <mel.chen@sifive.com>
946
947 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
948 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
949
950 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
951 fscsr.
952
0f3f7167
CZ		 9532019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
954
955 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
956 and MPY class instructions.
957 (parse_option): Add nps400 option.
958 (print_arc_disassembler_options): Add nps400 info.
959
7e126ba3
CZ		 9602019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
961
962 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
963 (bspop): Likewise.
964 (modapp): Likewise.
965 * arc-opc.c (RAD_CHK): Add.
966 * arc-tbl.h: Regenerate.
967
a028026d
KT		 9682019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
969
970 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
971 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
972
ac79ff9e
NC		 9732019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
974
975 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
976 instructions as UNPREDICTABLE.
977
231097b0
JM		 9782019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
979
980 * bpf-desc.c: Regenerated.
981
1d942ae9
JB		 9822019-07-17 Jan Beulich <jbeulich@suse.com>
983
984 * i386-gen.c (static_assert): Define.
985 (main): Use it.
986 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
987 (Opcode_Modifier_Num): ... this.
988 (Mem): Delete.
989
dfd69174
JB		 9902019-07-16 Jan Beulich <jbeulich@suse.com>
991
992 * i386-gen.c (operand_types): Move RegMem ...
993 (opcode_modifiers): ... here.
994 * i386-opc.h (RegMem): Move to opcode modifer enum.
995 (union i386_operand_type): Move regmem field ...
996 (struct i386_opcode_modifier): ... here.
997 * i386-opc.tbl (RegMem): Define.
998 (mov, movq): Move RegMem on segment, control, debug, and test
999 register flavors.
1000 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1001 to non-SSE2AVX flavor.
1002 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1003 Move RegMem on register only flavors. Drop IgnoreSize from
1004 legacy encoding flavors.
1005 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1006 flavors.
1007 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1008 register only flavors.
1009 (vmovd): Move RegMem and drop IgnoreSize on register only
1010 flavor. Change opcode and operand order to store form.
1011 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1012
21df382b
JB		 10132019-07-16 Jan Beulich <jbeulich@suse.com>
1014
1015 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1016 entries.
1017 * i386-opc.h (SReg2, SReg3): Replace by ...
1018 (SReg): ... this.
1019 (union i386_operand_type): Replace sreg fields.
1020 * i386-opc.tbl (mov, ): Use SReg.
1021 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1022 register flavors.
1023 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1024 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1025
3719fd55
JM		 10262019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1027
1028 * bpf-desc.c: Regenerate.
1029 * bpf-opc.c: Likewise.
1030 * bpf-opc.h: Likewise.
1031
92434a14
JM		 10322019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1033
1034 * bpf-desc.c: Regenerate.
1035 * bpf-opc.c: Likewise.
1036
43dd7626
HPN		 10372019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1038
1039 * arm-dis.c (print_insn_coprocessor): Rename index to
1040 index_operand.
1041
98602811
JW		 10422019-07-05 Kito Cheng <kito.cheng@sifive.com>
1043
1044 * riscv-opc.c (riscv_insn_types): Add r4 type.
1045
1046 * riscv-opc.c (riscv_insn_types): Add b and j type.
1047
1048 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1049 format for sb type and correct s type.
1050
01c1ee4a
RS		 10512019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1052
1053 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1054 SVE FMOV alias of FCPY.
1055
83adff69
RS		 10562019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1057
1058 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1059 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1060
89418844
RS		 10612019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1062
1063 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1064 registers in an instruction prefixed by MOVPRFX.
1065
41be57ca
MM		 10662019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1067
1068 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1069 sve_size_13 icode to account for variant behaviour of
1070 pmull{t,b}.
1071 * aarch64-dis-2.c: Regenerate.
1072 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1073 sve_size_13 icode to account for variant behaviour of
1074 pmull{t,b}.
1075 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1076 (OP_SVE_VVV_Q_D): Add new qualifier.
1077 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1078 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1079 AES and those not.
1080
9d3bf266
JB		 10812019-07-01 Jan Beulich <jbeulich@suse.com>
1082
1083 * opcodes/i386-gen.c (operand_type_init): Remove
1084 OPERAND_TYPE_VEC_IMM4 entry.
1085 (operand_types): Remove Vec_Imm4.
1086 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1087 (union i386_operand_type): Remove vec_imm4.
1088 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1089 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1090
c3949f43
JB		 10912019-07-01 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1094 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1095 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1096 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1097 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1098 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1099 * i386-tbl.h: Re-generate.
1100
5641ec01
JB		 11012019-07-01 Jan Beulich <jbeulich@suse.com>
1102
1103 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1104 register operands.
1105 * i386-tbl.h: Re-generate.
1106
79dec6b7
JB		 11072019-07-01 Jan Beulich <jbeulich@suse.com>
1108
1109 * i386-opc.tbl (C): New.
1110 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1111 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1112 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1113 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1114 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1115 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1116 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1117 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1118 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1119 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1120 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1121 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1122 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1123 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1124 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1125 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1126 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1127 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1128 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1129 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1130 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1131 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1132 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1133 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1134 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1135 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1136 flavors.
1137 * i386-tbl.h: Re-generate.
1138
a0a1771e
JB		 11392019-07-01 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1142 register operands.
1143 * i386-tbl.h: Re-generate.
1144
cd546e7b
JB		 11452019-07-01 Jan Beulich <jbeulich@suse.com>
1146
1147 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1148 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1149 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1150 * i386-tbl.h: Re-generate.
1151
e3bba3fc
JB		 11522019-07-01 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1155 Disp8MemShift from register only templates.
1156 * i386-tbl.h: Re-generate.
1157
36cc073e
JB		 11582019-07-01 Jan Beulich <jbeulich@suse.com>
1159
1160 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1161 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1162 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1163 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1164 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1165 EVEX_W_0F11_P_3_M_1): Delete.
1166 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1167 EVEX_W_0F11_P_3): New.
1168 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1169 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1170 MOD_EVEX_0F11_PREFIX_3 table entries.
1171 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1172 PREFIX_EVEX_0F11 table entries.
1173 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1174 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1175 EVEX_W_0F11_P_3_M_{0,1} table entries.
1176
219920a7
JB		 11772019-07-01 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1180 Delete.
1181
e395f487
L		 11822019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1183
1184 PR binutils/24719
1185 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1186 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1187 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1188 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1189 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1190 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1191 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1192 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1193 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1194 PREFIX_EVEX_0F38C6_REG_6 entries.
1195 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1196 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1197 EVEX_W_0F38C7_R_6_P_2 entries.
1198 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1199 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1200 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1201 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1202 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1203 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1204 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1205
2b7bcc87
JB		 12062019-06-27 Jan Beulich <jbeulich@suse.com>
1207
1208 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1209 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1210 VEX_LEN_0F2D_P_3): Delete.
1211 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1212 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1213 (prefix_table): ... here.
1214
c1dc7af5
JB		 12152019-06-27 Jan Beulich <jbeulich@suse.com>
1216
1217 * i386-dis.c (Iq): Delete.
1218 (Id): New.
1219 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1220 TBM insns.
1221 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1222 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1223 (OP_E_memory): Also honor needindex when deciding whether an
1224 address size prefix needs printing.
1225 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1226
d7560e2d
JW		 12272019-06-26 Jim Wilson <jimw@sifive.com>
1228
1229 PR binutils/24739
1230 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1231 Set info->display_endian to info->endian_code.
1232
2c703856
JB		 12332019-06-25 Jan Beulich <jbeulich@suse.com>
1234
1235 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1236 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1237 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1238 OPERAND_TYPE_ACC64 entries.
1239 * i386-init.h: Re-generate.
1240
54fbadc0
JB		 12412019-06-25 Jan Beulich <jbeulich@suse.com>
1242
1243 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1244 Delete.
1245 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1246 of dqa_mode.
1247 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1248 entries here.
1249 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1250 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1251
a280ab8e
JB		 12522019-06-25 Jan Beulich <jbeulich@suse.com>
1253
1254 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1255 variables.
1256
e1a1babd
JB		 12572019-06-25 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1260 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1261 movnti.
d7560e2d 1262 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1263 * i386-tbl.h: Re-generate.
1264
b8364fa7
JB		 12652019-06-25 Jan Beulich <jbeulich@suse.com>
1266
1267 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1268 * i386-tbl.h: Re-generate.
1269
ad692897
L		 12702019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1271
1272 * i386-dis-evex.h: Break into ...
1273 * i386-dis-evex-len.h: New file.
1274 * i386-dis-evex-mod.h: Likewise.
1275 * i386-dis-evex-prefix.h: Likewise.
1276 * i386-dis-evex-reg.h: Likewise.
1277 * i386-dis-evex-w.h: Likewise.
1278 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1279 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1280 i386-dis-evex-mod.h.
1281
f0a6222e
L		 12822019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1283
1284 PR binutils/24700
1285 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1286 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1287 EVEX_W_0F385B_P_2.
1288 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1289 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1290 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1291 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1292 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1293 EVEX_LEN_0F385B_P_2_W_1.
1294 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1295 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1296 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1297 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1298 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1299 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1300 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1301 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1302 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1303 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1304
6e1c90b7
L		 13052019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1306
1307 PR binutils/24691
1308 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1309 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1310 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1311 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1312 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1313 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1314 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1315 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1316 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1317 EVEX_LEN_0F3A43_P_2_W_1.
1318 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1319 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1320 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1321 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1322 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1323 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1324 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1325 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1326 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1327 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1328 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1329 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1330
bcc5a6eb
NC		 13312019-06-14 Nick Clifton <nickc@redhat.com>
1332
1333 * po/fr.po; Updated French translation.
1334
e4c4ac46
SH		 13352019-06-13 Stafford Horne <shorne@gmail.com>
1336
1337 * or1k-asm.c: Regenerated.
1338 * or1k-desc.c: Regenerated.
1339 * or1k-desc.h: Regenerated.
1340 * or1k-dis.c: Regenerated.
1341 * or1k-ibld.c: Regenerated.
1342 * or1k-opc.c: Regenerated.
1343 * or1k-opc.h: Regenerated.
1344 * or1k-opinst.c: Regenerated.
1345
a0e44ef5
PB		 13462019-06-12 Peter Bergner <bergner@linux.ibm.com>
1347
1348 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1349
12efd68d
L		 13502019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1351
1352 PR binutils/24633
1353 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1354 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1355 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1356 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1357 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1358 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1359 EVEX_LEN_0F3A1B_P_2_W_1.
1360 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1361 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1362 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1363 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1364 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1365 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1366 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1367 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1368
63c6fc6c
L		 13692019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1370
1371 PR binutils/24626
1372 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1373 EVEX.vvvv when disassembling VEX and EVEX instructions.
1374 (OP_VEX): Set vex.register_specifier to 0 after readding
1375 vex.register_specifier.
1376 (OP_Vex_2src_1): Likewise.
1377 (OP_Vex_2src_2): Likewise.
1378 (OP_LWP_E): Likewise.
1379 (OP_EX_Vex): Don't check vex.register_specifier.
1380 (OP_XMM_Vex): Likewise.
1381
9186c494
L		 13822019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1383 Lili Cui <lili.cui@intel.com>
1384
1385 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1386 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1387 instructions.
1388 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1389 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1390 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1391 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1392 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1393 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1394 * i386-init.h: Regenerated.
1395 * i386-tbl.h: Likewise.
1396
5d79adc4
L		 13972019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1398 Lili Cui <lili.cui@intel.com>
1399
1400 * doc/c-i386.texi: Document enqcmd.
1401 * testsuite/gas/i386/enqcmd-intel.d: New file.
1402 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1403 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1404 * testsuite/gas/i386/enqcmd.d: Likewise.
1405 * testsuite/gas/i386/enqcmd.s: Likewise.
1406 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1407 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1408 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1409 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1410 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1411 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1412 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1413 and x86-64-enqcmd.
1414
a9d96ab9
AH		 14152019-06-04 Alan Hayward <alan.hayward@arm.com>
1416
1417 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1418
4f6d070a
AM		 14192019-06-03 Alan Modra <amodra@gmail.com>
1420
1421 * ppc-dis.c (prefix_opcd_indices): Correct size.
1422
a2f4b66c
L		 14232019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1424
1425 PR gas/24625
1426 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1427 Disp8ShiftVL.
1428 * i386-tbl.h: Regenerated.
1429
405b5bd8
AM		 14302019-05-24 Alan Modra <amodra@gmail.com>
1431
1432 * po/POTFILES.in: Regenerate.
1433
8acf1435
PB		 14342019-05-24 Peter Bergner <bergner@linux.ibm.com>
1435 Alan Modra <amodra@gmail.com>
1436
1437 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1438 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1439 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1440 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1441 XTOP>): Define and add entries.
1442 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1443 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1444 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1445 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1446
dd7efa79
PB		 14472019-05-24 Peter Bergner <bergner@linux.ibm.com>
1448 Alan Modra <amodra@gmail.com>
1449
1450 * ppc-dis.c (ppc_opts): Add "future" entry.
1451 (PREFIX_OPCD_SEGS): Define.
1452 (prefix_opcd_indices): New array.
1453 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1454 (lookup_prefix): New function.
1455 (print_insn_powerpc): Handle 64-bit prefix instructions.
1456 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1457 (PMRR, POWERXX): Define.
1458 (prefix_opcodes): New instruction table.
1459 (prefix_num_opcodes): New constant.
1460
79472b45
JM		 14612019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1462
1463 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1464 * configure: Regenerated.
1465 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1466 and cpu/bpf.opc.
1467 (HFILES): Add bpf-desc.h and bpf-opc.h.
1468 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1469 bpf-ibld.c and bpf-opc.c.
1470 (BPF_DEPS): Define.
1471 * Makefile.in: Regenerated.
1472 * disassemble.c (ARCH_bpf): Define.
1473 (disassembler): Add case for bfd_arch_bpf.
1474 (disassemble_init_for_target): Likewise.
1475 (enum epbf_isa_attr): Define.
1476 * disassemble.h: extern print_insn_bpf.
1477 * bpf-asm.c: Generated.
1478 * bpf-opc.h: Likewise.
1479 * bpf-opc.c: Likewise.
1480 * bpf-ibld.c: Likewise.
1481 * bpf-dis.c: Likewise.
1482 * bpf-desc.h: Likewise.
1483 * bpf-desc.c: Likewise.
1484
ba6cd17f
SD		 14852019-05-21 Sudakshina Das <sudi.das@arm.com>
1486
1487 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1488 and VMSR with the new operands.
1489
e39c1607
SD		 14902019-05-21 Sudakshina Das <sudi.das@arm.com>
1491
1492 * arm-dis.c (enum mve_instructions): New enum
1493 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1494 and cneg.
1495 (mve_opcodes): New instructions as above.
1496 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1497 csneg and csel.
1498 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1499
23d00a41
SD		 15002019-05-21 Sudakshina Das <sudi.das@arm.com>
1501
1502 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1503 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1504 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1505 uqshl, urshrl and urshr.
1506 (is_mve_okay_in_it): Add new instructions to TRUE list.
1507 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1508 (print_insn_mve): Updated to accept new %j,
1509 %<bitfield>m and %<bitfield>n patterns.
1510
cd4797ee
FS		 15112019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1512
1513 * mips-opc.c (mips_builtin_opcodes): Change source register
1514 constraint for DAUI.
1515
999b073b
NC		 15162019-05-20 Nick Clifton <nickc@redhat.com>
1517
1518 * po/fr.po: Updated French translation.
1519
14b456f2
AV		 15202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1521 Michael Collison <michael.collison@arm.com>
1522
1523 * arm-dis.c (thumb32_opcodes): Add new instructions.
1524 (enum mve_instructions): Likewise.
1525 (enum mve_undefined): Add new reasons.
1526 (is_mve_encoding_conflict): Handle new instructions.
1527 (is_mve_undefined): Likewise.
1528 (is_mve_unpredictable): Likewise.
1529 (print_mve_undefined): Likewise.
1530 (print_mve_size): Likewise.
1531
f49bb598
AV		 15322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1533 Michael Collison <michael.collison@arm.com>
1534
1535 * arm-dis.c (thumb32_opcodes): Add new instructions.
1536 (enum mve_instructions): Likewise.
1537 (is_mve_encoding_conflict): Handle new instructions.
1538 (is_mve_undefined): Likewise.
1539 (is_mve_unpredictable): Likewise.
1540 (print_mve_size): Likewise.
1541
56858bea
AV		 15422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1543 Michael Collison <michael.collison@arm.com>
1544
1545 * arm-dis.c (thumb32_opcodes): Add new instructions.
1546 (enum mve_instructions): Likewise.
1547 (is_mve_encoding_conflict): Likewise.
1548 (is_mve_unpredictable): Likewise.
1549 (print_mve_size): Likewise.
1550
e523f101
AV		 15512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1552 Michael Collison <michael.collison@arm.com>
1553
1554 * arm-dis.c (thumb32_opcodes): Add new instructions.
1555 (enum mve_instructions): Likewise.
1556 (is_mve_encoding_conflict): Handle new instructions.
1557 (is_mve_undefined): Likewise.
1558 (is_mve_unpredictable): Likewise.
1559 (print_mve_size): Likewise.
1560
66dcaa5d
AV		 15612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1562 Michael Collison <michael.collison@arm.com>
1563
1564 * arm-dis.c (thumb32_opcodes): Add new instructions.
1565 (enum mve_instructions): Likewise.
1566 (is_mve_encoding_conflict): Handle new instructions.
1567 (is_mve_undefined): Likewise.
1568 (is_mve_unpredictable): Likewise.
1569 (print_mve_size): Likewise.
1570 (print_insn_mve): Likewise.
1571
d052b9b7
AV		 15722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1573 Michael Collison <michael.collison@arm.com>
1574
1575 * arm-dis.c (thumb32_opcodes): Add new instructions.
1576 (print_insn_thumb32): Handle new instructions.
1577
ed63aa17
AV		 15782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1579 Michael Collison <michael.collison@arm.com>
1580
1581 * arm-dis.c (enum mve_instructions): Add new instructions.
1582 (enum mve_undefined): Add new reasons.
1583 (is_mve_encoding_conflict): Handle new instructions.
1584 (is_mve_undefined): Likewise.
1585 (is_mve_unpredictable): Likewise.
1586 (print_mve_undefined): Likewise.
1587 (print_mve_size): Likewise.
1588 (print_mve_shift_n): Likewise.
1589 (print_insn_mve): Likewise.
1590
897b9bbc
AV		 15912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1593
1594 * arm-dis.c (enum mve_instructions): Add new instructions.
1595 (is_mve_encoding_conflict): Handle new instructions.
1596 (is_mve_unpredictable): Likewise.
1597 (print_mve_rotate): Likewise.
1598 (print_mve_size): Likewise.
1599 (print_insn_mve): Likewise.
1600
1c8f2df8
AV		 16012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1603
1604 * arm-dis.c (enum mve_instructions): Add new instructions.
1605 (is_mve_encoding_conflict): Handle new instructions.
1606 (is_mve_unpredictable): Likewise.
1607 (print_mve_size): Likewise.
1608 (print_insn_mve): Likewise.
1609
d3b63143
AV		 16102019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1611 Michael Collison <michael.collison@arm.com>
1612
1613 * arm-dis.c (enum mve_instructions): Add new instructions.
1614 (enum mve_undefined): Add new reasons.
1615 (is_mve_encoding_conflict): Handle new instructions.
1616 (is_mve_undefined): Likewise.
1617 (is_mve_unpredictable): Likewise.
1618 (print_mve_undefined): Likewise.
1619 (print_mve_size): Likewise.
1620 (print_insn_mve): Likewise.
1621
14925797
AV		 16222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1623 Michael Collison <michael.collison@arm.com>
1624
1625 * arm-dis.c (enum mve_instructions): Add new instructions.
1626 (is_mve_encoding_conflict): Handle new instructions.
1627 (is_mve_undefined): Likewise.
1628 (is_mve_unpredictable): Likewise.
1629 (print_mve_size): Likewise.
1630 (print_insn_mve): Likewise.
1631
c507f10b
AV		 16322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1633 Michael Collison <michael.collison@arm.com>
1634
1635 * arm-dis.c (enum mve_instructions): Add new instructions.
1636 (enum mve_unpredictable): Add new reasons.
1637 (enum mve_undefined): Likewise.
1638 (is_mve_okay_in_it): Handle new isntructions.
1639 (is_mve_encoding_conflict): Likewise.
1640 (is_mve_undefined): Likewise.
1641 (is_mve_unpredictable): Likewise.
1642 (print_mve_vmov_index): Likewise.
1643 (print_simd_imm8): Likewise.
1644 (print_mve_undefined): Likewise.
1645 (print_mve_unpredictable): Likewise.
1646 (print_mve_size): Likewise.
1647 (print_insn_mve): Likewise.
1648
bf0b396d
AV		 16492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1650 Michael Collison <michael.collison@arm.com>
1651
1652 * arm-dis.c (enum mve_instructions): Add new instructions.
1653 (enum mve_unpredictable): Add new reasons.
1654 (enum mve_undefined): Likewise.
1655 (is_mve_encoding_conflict): Handle new instructions.
1656 (is_mve_undefined): Likewise.
1657 (is_mve_unpredictable): Likewise.
1658 (print_mve_undefined): Likewise.
1659 (print_mve_unpredictable): Likewise.
1660 (print_mve_rounding_mode): Likewise.
1661 (print_mve_vcvt_size): Likewise.
1662 (print_mve_size): Likewise.
1663 (print_insn_mve): Likewise.
1664
ef1576a1
AV		 16652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1666 Michael Collison <michael.collison@arm.com>
1667
1668 * arm-dis.c (enum mve_instructions): Add new instructions.
1669 (enum mve_unpredictable): Add new reasons.
1670 (enum mve_undefined): Likewise.
1671 (is_mve_undefined): Handle new instructions.
1672 (is_mve_unpredictable): Likewise.
1673 (print_mve_undefined): Likewise.
1674 (print_mve_unpredictable): Likewise.
1675 (print_mve_size): Likewise.
1676 (print_insn_mve): Likewise.
1677
aef6d006
AV		 16782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1679 Michael Collison <michael.collison@arm.com>
1680
1681 * arm-dis.c (enum mve_instructions): Add new instructions.
1682 (enum mve_undefined): Add new reasons.
1683 (insns): Add new instructions.
1684 (is_mve_encoding_conflict):
1685 (print_mve_vld_str_addr): New print function.
1686 (is_mve_undefined): Handle new instructions.
1687 (is_mve_unpredictable): Likewise.
1688 (print_mve_undefined): Likewise.
1689 (print_mve_size): Likewise.
1690 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1691 (print_insn_mve): Handle new operands.
1692
04d54ace
AV		 16932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1694 Michael Collison <michael.collison@arm.com>
1695
1696 * arm-dis.c (enum mve_instructions): Add new instructions.
1697 (enum mve_unpredictable): Add new reasons.
1698 (is_mve_encoding_conflict): Handle new instructions.
1699 (is_mve_unpredictable): Likewise.
1700 (mve_opcodes): Add new instructions.
1701 (print_mve_unpredictable): Handle new reasons.
1702 (print_mve_register_blocks): New print function.
1703 (print_mve_size): Handle new instructions.
1704 (print_insn_mve): Likewise.
1705
9743db03
AV		 17062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1707 Michael Collison <michael.collison@arm.com>
1708
1709 * arm-dis.c (enum mve_instructions): Add new instructions.
1710 (enum mve_unpredictable): Add new reasons.
1711 (enum mve_undefined): Likewise.
1712 (is_mve_encoding_conflict): Handle new instructions.
1713 (is_mve_undefined): Likewise.
1714 (is_mve_unpredictable): Likewise.
1715 (coprocessor_opcodes): Move NEON VDUP from here...
1716 (neon_opcodes): ... to here.
1717 (mve_opcodes): Add new instructions.
1718 (print_mve_undefined): Handle new reasons.
1719 (print_mve_unpredictable): Likewise.
1720 (print_mve_size): Handle new instructions.
1721 (print_insn_neon): Handle vdup.
1722 (print_insn_mve): Handle new operands.
1723
143275ea
AV		 17242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1725 Michael Collison <michael.collison@arm.com>
1726
1727 * arm-dis.c (enum mve_instructions): Add new instructions.
1728 (enum mve_unpredictable): Add new values.
1729 (mve_opcodes): Add new instructions.
1730 (vec_condnames): New array with vector conditions.
1731 (mve_predicatenames): New array with predicate suffixes.
1732 (mve_vec_sizename): New array with vector sizes.
1733 (enum vpt_pred_state): New enum with vector predication states.
1734 (struct vpt_block): New struct type for vpt blocks.
1735 (vpt_block_state): Global struct to keep track of state.
1736 (mve_extract_pred_mask): New helper function.
1737 (num_instructions_vpt_block): Likewise.
1738 (mark_outside_vpt_block): Likewise.
1739 (mark_inside_vpt_block): Likewise.
1740 (invert_next_predicate_state): Likewise.
1741 (update_next_predicate_state): Likewise.
1742 (update_vpt_block_state): Likewise.
1743 (is_vpt_instruction): Likewise.
1744 (is_mve_encoding_conflict): Add entries for new instructions.
1745 (is_mve_unpredictable): Likewise.
1746 (print_mve_unpredictable): Handle new cases.
1747 (print_instruction_predicate): Likewise.
1748 (print_mve_size): New function.
1749 (print_vec_condition): New function.
1750 (print_insn_mve): Handle vpt blocks and new print operands.
1751
f08d8ce3
AV		 17522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1753
1754 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1755 8, 14 and 15 for Armv8.1-M Mainline.
1756
73cd51e5
AV		 17572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1758 Michael Collison <michael.collison@arm.com>
1759
1760 * arm-dis.c (enum mve_instructions): New enum.
1761 (enum mve_unpredictable): Likewise.
1762 (enum mve_undefined): Likewise.
1763 (struct mopcode32): New struct.
1764 (is_mve_okay_in_it): New function.
1765 (is_mve_architecture): Likewise.
1766 (arm_decode_field): Likewise.
1767 (arm_decode_field_multiple): Likewise.
1768 (is_mve_encoding_conflict): Likewise.
1769 (is_mve_undefined): Likewise.
1770 (is_mve_unpredictable): Likewise.
1771 (print_mve_undefined): Likewise.
1772 (print_mve_unpredictable): Likewise.
1773 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1774 (print_insn_mve): New function.
1775 (print_insn_thumb32): Handle MVE architecture.
1776 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1777
3076e594
NC		 17782019-05-10 Nick Clifton <nickc@redhat.com>
1779
1780 PR 24538
1781 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1782 end of the table prematurely.
1783
387e7624
FS		 17842019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1785
1786 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1787 macros for R6.
1788
0067be51
AM		 17892019-05-11 Alan Modra <amodra@gmail.com>
1790
1791 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1792 when -Mraw is in effect.
1793
42e6288f
MM		 17942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1795
1796 * aarch64-dis-2.c: Regenerate.
1797 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1798 (OP_SVE_BBB): New variant set.
1799 (OP_SVE_DDDD): New variant set.
1800 (OP_SVE_HHH): New variant set.
1801 (OP_SVE_HHHU): New variant set.
1802 (OP_SVE_SSS): New variant set.
1803 (OP_SVE_SSSU): New variant set.
1804 (OP_SVE_SHH): New variant set.
1805 (OP_SVE_SBBU): New variant set.
1806 (OP_SVE_DSS): New variant set.
1807 (OP_SVE_DHHU): New variant set.
1808 (OP_SVE_VMV_HSD_BHS): New variant set.
1809 (OP_SVE_VVU_HSD_BHS): New variant set.
1810 (OP_SVE_VVVU_SD_BH): New variant set.
1811 (OP_SVE_VVVU_BHSD): New variant set.
1812 (OP_SVE_VVV_QHD_DBS): New variant set.
1813 (OP_SVE_VVV_HSD_BHS): New variant set.
1814 (OP_SVE_VVV_HSD_BHS2): New variant set.
1815 (OP_SVE_VVV_BHS_HSD): New variant set.
1816 (OP_SVE_VV_BHS_HSD): New variant set.
1817 (OP_SVE_VVV_SD): New variant set.
1818 (OP_SVE_VVU_BHS_HSD): New variant set.
1819 (OP_SVE_VZVV_SD): New variant set.
1820 (OP_SVE_VZVV_BH): New variant set.
1821 (OP_SVE_VZV_SD): New variant set.
1822 (aarch64_opcode_table): Add sve2 instructions.
1823
28ed815a
MM		 18242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1825
1826 * aarch64-asm-2.c: Regenerated.
1827 * aarch64-dis-2.c: Regenerated.
1828 * aarch64-opc-2.c: Regenerated.
1829 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1830 for SVE_SHLIMM_UNPRED_22.
1831 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1832 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1833 operand.
1834
fd1dc4a0
MM		 18352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1836
1837 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1838 sve_size_tsz_bhs iclass encode.
1839 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1840 sve_size_tsz_bhs iclass decode.
1841
31e36ab3
MM		 18422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1843
1844 * aarch64-asm-2.c: Regenerated.
1845 * aarch64-dis-2.c: Regenerated.
1846 * aarch64-opc-2.c: Regenerated.
1847 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1848 for SVE_Zm4_11_INDEX.
1849 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1850 (fields): Handle SVE_i2h field.
1851 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1852 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1853
1be5f94f
MM		 18542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1855
1856 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1857 sve_shift_tsz_bhsd iclass encode.
1858 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1859 sve_shift_tsz_bhsd iclass decode.
1860
3c17238b
MM		 18612019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1862
1863 * aarch64-asm-2.c: Regenerated.
1864 * aarch64-dis-2.c: Regenerated.
1865 * aarch64-opc-2.c: Regenerated.
1866 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1867 (aarch64_encode_variant_using_iclass): Handle
1868 sve_shift_tsz_hsd iclass encode.
1869 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1870 sve_shift_tsz_hsd iclass decode.
1871 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1872 for SVE_SHRIMM_UNPRED_22.
1873 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1874 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1875 operand.
1876
cd50a87a
MM		 18772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1878
1879 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1880 sve_size_013 iclass encode.
1881 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1882 sve_size_013 iclass decode.
1883
3c705960
MM		 18842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1885
1886 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1887 sve_size_bh iclass encode.
1888 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1889 sve_size_bh iclass decode.
1890
0a57e14f
MM		 18912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1892
1893 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1894 sve_size_sd2 iclass encode.
1895 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1896 sve_size_sd2 iclass decode.
1897 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1898 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1899
c469c864
MM		 19002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1901
1902 * aarch64-asm-2.c: Regenerated.
1903 * aarch64-dis-2.c: Regenerated.
1904 * aarch64-opc-2.c: Regenerated.
1905 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1906 for SVE_ADDR_ZX.
1907 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1908 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1909
116adc27
MM		 19102019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1911
1912 * aarch64-asm-2.c: Regenerated.
1913 * aarch64-dis-2.c: Regenerated.
1914 * aarch64-opc-2.c: Regenerated.
1915 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1916 for SVE_Zm3_11_INDEX.
1917 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1918 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1919 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1920 fields.
1921 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1922
3bd82c86
MM		 19232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1924
1925 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1926 sve_size_hsd2 iclass encode.
1927 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1928 sve_size_hsd2 iclass decode.
1929 * aarch64-opc.c (fields): Handle SVE_size field.
1930 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1931
adccc507
MM		 19322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1933
1934 * aarch64-asm-2.c: Regenerated.
1935 * aarch64-dis-2.c: Regenerated.
1936 * aarch64-opc-2.c: Regenerated.
1937 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1938 for SVE_IMM_ROT3.
1939 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1940 (fields): Handle SVE_rot3 field.
1941 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1942 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1943
5cd99750
MM		 19442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1945
1946 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1947 instructions.
1948
7ce2460a
MM		 19492019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1950
1951 * aarch64-tbl.h
1952 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1953 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1954 aarch64_feature_sve2bitperm): New feature sets.
1955 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1956 for feature set addresses.
1957 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1958 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1959
41cee089
FS		 19602019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1961 Faraz Shahbazker <fshahbazker@wavecomp.com>
1962
1963 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1964 argument and set ASE_EVA_R6 appropriately.
1965 (set_default_mips_dis_options): Pass ISA to above.
1966 (parse_mips_dis_option): Likewise.
1967 * mips-opc.c (EVAR6): New macro.
1968 (mips_builtin_opcodes): Add llwpe, scwpe.
1969
b83b4b13
SD		 19702019-05-01 Sudakshina Das <sudi.das@arm.com>
1971
1972 * aarch64-asm-2.c: Regenerated.
1973 * aarch64-dis-2.c: Regenerated.
1974 * aarch64-opc-2.c: Regenerated.
1975 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1976 AARCH64_OPND_TME_UIMM16.
1977 (aarch64_print_operand): Likewise.
1978 * aarch64-tbl.h (QL_IMM_NIL): New.
1979 (TME): New.
1980 (_TME_INSN): New.
1981 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1982
4a90ce95
JD		 19832019-04-29 John Darrington <john@darrington.wattle.id.au>
1984
1985 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1986
a45328b9
AB		 19872019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1988 Faraz Shahbazker <fshahbazker@wavecomp.com>
1989
1990 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1991
d10be0cb
JD		 19922019-04-24 John Darrington <john@darrington.wattle.id.au>
1993
1994 * s12z-opc.h: Add extern "C" bracketing to help
1995 users who wish to use this interface in c++ code.
1996
a679f24e
JD		 19972019-04-24 John Darrington <john@darrington.wattle.id.au>
1998
1999 * s12z-opc.c (bm_decode): Handle bit map operations with the
2000 "reserved0" mode.
2001
32c36c3c
AV		 20022019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2003
2004 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2005 specifier. Add entries for VLDR and VSTR of system registers.
2006 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2007 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2008 of %J and %K format specifier.
2009
efd6b359
AV		 20102019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2011
2012 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2013 Add new entries for VSCCLRM instruction.
2014 (print_insn_coprocessor): Handle new %C format control code.
2015
6b0dd094
AV		 20162019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2017
2018 * arm-dis.c (enum isa): New enum.
2019 (struct sopcode32): New structure.
2020 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2021 set isa field of all current entries to ANY.
2022 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2023 Only match an entry if its isa field allows the current mode.
2024
4b5a202f
AV		 20252019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2026
2027 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2028 CLRM.
2029 (print_insn_thumb32): Add logic to print %n CLRM register list.
2030
60f993ce
AV		 20312019-04-15 Sudakshina Das <sudi.das@arm.com>
2032
2033 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2034 and %Q patterns.
2035
f6b2b12d
AV		 20362019-04-15 Sudakshina Das <sudi.das@arm.com>
2037
2038 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2039 (print_insn_thumb32): Edit the switch case for %Z.
2040
1889da70
AV		 20412019-04-15 Sudakshina Das <sudi.das@arm.com>
2042
2043 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2044
65d1bc05
AV		 20452019-04-15 Sudakshina Das <sudi.das@arm.com>
2046
2047 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2048
1caf72a5
AV		 20492019-04-15 Sudakshina Das <sudi.das@arm.com>
2050
2051 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2052
f1c7f421
AV		 20532019-04-15 Sudakshina Das <sudi.das@arm.com>
2054
2055 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2056 Arm register with r13 and r15 unpredictable.
2057 (thumb32_opcodes): New instructions for bfx and bflx.
2058
4389b29a
AV		 20592019-04-15 Sudakshina Das <sudi.das@arm.com>
2060
2061 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2062
e5d6e09e
AV		 20632019-04-15 Sudakshina Das <sudi.das@arm.com>
2064
2065 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2066
e12437dc
AV		 20672019-04-15 Sudakshina Das <sudi.das@arm.com>
2068
2069 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2070
031254f2
AV		 20712019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2072
2073 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2074
e5a557ac
JD		 20752019-04-12 John Darrington <john@darrington.wattle.id.au>
2076
2077 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2078 "optr". ("operator" is a reserved word in c++).
2079
bd7ceb8d
SD		 20802019-04-11 Sudakshina Das <sudi.das@arm.com>
2081
2082 * aarch64-opc.c (aarch64_print_operand): Add case for
2083 AARCH64_OPND_Rt_SP.
2084 (verify_constraints): Likewise.
2085 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2086 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2087 to accept Rt|SP as first operand.
2088 (AARCH64_OPERANDS): Add new Rt_SP.
2089 * aarch64-asm-2.c: Regenerated.
2090 * aarch64-dis-2.c: Regenerated.
2091 * aarch64-opc-2.c: Regenerated.
2092
e54010f1
SD		 20932019-04-11 Sudakshina Das <sudi.das@arm.com>
2094
2095 * aarch64-asm-2.c: Regenerated.
2096 * aarch64-dis-2.c: Likewise.
2097 * aarch64-opc-2.c: Likewise.
2098 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2099
7e96e219
RS		 21002019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2101
2102 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2103
6f2791d5
L		 21042019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2105
2106 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2107 * i386-init.h: Regenerated.
2108
e392bad3
AM		 21092019-04-07 Alan Modra <amodra@gmail.com>
2110
2111 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2112 op_separator to control printing of spaces, comma and parens
2113 rather than need_comma, need_paren and spaces vars.
2114
dffaa15c
AM		 21152019-04-07 Alan Modra <amodra@gmail.com>
2116
2117 PR 24421
2118 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2119 (print_insn_neon, print_insn_arm): Likewise.
2120
d6aab7a1
XG		 21212019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2122
2123 * i386-dis-evex.h (evex_table): Updated to support BF16
2124 instructions.
2125 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2126 and EVEX_W_0F3872_P_3.
2127 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2128 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2129 * i386-opc.h (enum): Add CpuAVX512_BF16.
2130 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2131 * i386-opc.tbl: Add AVX512 BF16 instructions.
2132 * i386-init.h: Regenerated.
2133 * i386-tbl.h: Likewise.
2134
66e85460
AM		 21352019-04-05 Alan Modra <amodra@gmail.com>
2136
2137 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2138 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2139 to favour printing of "-" branch hint when using the "y" bit.
2140 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2141
c2b1c275
AM		 21422019-04-05 Alan Modra <amodra@gmail.com>
2143
2144 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2145 opcode until first operand is output.
2146
aae9718e
PB		 21472019-04-04 Peter Bergner <bergner@linux.ibm.com>
2148
2149 PR gas/24349
2150 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2151 (valid_bo_post_v2): Add support for 'at' branch hints.
2152 (insert_bo): Only error on branch on ctr.
2153 (get_bo_hint_mask): New function.
2154 (insert_boe): Add new 'branch_taken' formal argument. Add support
2155 for inserting 'at' branch hints.
2156 (extract_boe): Add new 'branch_taken' formal argument. Add support
2157 for extracting 'at' branch hints.
2158 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2159 (BOE): Delete operand.
2160 (BOM, BOP): New operands.
2161 (RM): Update value.
2162 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2163 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2164 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2165 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2166 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2167 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2168 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2169 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2170 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2171 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2172 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2173 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2174 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2175 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2176 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2177 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2178 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2179 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2180 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2181 bttarl+>: New extended mnemonics.
2182
96a86c01
AM		 21832019-03-28 Alan Modra <amodra@gmail.com>
2184
2185 PR 24390
2186 * ppc-opc.c (BTF): Define.
2187 (powerpc_opcodes): Use for mtfsb*.
2188 * ppc-dis.c (print_insn_powerpc): Print fields with both
2189 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2190
796d6298
TC		 21912019-03-25 Tamar Christina <tamar.christina@arm.com>
2192
2193 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2194 (mapping_symbol_for_insn): Implement new algorithm.
2195 (print_insn): Remove duplicate code.
2196
60df3720
TC		 21972019-03-25 Tamar Christina <tamar.christina@arm.com>
2198
2199 * aarch64-dis.c (print_insn_aarch64):
2200 Implement override.
2201
51457761
TC		 22022019-03-25 Tamar Christina <tamar.christina@arm.com>
2203
2204 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2205 order.
2206
53b2f36b
TC		 22072019-03-25 Tamar Christina <tamar.christina@arm.com>
2208
2209 * aarch64-dis.c (last_stop_offset): New.
2210 (print_insn_aarch64): Use stop_offset.
2211
89199bb5
L		 22122019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2213
2214 PR gas/24359
2215 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2216 CPU_ANY_AVX2_FLAGS.
2217 * i386-init.h: Regenerated.
2218
97ed31ae
L		 22192019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2220
2221 PR gas/24348
2222 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2223 vmovdqu16, vmovdqu32 and vmovdqu64.
2224 * i386-tbl.h: Regenerated.
2225
0919bfe9
AK		 22262019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2227
2228 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2229 from vstrszb, vstrszh, and vstrszf.
2230
22312019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2232
2233 * s390-opc.txt: Add instruction descriptions.
2234
21820ebe
JW		 22352019-02-08 Jim Wilson <jimw@sifive.com>
2236
2237 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2238 <bne>: Likewise.
2239
f7dd2fb2
TC		 22402019-02-07 Tamar Christina <tamar.christina@arm.com>
2241
2242 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2243
6456d318
TC		 22442019-02-07 Tamar Christina <tamar.christina@arm.com>
2245
2246 PR binutils/23212
2247 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2248 * aarch64-opc.c (verify_elem_sd): New.
2249 (fields): Add FLD_sz entr.
2250 * aarch64-tbl.h (_SIMD_INSN): New.
2251 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2252 fmulx scalar and vector by element isns.
2253
4a83b610
NC		 22542019-02-07 Nick Clifton <nickc@redhat.com>
2255
2256 * po/sv.po: Updated Swedish translation.
2257
fc60b8c8
AK		 22582019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2259
2260 * s390-mkopc.c (main): Accept arch13 as cpu string.
2261 * s390-opc.c: Add new instruction formats and instruction opcode
2262 masks.
2263 * s390-opc.txt: Add new arch13 instructions.
2264
e10620d3
TC		 22652019-01-25 Sudakshina Das <sudi.das@arm.com>
2266
2267 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2268 (aarch64_opcode): Change encoding for stg, stzg
2269 st2g and st2zg.
2270 * aarch64-asm-2.c: Regenerated.
2271 * aarch64-dis-2.c: Regenerated.
2272 * aarch64-opc-2.c: Regenerated.
2273
20a4ca55
SD		 22742019-01-25 Sudakshina Das <sudi.das@arm.com>
2275
2276 * aarch64-asm-2.c: Regenerated.
2277 * aarch64-dis-2.c: Likewise.
2278 * aarch64-opc-2.c: Likewise.
2279 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2280
550fd7bf
SD		 22812019-01-25 Sudakshina Das <sudi.das@arm.com>
2282 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2283
2284 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2285 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2286 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2287 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2288 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2289 case for ldstgv_indexed.
2290 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2291 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2292 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2293 * aarch64-asm-2.c: Regenerated.
2294 * aarch64-dis-2.c: Regenerated.
2295 * aarch64-opc-2.c: Regenerated.
2296
d9938630
NC		 22972019-01-23 Nick Clifton <nickc@redhat.com>
2298
2299 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2300
375cd423
NC		 23012019-01-21 Nick Clifton <nickc@redhat.com>
2302
2303 * po/de.po: Updated German translation.
2304 * po/uk.po: Updated Ukranian translation.
2305
57299f48
CX		 23062019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2307 * mips-dis.c (mips_arch_choices): Fix typo in
2308 gs464, gs464e and gs264e descriptors.
2309
f48dfe41
NC		 23102019-01-19 Nick Clifton <nickc@redhat.com>
2311
2312 * configure: Regenerate.
2313 * po/opcodes.pot: Regenerate.
2314
f974f26c
NC		 23152018-06-24 Nick Clifton <nickc@redhat.com>
2316
2317 2.32 branch created.
2318
39f286cd
JD		 23192019-01-09 John Darrington <john@darrington.wattle.id.au>
2320
448b8ca8
JD		 2321 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2322 if it is null.
2323 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2324 zero.
2325
3107326d
AP		 23262019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2327
2328 * configure: Regenerate.
2329
7e9ca91e
AM		 23302019-01-07 Alan Modra <amodra@gmail.com>
2331
2332 * configure: Regenerate.
2333 * po/POTFILES.in: Regenerate.
2334
ef1ad42b
JD		 23352019-01-03 John Darrington <john@darrington.wattle.id.au>
2336
2337 * s12z-opc.c: New file.
2338 * s12z-opc.h: New file.
2339 * s12z-dis.c: Removed all code not directly related to display
2340 of instructions. Used the interface provided by the new files
2341 instead.
2342 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2343 * Makefile.in: Regenerate.
ef1ad42b 2344 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2345 * configure: Regenerate.
ef1ad42b 2346
82704155
AM		 23472019-01-01 Alan Modra <amodra@gmail.com>
2348
2349 Update year range in copyright notice of all files.
2350
d5c04e1b 2351For older changes see ChangeLog-2018
3499769a 2352\f
d5c04e1b 2353Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2354
2355Copying and distribution of this file, with or without modification,
2356are permitted in any medium without royalty provided the copyright
2357notice and this notice are preserved.
2358
2359Local Variables:
2360mode: change-log
2361left-margin: 8
2362fill-column: 74
2363version-control: never
2364End:
GDB Binutils - Deliverables
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