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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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8063ab7e
MV		 12019-09-10 Miod Vallat <miod@online.fr>
2
3 PR 24982
4 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
5
60391a25
PB		 62019-09-09 Phil Blundell <pb@pbcl.net>
7
8 binutils 2.33 branch created.
9
f44b758d
NC		 102019-09-03 Nick Clifton <nickc@redhat.com>
11
12 PR 24961
13 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
14 greater than zero before indexing via (bufcnt -1).
15
1e4b5e7d
NC		 162019-09-03 Nick Clifton <nickc@redhat.com>
17
18 PR 24958
19 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
20 (MAX_SPEC_REG_NAME_LEN): Define.
21 (struct mmix_dis_info): Use defined constants for array lengths.
22 (get_reg_name): New function.
23 (get_sprec_reg_name): New function.
24 (print_insn_mmix): Use new functions.
25
c4a23bf8
SP		 262019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
27
28 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
29 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
30 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
31
a051e2f3
KT		 322019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
33
34 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
35 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
36 (aarch64_sys_reg_supported_p): Update checks for the above.
37
08132bdd
SP		 382019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
39
40 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
41 cases MVE_SQRSHRL and MVE_UQRSHLL.
42 (print_insn_mve): Add case for specifier 'k' to check
43 specific bit of the instruction.
44
d88bdcb4
PA		 452019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
46
47 PR 24854
48 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
49 encountering an unknown machine type.
50 (print_insn_arc): Handle arc_insn_length returning 0. In error
51 cases return -1 rather than calling abort.
52
bc750500
JB		 532019-08-07 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
56 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
57 IgnoreSize.
58 * i386-tbl.h: Re-generate.
59
23d188c7
BW		 602019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
61
62 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
63 instructions.
64
c0d6f62f
JW		 652019-07-30 Mel Chen <mel.chen@sifive.com>
66
67 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
68 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
69
70 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
71 fscsr.
72
0f3f7167
CZ		 732019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
74
75 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
76 and MPY class instructions.
77 (parse_option): Add nps400 option.
78 (print_arc_disassembler_options): Add nps400 info.
79
7e126ba3
CZ		 802019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
81
82 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
83 (bspop): Likewise.
84 (modapp): Likewise.
85 * arc-opc.c (RAD_CHK): Add.
86 * arc-tbl.h: Regenerate.
87
a028026d
KT		 882019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
89
90 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
91 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
92
ac79ff9e
NC		 932019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
94
95 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
96 instructions as UNPREDICTABLE.
97
231097b0
JM		 982019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
99
100 * bpf-desc.c: Regenerated.
101
1d942ae9
JB		 1022019-07-17 Jan Beulich <jbeulich@suse.com>
103
104 * i386-gen.c (static_assert): Define.
105 (main): Use it.
106 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
107 (Opcode_Modifier_Num): ... this.
108 (Mem): Delete.
109
dfd69174
JB		 1102019-07-16 Jan Beulich <jbeulich@suse.com>
111
112 * i386-gen.c (operand_types): Move RegMem ...
113 (opcode_modifiers): ... here.
114 * i386-opc.h (RegMem): Move to opcode modifer enum.
115 (union i386_operand_type): Move regmem field ...
116 (struct i386_opcode_modifier): ... here.
117 * i386-opc.tbl (RegMem): Define.
118 (mov, movq): Move RegMem on segment, control, debug, and test
119 register flavors.
120 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
121 to non-SSE2AVX flavor.
122 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
123 Move RegMem on register only flavors. Drop IgnoreSize from
124 legacy encoding flavors.
125 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
126 flavors.
127 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
128 register only flavors.
129 (vmovd): Move RegMem and drop IgnoreSize on register only
130 flavor. Change opcode and operand order to store form.
131 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
132
21df382b
JB		 1332019-07-16 Jan Beulich <jbeulich@suse.com>
134
135 * i386-gen.c (operand_type_init, operand_types): Replace SReg
136 entries.
137 * i386-opc.h (SReg2, SReg3): Replace by ...
138 (SReg): ... this.
139 (union i386_operand_type): Replace sreg fields.
140 * i386-opc.tbl (mov, ): Use SReg.
141 (push, pop): Likewies. Drop i386 and x86-64 specific segment
142 register flavors.
143 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
144 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
145
3719fd55
JM		 1462019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
147
148 * bpf-desc.c: Regenerate.
149 * bpf-opc.c: Likewise.
150 * bpf-opc.h: Likewise.
151
92434a14
JM		 1522019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
153
154 * bpf-desc.c: Regenerate.
155 * bpf-opc.c: Likewise.
156
43dd7626
HPN		 1572019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
158
159 * arm-dis.c (print_insn_coprocessor): Rename index to
160 index_operand.
161
98602811
JW		 1622019-07-05 Kito Cheng <kito.cheng@sifive.com>
163
164 * riscv-opc.c (riscv_insn_types): Add r4 type.
165
166 * riscv-opc.c (riscv_insn_types): Add b and j type.
167
168 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
169 format for sb type and correct s type.
170
01c1ee4a
RS		 1712019-07-02 Richard Sandiford <richard.sandiford@arm.com>
172
173 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
174 SVE FMOV alias of FCPY.
175
83adff69
RS		 1762019-07-02 Richard Sandiford <richard.sandiford@arm.com>
177
178 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
179 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
180
89418844
RS		 1812019-07-02 Richard Sandiford <richard.sandiford@arm.com>
182
183 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
184 registers in an instruction prefixed by MOVPRFX.
185
41be57ca
MM		 1862019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
187
188 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
189 sve_size_13 icode to account for variant behaviour of
190 pmull{t,b}.
191 * aarch64-dis-2.c: Regenerate.
192 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
193 sve_size_13 icode to account for variant behaviour of
194 pmull{t,b}.
195 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
196 (OP_SVE_VVV_Q_D): Add new qualifier.
197 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
198 (struct aarch64_opcode): Split pmull{t,b} into those requiring
199 AES and those not.
200
9d3bf266
JB		 2012019-07-01 Jan Beulich <jbeulich@suse.com>
202
203 * opcodes/i386-gen.c (operand_type_init): Remove
204 OPERAND_TYPE_VEC_IMM4 entry.
205 (operand_types): Remove Vec_Imm4.
206 * opcodes/i386-opc.h (Vec_Imm4): Delete.
207 (union i386_operand_type): Remove vec_imm4.
208 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
209 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
210
c3949f43
JB		 2112019-07-01 Jan Beulich <jbeulich@suse.com>
212
213 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
214 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
215 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
216 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
217 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
218 monitorx, mwaitx): Drop ImmExt from operand-less forms.
219 * i386-tbl.h: Re-generate.
220
5641ec01
JB		 2212019-07-01 Jan Beulich <jbeulich@suse.com>
222
223 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
224 register operands.
225 * i386-tbl.h: Re-generate.
226
79dec6b7
JB		 2272019-07-01 Jan Beulich <jbeulich@suse.com>
228
229 * i386-opc.tbl (C): New.
230 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
231 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
232 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
233 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
234 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
235 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
236 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
237 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
238 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
239 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
240 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
241 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
242 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
243 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
244 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
245 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
246 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
247 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
248 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
249 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
250 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
251 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
252 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
253 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
254 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
255 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
256 flavors.
257 * i386-tbl.h: Re-generate.
258
a0a1771e
JB		 2592019-07-01 Jan Beulich <jbeulich@suse.com>
260
261 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
262 register operands.
263 * i386-tbl.h: Re-generate.
264
cd546e7b
JB		 2652019-07-01 Jan Beulich <jbeulich@suse.com>
266
267 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
268 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
269 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
270 * i386-tbl.h: Re-generate.
271
e3bba3fc
JB		 2722019-07-01 Jan Beulich <jbeulich@suse.com>
273
274 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
275 Disp8MemShift from register only templates.
276 * i386-tbl.h: Re-generate.
277
36cc073e
JB		 2782019-07-01 Jan Beulich <jbeulich@suse.com>
279
280 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
281 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
282 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
283 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
284 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
285 EVEX_W_0F11_P_3_M_1): Delete.
286 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
287 EVEX_W_0F11_P_3): New.
288 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
289 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
290 MOD_EVEX_0F11_PREFIX_3 table entries.
291 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
292 PREFIX_EVEX_0F11 table entries.
293 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
294 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
295 EVEX_W_0F11_P_3_M_{0,1} table entries.
296
219920a7
JB		 2972019-07-01 Jan Beulich <jbeulich@suse.com>
298
299 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
300 Delete.
301
e395f487
L		 3022019-06-27 H.J. Lu <hongjiu.lu@intel.com>
303
304 PR binutils/24719
305 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
306 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
307 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
308 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
309 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
310 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
311 EVEX_LEN_0F38C7_R_6_P_2_W_1.
312 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
313 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
314 PREFIX_EVEX_0F38C6_REG_6 entries.
315 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
316 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
317 EVEX_W_0F38C7_R_6_P_2 entries.
318 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
319 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
320 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
321 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
322 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
323 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
324 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
325
2b7bcc87
JB		 3262019-06-27 Jan Beulich <jbeulich@suse.com>
327
328 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
329 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
330 VEX_LEN_0F2D_P_3): Delete.
331 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
332 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
333 (prefix_table): ... here.
334
c1dc7af5
JB		 3352019-06-27 Jan Beulich <jbeulich@suse.com>
336
337 * i386-dis.c (Iq): Delete.
338 (Id): New.
339 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
340 TBM insns.
341 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
342 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
343 (OP_E_memory): Also honor needindex when deciding whether an
344 address size prefix needs printing.
345 (OP_I): Remove handling of q_mode. Add handling of d_mode.
346
d7560e2d
JW		 3472019-06-26 Jim Wilson <jimw@sifive.com>
348
349 PR binutils/24739
350 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
351 Set info->display_endian to info->endian_code.
352
2c703856
JB		 3532019-06-25 Jan Beulich <jbeulich@suse.com>
354
355 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
356 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
357 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
358 OPERAND_TYPE_ACC64 entries.
359 * i386-init.h: Re-generate.
360
54fbadc0
JB		 3612019-06-25 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
364 Delete.
365 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
366 of dqa_mode.
367 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
368 entries here.
369 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
370 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
371
a280ab8e
JB		 3722019-06-25 Jan Beulich <jbeulich@suse.com>
373
374 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
375 variables.
376
e1a1babd
JB		 3772019-06-25 Jan Beulich <jbeulich@suse.com>
378
379 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
380 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
381 movnti.
d7560e2d 382 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 383 * i386-tbl.h: Re-generate.
384
b8364fa7
JB		 3852019-06-25 Jan Beulich <jbeulich@suse.com>
386
387 * i386-opc.tbl (and): Mark Imm8S form for optimization.
388 * i386-tbl.h: Re-generate.
389
ad692897
L		 3902019-06-21 H.J. Lu <hongjiu.lu@intel.com>
391
392 * i386-dis-evex.h: Break into ...
393 * i386-dis-evex-len.h: New file.
394 * i386-dis-evex-mod.h: Likewise.
395 * i386-dis-evex-prefix.h: Likewise.
396 * i386-dis-evex-reg.h: Likewise.
397 * i386-dis-evex-w.h: Likewise.
398 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
399 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
400 i386-dis-evex-mod.h.
401
f0a6222e
L		 4022019-06-19 H.J. Lu <hongjiu.lu@intel.com>
403
404 PR binutils/24700
405 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
406 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
407 EVEX_W_0F385B_P_2.
408 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
409 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
410 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
411 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
412 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
413 EVEX_LEN_0F385B_P_2_W_1.
414 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
415 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
416 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
417 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
418 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
419 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
420 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
421 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
422 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
423 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
424
6e1c90b7
L		 4252019-06-17 H.J. Lu <hongjiu.lu@intel.com>
426
427 PR binutils/24691
428 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
429 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
430 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
431 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
432 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
433 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
434 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
435 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
436 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
437 EVEX_LEN_0F3A43_P_2_W_1.
438 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
439 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
440 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
441 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
442 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
443 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
444 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
445 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
446 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
447 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
448 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
449 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
450
bcc5a6eb
NC		 4512019-06-14 Nick Clifton <nickc@redhat.com>
452
453 * po/fr.po; Updated French translation.
454
e4c4ac46
SH		 4552019-06-13 Stafford Horne <shorne@gmail.com>
456
457 * or1k-asm.c: Regenerated.
458 * or1k-desc.c: Regenerated.
459 * or1k-desc.h: Regenerated.
460 * or1k-dis.c: Regenerated.
461 * or1k-ibld.c: Regenerated.
462 * or1k-opc.c: Regenerated.
463 * or1k-opc.h: Regenerated.
464 * or1k-opinst.c: Regenerated.
465
a0e44ef5
PB		 4662019-06-12 Peter Bergner <bergner@linux.ibm.com>
467
468 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
469
12efd68d
L		 4702019-06-05 H.J. Lu <hongjiu.lu@intel.com>
471
472 PR binutils/24633
473 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
474 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
475 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
476 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
477 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
478 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
479 EVEX_LEN_0F3A1B_P_2_W_1.
480 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
481 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
482 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
483 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
484 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
485 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
486 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
487 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
488
63c6fc6c
L		 4892019-06-04 H.J. Lu <hongjiu.lu@intel.com>
490
491 PR binutils/24626
492 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
493 EVEX.vvvv when disassembling VEX and EVEX instructions.
494 (OP_VEX): Set vex.register_specifier to 0 after readding
495 vex.register_specifier.
496 (OP_Vex_2src_1): Likewise.
497 (OP_Vex_2src_2): Likewise.
498 (OP_LWP_E): Likewise.
499 (OP_EX_Vex): Don't check vex.register_specifier.
500 (OP_XMM_Vex): Likewise.
501
9186c494
L		 5022019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
503 Lili Cui <lili.cui@intel.com>
504
505 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
506 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
507 instructions.
508 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
509 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
510 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
511 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
512 (i386_cpu_flags): Add cpuavx512_vp2intersect.
513 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
514 * i386-init.h: Regenerated.
515 * i386-tbl.h: Likewise.
516
5d79adc4
L		 5172019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
518 Lili Cui <lili.cui@intel.com>
519
520 * doc/c-i386.texi: Document enqcmd.
521 * testsuite/gas/i386/enqcmd-intel.d: New file.
522 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
523 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
524 * testsuite/gas/i386/enqcmd.d: Likewise.
525 * testsuite/gas/i386/enqcmd.s: Likewise.
526 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
527 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
528 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
529 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
530 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
531 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
532 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
533 and x86-64-enqcmd.
534
a9d96ab9
AH		 5352019-06-04 Alan Hayward <alan.hayward@arm.com>
536
537 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
538
4f6d070a
AM		 5392019-06-03 Alan Modra <amodra@gmail.com>
540
541 * ppc-dis.c (prefix_opcd_indices): Correct size.
542
a2f4b66c
L		 5432019-05-28 H.J. Lu <hongjiu.lu@intel.com>
544
545 PR gas/24625
546 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
547 Disp8ShiftVL.
548 * i386-tbl.h: Regenerated.
549
405b5bd8
AM		 5502019-05-24 Alan Modra <amodra@gmail.com>
551
552 * po/POTFILES.in: Regenerate.
553
8acf1435
PB		 5542019-05-24 Peter Bergner <bergner@linux.ibm.com>
555 Alan Modra <amodra@gmail.com>
556
557 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
558 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
559 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
560 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
561 XTOP>): Define and add entries.
562 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
563 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
564 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
565 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
566
dd7efa79
PB		 5672019-05-24 Peter Bergner <bergner@linux.ibm.com>
568 Alan Modra <amodra@gmail.com>
569
570 * ppc-dis.c (ppc_opts): Add "future" entry.
571 (PREFIX_OPCD_SEGS): Define.
572 (prefix_opcd_indices): New array.
573 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
574 (lookup_prefix): New function.
575 (print_insn_powerpc): Handle 64-bit prefix instructions.
576 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
577 (PMRR, POWERXX): Define.
578 (prefix_opcodes): New instruction table.
579 (prefix_num_opcodes): New constant.
580
79472b45
JM		 5812019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
582
583 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
584 * configure: Regenerated.
585 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
586 and cpu/bpf.opc.
587 (HFILES): Add bpf-desc.h and bpf-opc.h.
588 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
589 bpf-ibld.c and bpf-opc.c.
590 (BPF_DEPS): Define.
591 * Makefile.in: Regenerated.
592 * disassemble.c (ARCH_bpf): Define.
593 (disassembler): Add case for bfd_arch_bpf.
594 (disassemble_init_for_target): Likewise.
595 (enum epbf_isa_attr): Define.
596 * disassemble.h: extern print_insn_bpf.
597 * bpf-asm.c: Generated.
598 * bpf-opc.h: Likewise.
599 * bpf-opc.c: Likewise.
600 * bpf-ibld.c: Likewise.
601 * bpf-dis.c: Likewise.
602 * bpf-desc.h: Likewise.
603 * bpf-desc.c: Likewise.
604
ba6cd17f
SD		 6052019-05-21 Sudakshina Das <sudi.das@arm.com>
606
607 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
608 and VMSR with the new operands.
609
e39c1607
SD		 6102019-05-21 Sudakshina Das <sudi.das@arm.com>
611
612 * arm-dis.c (enum mve_instructions): New enum
613 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
614 and cneg.
615 (mve_opcodes): New instructions as above.
616 (is_mve_encoding_conflict): Add cases for csinc, csinv,
617 csneg and csel.
618 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
619
23d00a41
SD		 6202019-05-21 Sudakshina Das <sudi.das@arm.com>
621
622 * arm-dis.c (emun mve_instructions): Updated for new instructions.
623 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
624 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
625 uqshl, urshrl and urshr.
626 (is_mve_okay_in_it): Add new instructions to TRUE list.
627 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
628 (print_insn_mve): Updated to accept new %j,
629 %<bitfield>m and %<bitfield>n patterns.
630
cd4797ee
FS		 6312019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
632
633 * mips-opc.c (mips_builtin_opcodes): Change source register
634 constraint for DAUI.
635
999b073b
NC		 6362019-05-20 Nick Clifton <nickc@redhat.com>
637
638 * po/fr.po: Updated French translation.
639
14b456f2
AV		 6402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
641 Michael Collison <michael.collison@arm.com>
642
643 * arm-dis.c (thumb32_opcodes): Add new instructions.
644 (enum mve_instructions): Likewise.
645 (enum mve_undefined): Add new reasons.
646 (is_mve_encoding_conflict): Handle new instructions.
647 (is_mve_undefined): Likewise.
648 (is_mve_unpredictable): Likewise.
649 (print_mve_undefined): Likewise.
650 (print_mve_size): Likewise.
651
f49bb598
AV		 6522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
653 Michael Collison <michael.collison@arm.com>
654
655 * arm-dis.c (thumb32_opcodes): Add new instructions.
656 (enum mve_instructions): Likewise.
657 (is_mve_encoding_conflict): Handle new instructions.
658 (is_mve_undefined): Likewise.
659 (is_mve_unpredictable): Likewise.
660 (print_mve_size): Likewise.
661
56858bea
AV		 6622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
663 Michael Collison <michael.collison@arm.com>
664
665 * arm-dis.c (thumb32_opcodes): Add new instructions.
666 (enum mve_instructions): Likewise.
667 (is_mve_encoding_conflict): Likewise.
668 (is_mve_unpredictable): Likewise.
669 (print_mve_size): Likewise.
670
e523f101
AV		 6712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
672 Michael Collison <michael.collison@arm.com>
673
674 * arm-dis.c (thumb32_opcodes): Add new instructions.
675 (enum mve_instructions): Likewise.
676 (is_mve_encoding_conflict): Handle new instructions.
677 (is_mve_undefined): Likewise.
678 (is_mve_unpredictable): Likewise.
679 (print_mve_size): Likewise.
680
66dcaa5d
AV		 6812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
682 Michael Collison <michael.collison@arm.com>
683
684 * arm-dis.c (thumb32_opcodes): Add new instructions.
685 (enum mve_instructions): Likewise.
686 (is_mve_encoding_conflict): Handle new instructions.
687 (is_mve_undefined): Likewise.
688 (is_mve_unpredictable): Likewise.
689 (print_mve_size): Likewise.
690 (print_insn_mve): Likewise.
691
d052b9b7
AV		 6922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
693 Michael Collison <michael.collison@arm.com>
694
695 * arm-dis.c (thumb32_opcodes): Add new instructions.
696 (print_insn_thumb32): Handle new instructions.
697
ed63aa17
AV		 6982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
699 Michael Collison <michael.collison@arm.com>
700
701 * arm-dis.c (enum mve_instructions): Add new instructions.
702 (enum mve_undefined): Add new reasons.
703 (is_mve_encoding_conflict): Handle new instructions.
704 (is_mve_undefined): Likewise.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_undefined): Likewise.
707 (print_mve_size): Likewise.
708 (print_mve_shift_n): Likewise.
709 (print_insn_mve): Likewise.
710
897b9bbc
AV		 7112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
712 Michael Collison <michael.collison@arm.com>
713
714 * arm-dis.c (enum mve_instructions): Add new instructions.
715 (is_mve_encoding_conflict): Handle new instructions.
716 (is_mve_unpredictable): Likewise.
717 (print_mve_rotate): Likewise.
718 (print_mve_size): Likewise.
719 (print_insn_mve): Likewise.
720
1c8f2df8
AV		 7212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
722 Michael Collison <michael.collison@arm.com>
723
724 * arm-dis.c (enum mve_instructions): Add new instructions.
725 (is_mve_encoding_conflict): Handle new instructions.
726 (is_mve_unpredictable): Likewise.
727 (print_mve_size): Likewise.
728 (print_insn_mve): Likewise.
729
d3b63143
AV		 7302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
731 Michael Collison <michael.collison@arm.com>
732
733 * arm-dis.c (enum mve_instructions): Add new instructions.
734 (enum mve_undefined): Add new reasons.
735 (is_mve_encoding_conflict): Handle new instructions.
736 (is_mve_undefined): Likewise.
737 (is_mve_unpredictable): Likewise.
738 (print_mve_undefined): Likewise.
739 (print_mve_size): Likewise.
740 (print_insn_mve): Likewise.
741
14925797
AV		 7422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
743 Michael Collison <michael.collison@arm.com>
744
745 * arm-dis.c (enum mve_instructions): Add new instructions.
746 (is_mve_encoding_conflict): Handle new instructions.
747 (is_mve_undefined): Likewise.
748 (is_mve_unpredictable): Likewise.
749 (print_mve_size): Likewise.
750 (print_insn_mve): Likewise.
751
c507f10b
AV		 7522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
753 Michael Collison <michael.collison@arm.com>
754
755 * arm-dis.c (enum mve_instructions): Add new instructions.
756 (enum mve_unpredictable): Add new reasons.
757 (enum mve_undefined): Likewise.
758 (is_mve_okay_in_it): Handle new isntructions.
759 (is_mve_encoding_conflict): Likewise.
760 (is_mve_undefined): Likewise.
761 (is_mve_unpredictable): Likewise.
762 (print_mve_vmov_index): Likewise.
763 (print_simd_imm8): Likewise.
764 (print_mve_undefined): Likewise.
765 (print_mve_unpredictable): Likewise.
766 (print_mve_size): Likewise.
767 (print_insn_mve): Likewise.
768
bf0b396d
AV		 7692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
770 Michael Collison <michael.collison@arm.com>
771
772 * arm-dis.c (enum mve_instructions): Add new instructions.
773 (enum mve_unpredictable): Add new reasons.
774 (enum mve_undefined): Likewise.
775 (is_mve_encoding_conflict): Handle new instructions.
776 (is_mve_undefined): Likewise.
777 (is_mve_unpredictable): Likewise.
778 (print_mve_undefined): Likewise.
779 (print_mve_unpredictable): Likewise.
780 (print_mve_rounding_mode): Likewise.
781 (print_mve_vcvt_size): Likewise.
782 (print_mve_size): Likewise.
783 (print_insn_mve): Likewise.
784
ef1576a1
AV		 7852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
786 Michael Collison <michael.collison@arm.com>
787
788 * arm-dis.c (enum mve_instructions): Add new instructions.
789 (enum mve_unpredictable): Add new reasons.
790 (enum mve_undefined): Likewise.
791 (is_mve_undefined): Handle new instructions.
792 (is_mve_unpredictable): Likewise.
793 (print_mve_undefined): Likewise.
794 (print_mve_unpredictable): Likewise.
795 (print_mve_size): Likewise.
796 (print_insn_mve): Likewise.
797
aef6d006
AV		 7982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
799 Michael Collison <michael.collison@arm.com>
800
801 * arm-dis.c (enum mve_instructions): Add new instructions.
802 (enum mve_undefined): Add new reasons.
803 (insns): Add new instructions.
804 (is_mve_encoding_conflict):
805 (print_mve_vld_str_addr): New print function.
806 (is_mve_undefined): Handle new instructions.
807 (is_mve_unpredictable): Likewise.
808 (print_mve_undefined): Likewise.
809 (print_mve_size): Likewise.
810 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
811 (print_insn_mve): Handle new operands.
812
04d54ace
AV		 8132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
814 Michael Collison <michael.collison@arm.com>
815
816 * arm-dis.c (enum mve_instructions): Add new instructions.
817 (enum mve_unpredictable): Add new reasons.
818 (is_mve_encoding_conflict): Handle new instructions.
819 (is_mve_unpredictable): Likewise.
820 (mve_opcodes): Add new instructions.
821 (print_mve_unpredictable): Handle new reasons.
822 (print_mve_register_blocks): New print function.
823 (print_mve_size): Handle new instructions.
824 (print_insn_mve): Likewise.
825
9743db03
AV		 8262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
827 Michael Collison <michael.collison@arm.com>
828
829 * arm-dis.c (enum mve_instructions): Add new instructions.
830 (enum mve_unpredictable): Add new reasons.
831 (enum mve_undefined): Likewise.
832 (is_mve_encoding_conflict): Handle new instructions.
833 (is_mve_undefined): Likewise.
834 (is_mve_unpredictable): Likewise.
835 (coprocessor_opcodes): Move NEON VDUP from here...
836 (neon_opcodes): ... to here.
837 (mve_opcodes): Add new instructions.
838 (print_mve_undefined): Handle new reasons.
839 (print_mve_unpredictable): Likewise.
840 (print_mve_size): Handle new instructions.
841 (print_insn_neon): Handle vdup.
842 (print_insn_mve): Handle new operands.
843
143275ea
AV		 8442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
845 Michael Collison <michael.collison@arm.com>
846
847 * arm-dis.c (enum mve_instructions): Add new instructions.
848 (enum mve_unpredictable): Add new values.
849 (mve_opcodes): Add new instructions.
850 (vec_condnames): New array with vector conditions.
851 (mve_predicatenames): New array with predicate suffixes.
852 (mve_vec_sizename): New array with vector sizes.
853 (enum vpt_pred_state): New enum with vector predication states.
854 (struct vpt_block): New struct type for vpt blocks.
855 (vpt_block_state): Global struct to keep track of state.
856 (mve_extract_pred_mask): New helper function.
857 (num_instructions_vpt_block): Likewise.
858 (mark_outside_vpt_block): Likewise.
859 (mark_inside_vpt_block): Likewise.
860 (invert_next_predicate_state): Likewise.
861 (update_next_predicate_state): Likewise.
862 (update_vpt_block_state): Likewise.
863 (is_vpt_instruction): Likewise.
864 (is_mve_encoding_conflict): Add entries for new instructions.
865 (is_mve_unpredictable): Likewise.
866 (print_mve_unpredictable): Handle new cases.
867 (print_instruction_predicate): Likewise.
868 (print_mve_size): New function.
869 (print_vec_condition): New function.
870 (print_insn_mve): Handle vpt blocks and new print operands.
871
f08d8ce3
AV		 8722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
873
874 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
875 8, 14 and 15 for Armv8.1-M Mainline.
876
73cd51e5
AV		 8772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
878 Michael Collison <michael.collison@arm.com>
879
880 * arm-dis.c (enum mve_instructions): New enum.
881 (enum mve_unpredictable): Likewise.
882 (enum mve_undefined): Likewise.
883 (struct mopcode32): New struct.
884 (is_mve_okay_in_it): New function.
885 (is_mve_architecture): Likewise.
886 (arm_decode_field): Likewise.
887 (arm_decode_field_multiple): Likewise.
888 (is_mve_encoding_conflict): Likewise.
889 (is_mve_undefined): Likewise.
890 (is_mve_unpredictable): Likewise.
891 (print_mve_undefined): Likewise.
892 (print_mve_unpredictable): Likewise.
893 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
894 (print_insn_mve): New function.
895 (print_insn_thumb32): Handle MVE architecture.
896 (select_arm_features): Force thumb for Armv8.1-m Mainline.
897
3076e594
NC		 8982019-05-10 Nick Clifton <nickc@redhat.com>
899
900 PR 24538
901 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
902 end of the table prematurely.
903
387e7624
FS		 9042019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
905
906 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
907 macros for R6.
908
0067be51
AM		 9092019-05-11 Alan Modra <amodra@gmail.com>
910
911 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
912 when -Mraw is in effect.
913
42e6288f
MM		 9142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
915
916 * aarch64-dis-2.c: Regenerate.
917 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
918 (OP_SVE_BBB): New variant set.
919 (OP_SVE_DDDD): New variant set.
920 (OP_SVE_HHH): New variant set.
921 (OP_SVE_HHHU): New variant set.
922 (OP_SVE_SSS): New variant set.
923 (OP_SVE_SSSU): New variant set.
924 (OP_SVE_SHH): New variant set.
925 (OP_SVE_SBBU): New variant set.
926 (OP_SVE_DSS): New variant set.
927 (OP_SVE_DHHU): New variant set.
928 (OP_SVE_VMV_HSD_BHS): New variant set.
929 (OP_SVE_VVU_HSD_BHS): New variant set.
930 (OP_SVE_VVVU_SD_BH): New variant set.
931 (OP_SVE_VVVU_BHSD): New variant set.
932 (OP_SVE_VVV_QHD_DBS): New variant set.
933 (OP_SVE_VVV_HSD_BHS): New variant set.
934 (OP_SVE_VVV_HSD_BHS2): New variant set.
935 (OP_SVE_VVV_BHS_HSD): New variant set.
936 (OP_SVE_VV_BHS_HSD): New variant set.
937 (OP_SVE_VVV_SD): New variant set.
938 (OP_SVE_VVU_BHS_HSD): New variant set.
939 (OP_SVE_VZVV_SD): New variant set.
940 (OP_SVE_VZVV_BH): New variant set.
941 (OP_SVE_VZV_SD): New variant set.
942 (aarch64_opcode_table): Add sve2 instructions.
943
28ed815a
MM		 9442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
945
946 * aarch64-asm-2.c: Regenerated.
947 * aarch64-dis-2.c: Regenerated.
948 * aarch64-opc-2.c: Regenerated.
949 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
950 for SVE_SHLIMM_UNPRED_22.
951 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
952 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
953 operand.
954
fd1dc4a0
MM		 9552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
956
957 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
958 sve_size_tsz_bhs iclass encode.
959 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
960 sve_size_tsz_bhs iclass decode.
961
31e36ab3
MM		 9622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
963
964 * aarch64-asm-2.c: Regenerated.
965 * aarch64-dis-2.c: Regenerated.
966 * aarch64-opc-2.c: Regenerated.
967 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
968 for SVE_Zm4_11_INDEX.
969 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
970 (fields): Handle SVE_i2h field.
971 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
972 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
973
1be5f94f
MM		 9742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975
976 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
977 sve_shift_tsz_bhsd iclass encode.
978 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
979 sve_shift_tsz_bhsd iclass decode.
980
3c17238b
MM		 9812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
982
983 * aarch64-asm-2.c: Regenerated.
984 * aarch64-dis-2.c: Regenerated.
985 * aarch64-opc-2.c: Regenerated.
986 * aarch64-asm.c (aarch64_ins_sve_shrimm):
987 (aarch64_encode_variant_using_iclass): Handle
988 sve_shift_tsz_hsd iclass encode.
989 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
990 sve_shift_tsz_hsd iclass decode.
991 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
992 for SVE_SHRIMM_UNPRED_22.
993 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
994 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
995 operand.
996
cd50a87a
MM		 9972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
998
999 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1000 sve_size_013 iclass encode.
1001 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1002 sve_size_013 iclass decode.
1003
3c705960
MM		 10042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1005
1006 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1007 sve_size_bh iclass encode.
1008 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1009 sve_size_bh iclass decode.
1010
0a57e14f
MM		 10112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1012
1013 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1014 sve_size_sd2 iclass encode.
1015 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1016 sve_size_sd2 iclass decode.
1017 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1018 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1019
c469c864
MM		 10202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1021
1022 * aarch64-asm-2.c: Regenerated.
1023 * aarch64-dis-2.c: Regenerated.
1024 * aarch64-opc-2.c: Regenerated.
1025 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1026 for SVE_ADDR_ZX.
1027 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1028 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1029
116adc27
MM		 10302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1031
1032 * aarch64-asm-2.c: Regenerated.
1033 * aarch64-dis-2.c: Regenerated.
1034 * aarch64-opc-2.c: Regenerated.
1035 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1036 for SVE_Zm3_11_INDEX.
1037 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1038 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1039 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1040 fields.
1041 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1042
3bd82c86
MM		 10432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1044
1045 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1046 sve_size_hsd2 iclass encode.
1047 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1048 sve_size_hsd2 iclass decode.
1049 * aarch64-opc.c (fields): Handle SVE_size field.
1050 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1051
adccc507
MM		 10522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1053
1054 * aarch64-asm-2.c: Regenerated.
1055 * aarch64-dis-2.c: Regenerated.
1056 * aarch64-opc-2.c: Regenerated.
1057 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1058 for SVE_IMM_ROT3.
1059 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1060 (fields): Handle SVE_rot3 field.
1061 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1062 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1063
5cd99750
MM		 10642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1065
1066 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1067 instructions.
1068
7ce2460a
MM		 10692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1070
1071 * aarch64-tbl.h
1072 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1073 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1074 aarch64_feature_sve2bitperm): New feature sets.
1075 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1076 for feature set addresses.
1077 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1078 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1079
41cee089
FS		 10802019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1081 Faraz Shahbazker <fshahbazker@wavecomp.com>
1082
1083 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1084 argument and set ASE_EVA_R6 appropriately.
1085 (set_default_mips_dis_options): Pass ISA to above.
1086 (parse_mips_dis_option): Likewise.
1087 * mips-opc.c (EVAR6): New macro.
1088 (mips_builtin_opcodes): Add llwpe, scwpe.
1089
b83b4b13
SD		 10902019-05-01 Sudakshina Das <sudi.das@arm.com>
1091
1092 * aarch64-asm-2.c: Regenerated.
1093 * aarch64-dis-2.c: Regenerated.
1094 * aarch64-opc-2.c: Regenerated.
1095 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1096 AARCH64_OPND_TME_UIMM16.
1097 (aarch64_print_operand): Likewise.
1098 * aarch64-tbl.h (QL_IMM_NIL): New.
1099 (TME): New.
1100 (_TME_INSN): New.
1101 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1102
4a90ce95
JD		 11032019-04-29 John Darrington <john@darrington.wattle.id.au>
1104
1105 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1106
a45328b9
AB		 11072019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1108 Faraz Shahbazker <fshahbazker@wavecomp.com>
1109
1110 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1111
d10be0cb
JD		 11122019-04-24 John Darrington <john@darrington.wattle.id.au>
1113
1114 * s12z-opc.h: Add extern "C" bracketing to help
1115 users who wish to use this interface in c++ code.
1116
a679f24e
JD		 11172019-04-24 John Darrington <john@darrington.wattle.id.au>
1118
1119 * s12z-opc.c (bm_decode): Handle bit map operations with the
1120 "reserved0" mode.
1121
32c36c3c
AV		 11222019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1123
1124 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1125 specifier. Add entries for VLDR and VSTR of system registers.
1126 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1127 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1128 of %J and %K format specifier.
1129
efd6b359
AV		 11302019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1131
1132 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1133 Add new entries for VSCCLRM instruction.
1134 (print_insn_coprocessor): Handle new %C format control code.
1135
6b0dd094
AV		 11362019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1137
1138 * arm-dis.c (enum isa): New enum.
1139 (struct sopcode32): New structure.
1140 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1141 set isa field of all current entries to ANY.
1142 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1143 Only match an entry if its isa field allows the current mode.
1144
4b5a202f
AV		 11452019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1146
1147 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1148 CLRM.
1149 (print_insn_thumb32): Add logic to print %n CLRM register list.
1150
60f993ce
AV		 11512019-04-15 Sudakshina Das <sudi.das@arm.com>
1152
1153 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1154 and %Q patterns.
1155
f6b2b12d
AV		 11562019-04-15 Sudakshina Das <sudi.das@arm.com>
1157
1158 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1159 (print_insn_thumb32): Edit the switch case for %Z.
1160
1889da70
AV		 11612019-04-15 Sudakshina Das <sudi.das@arm.com>
1162
1163 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1164
65d1bc05
AV		 11652019-04-15 Sudakshina Das <sudi.das@arm.com>
1166
1167 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1168
1caf72a5
AV		 11692019-04-15 Sudakshina Das <sudi.das@arm.com>
1170
1171 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1172
f1c7f421
AV		 11732019-04-15 Sudakshina Das <sudi.das@arm.com>
1174
1175 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1176 Arm register with r13 and r15 unpredictable.
1177 (thumb32_opcodes): New instructions for bfx and bflx.
1178
4389b29a
AV		 11792019-04-15 Sudakshina Das <sudi.das@arm.com>
1180
1181 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1182
e5d6e09e
AV		 11832019-04-15 Sudakshina Das <sudi.das@arm.com>
1184
1185 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1186
e12437dc
AV		 11872019-04-15 Sudakshina Das <sudi.das@arm.com>
1188
1189 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1190
031254f2
AV		 11912019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1192
1193 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1194
e5a557ac
JD		 11952019-04-12 John Darrington <john@darrington.wattle.id.au>
1196
1197 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1198 "optr". ("operator" is a reserved word in c++).
1199
bd7ceb8d
SD		 12002019-04-11 Sudakshina Das <sudi.das@arm.com>
1201
1202 * aarch64-opc.c (aarch64_print_operand): Add case for
1203 AARCH64_OPND_Rt_SP.
1204 (verify_constraints): Likewise.
1205 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1206 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1207 to accept Rt|SP as first operand.
1208 (AARCH64_OPERANDS): Add new Rt_SP.
1209 * aarch64-asm-2.c: Regenerated.
1210 * aarch64-dis-2.c: Regenerated.
1211 * aarch64-opc-2.c: Regenerated.
1212
e54010f1
SD		 12132019-04-11 Sudakshina Das <sudi.das@arm.com>
1214
1215 * aarch64-asm-2.c: Regenerated.
1216 * aarch64-dis-2.c: Likewise.
1217 * aarch64-opc-2.c: Likewise.
1218 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1219
7e96e219
RS		 12202019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1221
1222 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1223
6f2791d5
L		 12242019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1225
1226 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1227 * i386-init.h: Regenerated.
1228
e392bad3
AM		 12292019-04-07 Alan Modra <amodra@gmail.com>
1230
1231 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1232 op_separator to control printing of spaces, comma and parens
1233 rather than need_comma, need_paren and spaces vars.
1234
dffaa15c
AM		 12352019-04-07 Alan Modra <amodra@gmail.com>
1236
1237 PR 24421
1238 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1239 (print_insn_neon, print_insn_arm): Likewise.
1240
d6aab7a1
XG		 12412019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1242
1243 * i386-dis-evex.h (evex_table): Updated to support BF16
1244 instructions.
1245 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1246 and EVEX_W_0F3872_P_3.
1247 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1248 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1249 * i386-opc.h (enum): Add CpuAVX512_BF16.
1250 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1251 * i386-opc.tbl: Add AVX512 BF16 instructions.
1252 * i386-init.h: Regenerated.
1253 * i386-tbl.h: Likewise.
1254
66e85460
AM		 12552019-04-05 Alan Modra <amodra@gmail.com>
1256
1257 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1258 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1259 to favour printing of "-" branch hint when using the "y" bit.
1260 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1261
c2b1c275
AM		 12622019-04-05 Alan Modra <amodra@gmail.com>
1263
1264 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1265 opcode until first operand is output.
1266
aae9718e
PB		 12672019-04-04 Peter Bergner <bergner@linux.ibm.com>
1268
1269 PR gas/24349
1270 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1271 (valid_bo_post_v2): Add support for 'at' branch hints.
1272 (insert_bo): Only error on branch on ctr.
1273 (get_bo_hint_mask): New function.
1274 (insert_boe): Add new 'branch_taken' formal argument. Add support
1275 for inserting 'at' branch hints.
1276 (extract_boe): Add new 'branch_taken' formal argument. Add support
1277 for extracting 'at' branch hints.
1278 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1279 (BOE): Delete operand.
1280 (BOM, BOP): New operands.
1281 (RM): Update value.
1282 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1283 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1284 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1285 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1286 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1287 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1288 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1289 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1290 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1291 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1292 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1293 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1294 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1295 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1296 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1297 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1298 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1299 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1300 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1301 bttarl+>: New extended mnemonics.
1302
96a86c01
AM		 13032019-03-28 Alan Modra <amodra@gmail.com>
1304
1305 PR 24390
1306 * ppc-opc.c (BTF): Define.
1307 (powerpc_opcodes): Use for mtfsb*.
1308 * ppc-dis.c (print_insn_powerpc): Print fields with both
1309 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1310
796d6298
TC		 13112019-03-25 Tamar Christina <tamar.christina@arm.com>
1312
1313 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1314 (mapping_symbol_for_insn): Implement new algorithm.
1315 (print_insn): Remove duplicate code.
1316
60df3720
TC		 13172019-03-25 Tamar Christina <tamar.christina@arm.com>
1318
1319 * aarch64-dis.c (print_insn_aarch64):
1320 Implement override.
1321
51457761
TC		 13222019-03-25 Tamar Christina <tamar.christina@arm.com>
1323
1324 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1325 order.
1326
53b2f36b
TC		 13272019-03-25 Tamar Christina <tamar.christina@arm.com>
1328
1329 * aarch64-dis.c (last_stop_offset): New.
1330 (print_insn_aarch64): Use stop_offset.
1331
89199bb5
L		 13322019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1333
1334 PR gas/24359
1335 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1336 CPU_ANY_AVX2_FLAGS.
1337 * i386-init.h: Regenerated.
1338
97ed31ae
L		 13392019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1340
1341 PR gas/24348
1342 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1343 vmovdqu16, vmovdqu32 and vmovdqu64.
1344 * i386-tbl.h: Regenerated.
1345
0919bfe9
AK		 13462019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1347
1348 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1349 from vstrszb, vstrszh, and vstrszf.
1350
13512019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1352
1353 * s390-opc.txt: Add instruction descriptions.
1354
21820ebe
JW		 13552019-02-08 Jim Wilson <jimw@sifive.com>
1356
1357 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1358 <bne>: Likewise.
1359
f7dd2fb2
TC		 13602019-02-07 Tamar Christina <tamar.christina@arm.com>
1361
1362 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1363
6456d318
TC		 13642019-02-07 Tamar Christina <tamar.christina@arm.com>
1365
1366 PR binutils/23212
1367 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1368 * aarch64-opc.c (verify_elem_sd): New.
1369 (fields): Add FLD_sz entr.
1370 * aarch64-tbl.h (_SIMD_INSN): New.
1371 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1372 fmulx scalar and vector by element isns.
1373
4a83b610
NC		 13742019-02-07 Nick Clifton <nickc@redhat.com>
1375
1376 * po/sv.po: Updated Swedish translation.
1377
fc60b8c8
AK		 13782019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1379
1380 * s390-mkopc.c (main): Accept arch13 as cpu string.
1381 * s390-opc.c: Add new instruction formats and instruction opcode
1382 masks.
1383 * s390-opc.txt: Add new arch13 instructions.
1384
e10620d3
TC		 13852019-01-25 Sudakshina Das <sudi.das@arm.com>
1386
1387 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1388 (aarch64_opcode): Change encoding for stg, stzg
1389 st2g and st2zg.
1390 * aarch64-asm-2.c: Regenerated.
1391 * aarch64-dis-2.c: Regenerated.
1392 * aarch64-opc-2.c: Regenerated.
1393
20a4ca55
SD		 13942019-01-25 Sudakshina Das <sudi.das@arm.com>
1395
1396 * aarch64-asm-2.c: Regenerated.
1397 * aarch64-dis-2.c: Likewise.
1398 * aarch64-opc-2.c: Likewise.
1399 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1400
550fd7bf
SD		 14012019-01-25 Sudakshina Das <sudi.das@arm.com>
1402 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1403
1404 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1405 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1406 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1407 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1408 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1409 case for ldstgv_indexed.
1410 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1411 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1412 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1413 * aarch64-asm-2.c: Regenerated.
1414 * aarch64-dis-2.c: Regenerated.
1415 * aarch64-opc-2.c: Regenerated.
1416
d9938630
NC		 14172019-01-23 Nick Clifton <nickc@redhat.com>
1418
1419 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1420
375cd423
NC		 14212019-01-21 Nick Clifton <nickc@redhat.com>
1422
1423 * po/de.po: Updated German translation.
1424 * po/uk.po: Updated Ukranian translation.
1425
57299f48
CX		 14262019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1427 * mips-dis.c (mips_arch_choices): Fix typo in
1428 gs464, gs464e and gs264e descriptors.
1429
f48dfe41
NC		 14302019-01-19 Nick Clifton <nickc@redhat.com>
1431
1432 * configure: Regenerate.
1433 * po/opcodes.pot: Regenerate.
1434
f974f26c
NC		 14352018-06-24 Nick Clifton <nickc@redhat.com>
1436
1437 2.32 branch created.
1438
39f286cd
JD		 14392019-01-09 John Darrington <john@darrington.wattle.id.au>
1440
448b8ca8
JD		 1441 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1442 if it is null.
1443 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1444 zero.
1445
3107326d
AP		 14462019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1447
1448 * configure: Regenerate.
1449
7e9ca91e
AM		 14502019-01-07 Alan Modra <amodra@gmail.com>
1451
1452 * configure: Regenerate.
1453 * po/POTFILES.in: Regenerate.
1454
ef1ad42b
JD		 14552019-01-03 John Darrington <john@darrington.wattle.id.au>
1456
1457 * s12z-opc.c: New file.
1458 * s12z-opc.h: New file.
1459 * s12z-dis.c: Removed all code not directly related to display
1460 of instructions. Used the interface provided by the new files
1461 instead.
1462 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1463 * Makefile.in: Regenerate.
ef1ad42b 1464 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1465 * configure: Regenerate.
ef1ad42b 1466
82704155
AM		 14672019-01-01 Alan Modra <amodra@gmail.com>
1468
1469 Update year range in copyright notice of all files.
1470
d5c04e1b 1471For older changes see ChangeLog-2018
3499769a 1472\f
d5c04e1b 1473Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1474
1475Copying and distribution of this file, with or without modification,
1476are permitted in any medium without royalty provided the copyright
1477notice and this notice are preserved.
1478
1479Local Variables:
1480mode: change-log
1481left-margin: 8
1482fill-column: 74
1483version-control: never
1484End:
GDB Binutils - Deliverables
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