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x86: support further AMD Zen2 instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
142861df
JB		 12019-11-07 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (prefix_table): Add mcommit.
4 (rm_table): Add rdpru.
5 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
6 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
7 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
8 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
9 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
10 * i386-opc.tbl (mcommit, rdpru): New.
11 * i386-init.h, i386-tbl.h: Re-generate.
12
081e283f
JB		 132019-11-07 Jan Beulich <jbeulich@suse.com>
14
15 * i386-dis.c (OP_Mwait): Drop local variable "names", use
16 "names32" instead.
17 (OP_Monitor): Drop local variable "op1_names", re-purpose
18 "names" for it instead, and replace former "names" uses by
19 "names32" ones.
20
c050c89a
JB		 212019-11-07 Jan Beulich <jbeulich@suse.com>
22
23 PR/gas 25167
24 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
25 operand-less forms.
26 * opcodes/i386-tbl.h: Re-generate.
27
7abb8d81
JB		 282019-11-05 Jan Beulich <jbeulich@suse.com>
29
30 * i386-dis.c (OP_Mwaitx): Delete.
31 (prefix_table): Use OP_Mwait for mwaitx entry.
32 (OP_Mwait): Also handle mwaitx.
33
267b8516
JB		 342019-11-05 Jan Beulich <jbeulich@suse.com>
35
36 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
37 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
38 (prefix_table): Add respective entries.
39 (rm_table): Link to those entries.
40
f8687e93
JB		 412019-11-05 Jan Beulich <jbeulich@suse.com>
42
43 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
44 (REG_0F1C_P_0_MOD_0): ... this.
45 (REG_0F1E_MOD_3): Rename to ...
46 (REG_0F1E_P_1_MOD_3): ... this.
47 (RM_0F01_REG_5): Rename to ...
48 (RM_0F01_REG_5_MOD_3): ... this.
49 (RM_0F01_REG_7): Rename to ...
50 (RM_0F01_REG_7_MOD_3): ... this.
51 (RM_0F1E_MOD_3_REG_7): Rename to ...
52 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
53 (RM_0FAE_REG_6): Rename to ...
54 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
55 (RM_0FAE_REG_7): Rename to ...
56 (RM_0FAE_REG_7_MOD_3): ... this.
57 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
58 (PREFIX_0F01_REG_5_MOD_0): ... this.
59 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
60 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
61 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
62 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
63 (PREFIX_0FAE_REG_0): Rename to ...
64 (PREFIX_0FAE_REG_0_MOD_3): ... this.
65 (PREFIX_0FAE_REG_1): Rename to ...
66 (PREFIX_0FAE_REG_1_MOD_3): ... this.
67 (PREFIX_0FAE_REG_2): Rename to ...
68 (PREFIX_0FAE_REG_2_MOD_3): ... this.
69 (PREFIX_0FAE_REG_3): Rename to ...
70 (PREFIX_0FAE_REG_3_MOD_3): ... this.
71 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
72 (PREFIX_0FAE_REG_4_MOD_0): ... this.
73 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
74 (PREFIX_0FAE_REG_4_MOD_3): ... this.
75 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
76 (PREFIX_0FAE_REG_5_MOD_0): ... this.
77 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
78 (PREFIX_0FAE_REG_5_MOD_3): ... this.
79 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
80 (PREFIX_0FAE_REG_6_MOD_0): ... this.
81 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
82 (PREFIX_0FAE_REG_6_MOD_3): ... this.
83 (PREFIX_0FAE_REG_7): Rename to ...
84 (PREFIX_0FAE_REG_7_MOD_0): ... this.
85 (PREFIX_MOD_0_0FC3): Rename to ...
86 (PREFIX_0FC3_MOD_0): ... this.
87 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
88 (PREFIX_0FC7_REG_6_MOD_0): ... this.
89 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
90 (PREFIX_0FC7_REG_6_MOD_3): ... this.
91 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
92 (PREFIX_0FC7_REG_7_MOD_3): ... this.
93 (reg_table, prefix_table, mod_table, rm_table): Adjust
94 accordingly.
95
5103274f
NC		 962019-11-04 Nick Clifton <nickc@redhat.com>
97
98 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
99 of a v850 system register. Move the v850_sreg_names array into
100 this function.
101 (get_v850_reg_name): Likewise for ordinary register names.
102 (get_v850_vreg_name): Likewise for vector register names.
103 (get_v850_cc_name): Likewise for condition codes.
104 * get_v850_float_cc_name): Likewise for floating point condition
105 codes.
106 (get_v850_cacheop_name): Likewise for cache-ops.
107 (get_v850_prefop_name): Likewise for pref-ops.
108 (disassemble): Use the new accessor functions.
109
1820262b
DB		 1102019-10-30 Delia Burduv <delia.burduv@arm.com>
111
112 * aarch64-opc.c (print_immediate_offset_address): Don't print the
113 immediate for the writeback form of ldraa/ldrab if it is 0.
114 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
115 * aarch64-opc-2.c: Regenerated.
116
3cc17af5
JB		 1172019-10-30 Jan Beulich <jbeulich@suse.com>
118
119 * i386-gen.c (operand_type_shorthands): Delete.
120 (operand_type_init): Expand previous shorthands.
121 (set_bitfield_from_shorthand): Rename back to ...
122 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
123 of operand_type_init[].
124 (set_bitfield): Adjust call to the above function.
125 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
126 RegXMM, RegYMM, RegZMM): Define.
127 * i386-reg.tbl: Expand prior shorthands.
128
a2cebd03
JB		 1292019-10-30 Jan Beulich <jbeulich@suse.com>
130
131 * i386-gen.c (output_i386_opcode): Change order of fields
132 emitted to output.
133 * i386-opc.h (struct insn_template): Move operands field.
134 Convert extension_opcode field to unsigned short.
135 * i386-tbl.h: Re-generate.
136
507916b8
JB		 1372019-10-30 Jan Beulich <jbeulich@suse.com>
138
139 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
140 of W.
141 * i386-opc.h (W): Extend comment.
142 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
143 general purpose variants not allowing for byte operands.
144 * i386-tbl.h: Re-generate.
145
efea62b4
NC		 1462019-10-29 Nick Clifton <nickc@redhat.com>
147
148 * tic30-dis.c (print_branch): Correct size of operand array.
149
9adb2591
NC		 1502019-10-29 Nick Clifton <nickc@redhat.com>
151
152 * d30v-dis.c (print_insn): Check that operand index is valid
153 before attempting to access the operands array.
154
993a00a9
NC		 1552019-10-29 Nick Clifton <nickc@redhat.com>
156
157 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
158 locating the bit to be tested.
159
66a66a17
NC		 1602019-10-29 Nick Clifton <nickc@redhat.com>
161
162 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
163 values.
164 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
165 (print_insn_s12z): Check for illegal size values.
166
1ee3542c
NC		 1672019-10-28 Nick Clifton <nickc@redhat.com>
168
169 * csky-dis.c (csky_chars_to_number): Check for a negative
170 count. Use an unsigned integer to construct the return value.
171
bbf9a0b5
NC		 1722019-10-28 Nick Clifton <nickc@redhat.com>
173
174 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
175 operand buffer. Set value to 15 not 13.
176 (get_register_operand): Use OPERAND_BUFFER_LEN.
177 (get_indirect_operand): Likewise.
178 (print_two_operand): Likewise.
179 (print_three_operand): Likewise.
180 (print_oar_insn): Likewise.
181
d1e304bc
NC		 1822019-10-28 Nick Clifton <nickc@redhat.com>
183
184 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
185 (bit_extract_simple): Likewise.
186 (bit_copy): Likewise.
187 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
188 index_offset array are not accessed.
189
dee33451
NC		 1902019-10-28 Nick Clifton <nickc@redhat.com>
191
192 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
193 operand.
194
27cee81d
NC		 1952019-10-25 Nick Clifton <nickc@redhat.com>
196
197 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
198 access to opcodes.op array element.
199
de6d8dc2
NC		 2002019-10-23 Nick Clifton <nickc@redhat.com>
201
202 * rx-dis.c (get_register_name): Fix spelling typo in error
203 message.
204 (get_condition_name, get_flag_name, get_double_register_name)
205 (get_double_register_high_name, get_double_register_low_name)
206 (get_double_control_register_name, get_double_condition_name)
207 (get_opsize_name, get_size_name): Likewise.
208
6207ed28
NC		 2092019-10-22 Nick Clifton <nickc@redhat.com>
210
211 * rx-dis.c (get_size_name): New function. Provides safe
212 access to name array.
213 (get_opsize_name): Likewise.
214 (print_insn_rx): Use the accessor functions.
215
12234dfd
NC		 2162019-10-16 Nick Clifton <nickc@redhat.com>
217
218 * rx-dis.c (get_register_name): New function. Provides safe
219 access to name array.
220 (get_condition_name, get_flag_name, get_double_register_name)
221 (get_double_register_high_name, get_double_register_low_name)
222 (get_double_control_register_name, get_double_condition_name):
223 Likewise.
224 (print_insn_rx): Use the accessor functions.
225
1d378749
NC		 2262019-10-09 Nick Clifton <nickc@redhat.com>
227
228 PR 25041
229 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
230 instructions.
231
d241b910
JB		 2322019-10-07 Jan Beulich <jbeulich@suse.com>
233
234 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
235 (cmpsd): Likewise. Move EsSeg to other operand.
236 * opcodes/i386-tbl.h: Re-generate.
237
f5c5b7c1
AM		 2382019-09-23 Alan Modra <amodra@gmail.com>
239
240 * m68k-dis.c: Include cpu-m68k.h
241
7beeaeb8
AM		 2422019-09-23 Alan Modra <amodra@gmail.com>
243
244 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
245 "elf/mips.h" earlier.
246
3f9aad11
JB		 2472018-09-20 Jan Beulich <jbeulich@suse.com>
248
249 PR gas/25012
250 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
251 with SReg operand.
252 * i386-tbl.h: Re-generate.
253
fd361982
AM		 2542019-09-18 Alan Modra <amodra@gmail.com>
255
256 * arc-ext.c: Update throughout for bfd section macro changes.
257
e0b2a78c
SM		 2582019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
259
260 * Makefile.in: Re-generate.
261 * configure: Re-generate.
262
7e9ad3a3
JW		 2632019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
264
265 * riscv-opc.c (riscv_opcodes): Change subset field
266 to insn_class field for all instructions.
267 (riscv_insn_types): Likewise.
268
bb695960
PB		 2692019-09-16 Phil Blundell <pb@pbcl.net>
270
271 * configure: Regenerated.
272
8063ab7e
MV		 2732019-09-10 Miod Vallat <miod@online.fr>
274
275 PR 24982
276 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
277
60391a25
PB		 2782019-09-09 Phil Blundell <pb@pbcl.net>
279
280 binutils 2.33 branch created.
281
f44b758d
NC		 2822019-09-03 Nick Clifton <nickc@redhat.com>
283
284 PR 24961
285 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
286 greater than zero before indexing via (bufcnt -1).
287
1e4b5e7d
NC		 2882019-09-03 Nick Clifton <nickc@redhat.com>
289
290 PR 24958
291 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
292 (MAX_SPEC_REG_NAME_LEN): Define.
293 (struct mmix_dis_info): Use defined constants for array lengths.
294 (get_reg_name): New function.
295 (get_sprec_reg_name): New function.
296 (print_insn_mmix): Use new functions.
297
c4a23bf8
SP		 2982019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
299
300 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
301 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
302 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
303
a051e2f3
KT		 3042019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
305
306 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
307 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
308 (aarch64_sys_reg_supported_p): Update checks for the above.
309
08132bdd
SP		 3102019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
311
312 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
313 cases MVE_SQRSHRL and MVE_UQRSHLL.
314 (print_insn_mve): Add case for specifier 'k' to check
315 specific bit of the instruction.
316
d88bdcb4
PA		 3172019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
318
319 PR 24854
320 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
321 encountering an unknown machine type.
322 (print_insn_arc): Handle arc_insn_length returning 0. In error
323 cases return -1 rather than calling abort.
324
bc750500
JB		 3252019-08-07 Jan Beulich <jbeulich@suse.com>
326
327 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
328 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
329 IgnoreSize.
330 * i386-tbl.h: Re-generate.
331
23d188c7
BW		 3322019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
333
334 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
335 instructions.
336
c0d6f62f
JW		 3372019-07-30 Mel Chen <mel.chen@sifive.com>
338
339 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
340 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
341
342 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
343 fscsr.
344
0f3f7167
CZ		 3452019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
346
347 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
348 and MPY class instructions.
349 (parse_option): Add nps400 option.
350 (print_arc_disassembler_options): Add nps400 info.
351
7e126ba3
CZ		 3522019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
353
354 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
355 (bspop): Likewise.
356 (modapp): Likewise.
357 * arc-opc.c (RAD_CHK): Add.
358 * arc-tbl.h: Regenerate.
359
a028026d
KT		 3602019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
361
362 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
363 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
364
ac79ff9e
NC		 3652019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
366
367 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
368 instructions as UNPREDICTABLE.
369
231097b0
JM		 3702019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
371
372 * bpf-desc.c: Regenerated.
373
1d942ae9
JB		 3742019-07-17 Jan Beulich <jbeulich@suse.com>
375
376 * i386-gen.c (static_assert): Define.
377 (main): Use it.
378 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
379 (Opcode_Modifier_Num): ... this.
380 (Mem): Delete.
381
dfd69174
JB		 3822019-07-16 Jan Beulich <jbeulich@suse.com>
383
384 * i386-gen.c (operand_types): Move RegMem ...
385 (opcode_modifiers): ... here.
386 * i386-opc.h (RegMem): Move to opcode modifer enum.
387 (union i386_operand_type): Move regmem field ...
388 (struct i386_opcode_modifier): ... here.
389 * i386-opc.tbl (RegMem): Define.
390 (mov, movq): Move RegMem on segment, control, debug, and test
391 register flavors.
392 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
393 to non-SSE2AVX flavor.
394 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
395 Move RegMem on register only flavors. Drop IgnoreSize from
396 legacy encoding flavors.
397 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
398 flavors.
399 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
400 register only flavors.
401 (vmovd): Move RegMem and drop IgnoreSize on register only
402 flavor. Change opcode and operand order to store form.
403 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
404
21df382b
JB		 4052019-07-16 Jan Beulich <jbeulich@suse.com>
406
407 * i386-gen.c (operand_type_init, operand_types): Replace SReg
408 entries.
409 * i386-opc.h (SReg2, SReg3): Replace by ...
410 (SReg): ... this.
411 (union i386_operand_type): Replace sreg fields.
412 * i386-opc.tbl (mov, ): Use SReg.
413 (push, pop): Likewies. Drop i386 and x86-64 specific segment
414 register flavors.
415 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
416 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
417
3719fd55
JM		 4182019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
419
420 * bpf-desc.c: Regenerate.
421 * bpf-opc.c: Likewise.
422 * bpf-opc.h: Likewise.
423
92434a14
JM		 4242019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
425
426 * bpf-desc.c: Regenerate.
427 * bpf-opc.c: Likewise.
428
43dd7626
HPN		 4292019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
430
431 * arm-dis.c (print_insn_coprocessor): Rename index to
432 index_operand.
433
98602811
JW		 4342019-07-05 Kito Cheng <kito.cheng@sifive.com>
435
436 * riscv-opc.c (riscv_insn_types): Add r4 type.
437
438 * riscv-opc.c (riscv_insn_types): Add b and j type.
439
440 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
441 format for sb type and correct s type.
442
01c1ee4a
RS		 4432019-07-02 Richard Sandiford <richard.sandiford@arm.com>
444
445 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
446 SVE FMOV alias of FCPY.
447
83adff69
RS		 4482019-07-02 Richard Sandiford <richard.sandiford@arm.com>
449
450 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
451 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
452
89418844
RS		 4532019-07-02 Richard Sandiford <richard.sandiford@arm.com>
454
455 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
456 registers in an instruction prefixed by MOVPRFX.
457
41be57ca
MM		 4582019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
459
460 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
461 sve_size_13 icode to account for variant behaviour of
462 pmull{t,b}.
463 * aarch64-dis-2.c: Regenerate.
464 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
465 sve_size_13 icode to account for variant behaviour of
466 pmull{t,b}.
467 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
468 (OP_SVE_VVV_Q_D): Add new qualifier.
469 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
470 (struct aarch64_opcode): Split pmull{t,b} into those requiring
471 AES and those not.
472
9d3bf266
JB		 4732019-07-01 Jan Beulich <jbeulich@suse.com>
474
475 * opcodes/i386-gen.c (operand_type_init): Remove
476 OPERAND_TYPE_VEC_IMM4 entry.
477 (operand_types): Remove Vec_Imm4.
478 * opcodes/i386-opc.h (Vec_Imm4): Delete.
479 (union i386_operand_type): Remove vec_imm4.
480 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
481 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
482
c3949f43
JB		 4832019-07-01 Jan Beulich <jbeulich@suse.com>
484
485 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
486 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
487 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
488 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
489 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
490 monitorx, mwaitx): Drop ImmExt from operand-less forms.
491 * i386-tbl.h: Re-generate.
492
5641ec01
JB		 4932019-07-01 Jan Beulich <jbeulich@suse.com>
494
495 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
496 register operands.
497 * i386-tbl.h: Re-generate.
498
79dec6b7
JB		 4992019-07-01 Jan Beulich <jbeulich@suse.com>
500
501 * i386-opc.tbl (C): New.
502 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
503 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
504 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
505 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
506 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
507 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
508 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
509 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
510 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
511 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
512 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
513 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
514 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
515 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
516 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
517 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
518 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
519 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
520 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
521 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
522 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
523 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
524 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
525 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
526 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
527 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
528 flavors.
529 * i386-tbl.h: Re-generate.
530
a0a1771e
JB		 5312019-07-01 Jan Beulich <jbeulich@suse.com>
532
533 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
534 register operands.
535 * i386-tbl.h: Re-generate.
536
cd546e7b
JB		 5372019-07-01 Jan Beulich <jbeulich@suse.com>
538
539 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
540 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
541 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
542 * i386-tbl.h: Re-generate.
543
e3bba3fc
JB		 5442019-07-01 Jan Beulich <jbeulich@suse.com>
545
546 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
547 Disp8MemShift from register only templates.
548 * i386-tbl.h: Re-generate.
549
36cc073e
JB		 5502019-07-01 Jan Beulich <jbeulich@suse.com>
551
552 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
553 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
554 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
555 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
556 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
557 EVEX_W_0F11_P_3_M_1): Delete.
558 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
559 EVEX_W_0F11_P_3): New.
560 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
561 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
562 MOD_EVEX_0F11_PREFIX_3 table entries.
563 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
564 PREFIX_EVEX_0F11 table entries.
565 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
566 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
567 EVEX_W_0F11_P_3_M_{0,1} table entries.
568
219920a7
JB		 5692019-07-01 Jan Beulich <jbeulich@suse.com>
570
571 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
572 Delete.
573
e395f487
L		 5742019-06-27 H.J. Lu <hongjiu.lu@intel.com>
575
576 PR binutils/24719
577 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
578 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
579 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
580 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
581 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
582 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
583 EVEX_LEN_0F38C7_R_6_P_2_W_1.
584 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
585 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
586 PREFIX_EVEX_0F38C6_REG_6 entries.
587 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
588 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
589 EVEX_W_0F38C7_R_6_P_2 entries.
590 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
591 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
592 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
593 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
594 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
595 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
596 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
597
2b7bcc87
JB		 5982019-06-27 Jan Beulich <jbeulich@suse.com>
599
600 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
601 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
602 VEX_LEN_0F2D_P_3): Delete.
603 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
604 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
605 (prefix_table): ... here.
606
c1dc7af5
JB		 6072019-06-27 Jan Beulich <jbeulich@suse.com>
608
609 * i386-dis.c (Iq): Delete.
610 (Id): New.
611 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
612 TBM insns.
613 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
614 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
615 (OP_E_memory): Also honor needindex when deciding whether an
616 address size prefix needs printing.
617 (OP_I): Remove handling of q_mode. Add handling of d_mode.
618
d7560e2d
JW		 6192019-06-26 Jim Wilson <jimw@sifive.com>
620
621 PR binutils/24739
622 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
623 Set info->display_endian to info->endian_code.
624
2c703856
JB		 6252019-06-25 Jan Beulich <jbeulich@suse.com>
626
627 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
628 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
629 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
630 OPERAND_TYPE_ACC64 entries.
631 * i386-init.h: Re-generate.
632
54fbadc0
JB		 6332019-06-25 Jan Beulich <jbeulich@suse.com>
634
635 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
636 Delete.
637 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
638 of dqa_mode.
639 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
640 entries here.
641 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
642 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
643
a280ab8e
JB		 6442019-06-25 Jan Beulich <jbeulich@suse.com>
645
646 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
647 variables.
648
e1a1babd
JB		 6492019-06-25 Jan Beulich <jbeulich@suse.com>
650
651 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
652 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
653 movnti.
d7560e2d 654 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 655 * i386-tbl.h: Re-generate.
656
b8364fa7
JB		 6572019-06-25 Jan Beulich <jbeulich@suse.com>
658
659 * i386-opc.tbl (and): Mark Imm8S form for optimization.
660 * i386-tbl.h: Re-generate.
661
ad692897
L		 6622019-06-21 H.J. Lu <hongjiu.lu@intel.com>
663
664 * i386-dis-evex.h: Break into ...
665 * i386-dis-evex-len.h: New file.
666 * i386-dis-evex-mod.h: Likewise.
667 * i386-dis-evex-prefix.h: Likewise.
668 * i386-dis-evex-reg.h: Likewise.
669 * i386-dis-evex-w.h: Likewise.
670 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
671 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
672 i386-dis-evex-mod.h.
673
f0a6222e
L		 6742019-06-19 H.J. Lu <hongjiu.lu@intel.com>
675
676 PR binutils/24700
677 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
678 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
679 EVEX_W_0F385B_P_2.
680 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
681 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
682 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
683 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
684 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
685 EVEX_LEN_0F385B_P_2_W_1.
686 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
687 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
688 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
689 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
690 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
691 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
692 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
693 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
694 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
695 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
696
6e1c90b7
L		 6972019-06-17 H.J. Lu <hongjiu.lu@intel.com>
698
699 PR binutils/24691
700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
701 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
702 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
703 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
704 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
705 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
706 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
707 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
708 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
709 EVEX_LEN_0F3A43_P_2_W_1.
710 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
711 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
712 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
713 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
714 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
715 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
716 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
717 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
718 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
719 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
720 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
721 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
722
bcc5a6eb
NC		 7232019-06-14 Nick Clifton <nickc@redhat.com>
724
725 * po/fr.po; Updated French translation.
726
e4c4ac46
SH		 7272019-06-13 Stafford Horne <shorne@gmail.com>
728
729 * or1k-asm.c: Regenerated.
730 * or1k-desc.c: Regenerated.
731 * or1k-desc.h: Regenerated.
732 * or1k-dis.c: Regenerated.
733 * or1k-ibld.c: Regenerated.
734 * or1k-opc.c: Regenerated.
735 * or1k-opc.h: Regenerated.
736 * or1k-opinst.c: Regenerated.
737
a0e44ef5
PB		 7382019-06-12 Peter Bergner <bergner@linux.ibm.com>
739
740 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
741
12efd68d
L		 7422019-06-05 H.J. Lu <hongjiu.lu@intel.com>
743
744 PR binutils/24633
745 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
746 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
747 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
748 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
749 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
750 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
751 EVEX_LEN_0F3A1B_P_2_W_1.
752 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
753 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
754 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
755 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
756 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
757 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
758 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
759 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
760
63c6fc6c
L		 7612019-06-04 H.J. Lu <hongjiu.lu@intel.com>
762
763 PR binutils/24626
764 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
765 EVEX.vvvv when disassembling VEX and EVEX instructions.
766 (OP_VEX): Set vex.register_specifier to 0 after readding
767 vex.register_specifier.
768 (OP_Vex_2src_1): Likewise.
769 (OP_Vex_2src_2): Likewise.
770 (OP_LWP_E): Likewise.
771 (OP_EX_Vex): Don't check vex.register_specifier.
772 (OP_XMM_Vex): Likewise.
773
9186c494
L		 7742019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
775 Lili Cui <lili.cui@intel.com>
776
777 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
778 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
779 instructions.
780 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
781 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
782 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
783 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
784 (i386_cpu_flags): Add cpuavx512_vp2intersect.
785 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
786 * i386-init.h: Regenerated.
787 * i386-tbl.h: Likewise.
788
5d79adc4
L		 7892019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
790 Lili Cui <lili.cui@intel.com>
791
792 * doc/c-i386.texi: Document enqcmd.
793 * testsuite/gas/i386/enqcmd-intel.d: New file.
794 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
795 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
796 * testsuite/gas/i386/enqcmd.d: Likewise.
797 * testsuite/gas/i386/enqcmd.s: Likewise.
798 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
799 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
800 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
801 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
802 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
803 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
804 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
805 and x86-64-enqcmd.
806
a9d96ab9
AH		 8072019-06-04 Alan Hayward <alan.hayward@arm.com>
808
809 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
810
4f6d070a
AM		 8112019-06-03 Alan Modra <amodra@gmail.com>
812
813 * ppc-dis.c (prefix_opcd_indices): Correct size.
814
a2f4b66c
L		 8152019-05-28 H.J. Lu <hongjiu.lu@intel.com>
816
817 PR gas/24625
818 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
819 Disp8ShiftVL.
820 * i386-tbl.h: Regenerated.
821
405b5bd8
AM		 8222019-05-24 Alan Modra <amodra@gmail.com>
823
824 * po/POTFILES.in: Regenerate.
825
8acf1435
PB		 8262019-05-24 Peter Bergner <bergner@linux.ibm.com>
827 Alan Modra <amodra@gmail.com>
828
829 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
830 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
831 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
832 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
833 XTOP>): Define and add entries.
834 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
835 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
836 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
837 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
838
dd7efa79
PB		 8392019-05-24 Peter Bergner <bergner@linux.ibm.com>
840 Alan Modra <amodra@gmail.com>
841
842 * ppc-dis.c (ppc_opts): Add "future" entry.
843 (PREFIX_OPCD_SEGS): Define.
844 (prefix_opcd_indices): New array.
845 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
846 (lookup_prefix): New function.
847 (print_insn_powerpc): Handle 64-bit prefix instructions.
848 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
849 (PMRR, POWERXX): Define.
850 (prefix_opcodes): New instruction table.
851 (prefix_num_opcodes): New constant.
852
79472b45
JM		 8532019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
854
855 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
856 * configure: Regenerated.
857 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
858 and cpu/bpf.opc.
859 (HFILES): Add bpf-desc.h and bpf-opc.h.
860 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
861 bpf-ibld.c and bpf-opc.c.
862 (BPF_DEPS): Define.
863 * Makefile.in: Regenerated.
864 * disassemble.c (ARCH_bpf): Define.
865 (disassembler): Add case for bfd_arch_bpf.
866 (disassemble_init_for_target): Likewise.
867 (enum epbf_isa_attr): Define.
868 * disassemble.h: extern print_insn_bpf.
869 * bpf-asm.c: Generated.
870 * bpf-opc.h: Likewise.
871 * bpf-opc.c: Likewise.
872 * bpf-ibld.c: Likewise.
873 * bpf-dis.c: Likewise.
874 * bpf-desc.h: Likewise.
875 * bpf-desc.c: Likewise.
876
ba6cd17f
SD		 8772019-05-21 Sudakshina Das <sudi.das@arm.com>
878
879 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
880 and VMSR with the new operands.
881
e39c1607
SD		 8822019-05-21 Sudakshina Das <sudi.das@arm.com>
883
884 * arm-dis.c (enum mve_instructions): New enum
885 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
886 and cneg.
887 (mve_opcodes): New instructions as above.
888 (is_mve_encoding_conflict): Add cases for csinc, csinv,
889 csneg and csel.
890 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
891
23d00a41
SD		 8922019-05-21 Sudakshina Das <sudi.das@arm.com>
893
894 * arm-dis.c (emun mve_instructions): Updated for new instructions.
895 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
896 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
897 uqshl, urshrl and urshr.
898 (is_mve_okay_in_it): Add new instructions to TRUE list.
899 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
900 (print_insn_mve): Updated to accept new %j,
901 %<bitfield>m and %<bitfield>n patterns.
902
cd4797ee
FS		 9032019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
904
905 * mips-opc.c (mips_builtin_opcodes): Change source register
906 constraint for DAUI.
907
999b073b
NC		 9082019-05-20 Nick Clifton <nickc@redhat.com>
909
910 * po/fr.po: Updated French translation.
911
14b456f2
AV		 9122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
913 Michael Collison <michael.collison@arm.com>
914
915 * arm-dis.c (thumb32_opcodes): Add new instructions.
916 (enum mve_instructions): Likewise.
917 (enum mve_undefined): Add new reasons.
918 (is_mve_encoding_conflict): Handle new instructions.
919 (is_mve_undefined): Likewise.
920 (is_mve_unpredictable): Likewise.
921 (print_mve_undefined): Likewise.
922 (print_mve_size): Likewise.
923
f49bb598
AV		 9242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
925 Michael Collison <michael.collison@arm.com>
926
927 * arm-dis.c (thumb32_opcodes): Add new instructions.
928 (enum mve_instructions): Likewise.
929 (is_mve_encoding_conflict): Handle new instructions.
930 (is_mve_undefined): Likewise.
931 (is_mve_unpredictable): Likewise.
932 (print_mve_size): Likewise.
933
56858bea
AV		 9342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
935 Michael Collison <michael.collison@arm.com>
936
937 * arm-dis.c (thumb32_opcodes): Add new instructions.
938 (enum mve_instructions): Likewise.
939 (is_mve_encoding_conflict): Likewise.
940 (is_mve_unpredictable): Likewise.
941 (print_mve_size): Likewise.
942
e523f101
AV		 9432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
944 Michael Collison <michael.collison@arm.com>
945
946 * arm-dis.c (thumb32_opcodes): Add new instructions.
947 (enum mve_instructions): Likewise.
948 (is_mve_encoding_conflict): Handle new instructions.
949 (is_mve_undefined): Likewise.
950 (is_mve_unpredictable): Likewise.
951 (print_mve_size): Likewise.
952
66dcaa5d
AV		 9532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
954 Michael Collison <michael.collison@arm.com>
955
956 * arm-dis.c (thumb32_opcodes): Add new instructions.
957 (enum mve_instructions): Likewise.
958 (is_mve_encoding_conflict): Handle new instructions.
959 (is_mve_undefined): Likewise.
960 (is_mve_unpredictable): Likewise.
961 (print_mve_size): Likewise.
962 (print_insn_mve): Likewise.
963
d052b9b7
AV		 9642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
965 Michael Collison <michael.collison@arm.com>
966
967 * arm-dis.c (thumb32_opcodes): Add new instructions.
968 (print_insn_thumb32): Handle new instructions.
969
ed63aa17
AV		 9702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
971 Michael Collison <michael.collison@arm.com>
972
973 * arm-dis.c (enum mve_instructions): Add new instructions.
974 (enum mve_undefined): Add new reasons.
975 (is_mve_encoding_conflict): Handle new instructions.
976 (is_mve_undefined): Likewise.
977 (is_mve_unpredictable): Likewise.
978 (print_mve_undefined): Likewise.
979 (print_mve_size): Likewise.
980 (print_mve_shift_n): Likewise.
981 (print_insn_mve): Likewise.
982
897b9bbc
AV		 9832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
984 Michael Collison <michael.collison@arm.com>
985
986 * arm-dis.c (enum mve_instructions): Add new instructions.
987 (is_mve_encoding_conflict): Handle new instructions.
988 (is_mve_unpredictable): Likewise.
989 (print_mve_rotate): Likewise.
990 (print_mve_size): Likewise.
991 (print_insn_mve): Likewise.
992
1c8f2df8
AV		 9932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
994 Michael Collison <michael.collison@arm.com>
995
996 * arm-dis.c (enum mve_instructions): Add new instructions.
997 (is_mve_encoding_conflict): Handle new instructions.
998 (is_mve_unpredictable): Likewise.
999 (print_mve_size): Likewise.
1000 (print_insn_mve): Likewise.
1001
d3b63143
AV		 10022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1003 Michael Collison <michael.collison@arm.com>
1004
1005 * arm-dis.c (enum mve_instructions): Add new instructions.
1006 (enum mve_undefined): Add new reasons.
1007 (is_mve_encoding_conflict): Handle new instructions.
1008 (is_mve_undefined): Likewise.
1009 (is_mve_unpredictable): Likewise.
1010 (print_mve_undefined): Likewise.
1011 (print_mve_size): Likewise.
1012 (print_insn_mve): Likewise.
1013
14925797
AV		 10142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1015 Michael Collison <michael.collison@arm.com>
1016
1017 * arm-dis.c (enum mve_instructions): Add new instructions.
1018 (is_mve_encoding_conflict): Handle new instructions.
1019 (is_mve_undefined): Likewise.
1020 (is_mve_unpredictable): Likewise.
1021 (print_mve_size): Likewise.
1022 (print_insn_mve): Likewise.
1023
c507f10b
AV		 10242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1025 Michael Collison <michael.collison@arm.com>
1026
1027 * arm-dis.c (enum mve_instructions): Add new instructions.
1028 (enum mve_unpredictable): Add new reasons.
1029 (enum mve_undefined): Likewise.
1030 (is_mve_okay_in_it): Handle new isntructions.
1031 (is_mve_encoding_conflict): Likewise.
1032 (is_mve_undefined): Likewise.
1033 (is_mve_unpredictable): Likewise.
1034 (print_mve_vmov_index): Likewise.
1035 (print_simd_imm8): Likewise.
1036 (print_mve_undefined): Likewise.
1037 (print_mve_unpredictable): Likewise.
1038 (print_mve_size): Likewise.
1039 (print_insn_mve): Likewise.
1040
bf0b396d
AV		 10412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1042 Michael Collison <michael.collison@arm.com>
1043
1044 * arm-dis.c (enum mve_instructions): Add new instructions.
1045 (enum mve_unpredictable): Add new reasons.
1046 (enum mve_undefined): Likewise.
1047 (is_mve_encoding_conflict): Handle new instructions.
1048 (is_mve_undefined): Likewise.
1049 (is_mve_unpredictable): Likewise.
1050 (print_mve_undefined): Likewise.
1051 (print_mve_unpredictable): Likewise.
1052 (print_mve_rounding_mode): Likewise.
1053 (print_mve_vcvt_size): Likewise.
1054 (print_mve_size): Likewise.
1055 (print_insn_mve): Likewise.
1056
ef1576a1
AV		 10572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1058 Michael Collison <michael.collison@arm.com>
1059
1060 * arm-dis.c (enum mve_instructions): Add new instructions.
1061 (enum mve_unpredictable): Add new reasons.
1062 (enum mve_undefined): Likewise.
1063 (is_mve_undefined): Handle new instructions.
1064 (is_mve_unpredictable): Likewise.
1065 (print_mve_undefined): Likewise.
1066 (print_mve_unpredictable): Likewise.
1067 (print_mve_size): Likewise.
1068 (print_insn_mve): Likewise.
1069
aef6d006
AV		 10702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1071 Michael Collison <michael.collison@arm.com>
1072
1073 * arm-dis.c (enum mve_instructions): Add new instructions.
1074 (enum mve_undefined): Add new reasons.
1075 (insns): Add new instructions.
1076 (is_mve_encoding_conflict):
1077 (print_mve_vld_str_addr): New print function.
1078 (is_mve_undefined): Handle new instructions.
1079 (is_mve_unpredictable): Likewise.
1080 (print_mve_undefined): Likewise.
1081 (print_mve_size): Likewise.
1082 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1083 (print_insn_mve): Handle new operands.
1084
04d54ace
AV		 10852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1086 Michael Collison <michael.collison@arm.com>
1087
1088 * arm-dis.c (enum mve_instructions): Add new instructions.
1089 (enum mve_unpredictable): Add new reasons.
1090 (is_mve_encoding_conflict): Handle new instructions.
1091 (is_mve_unpredictable): Likewise.
1092 (mve_opcodes): Add new instructions.
1093 (print_mve_unpredictable): Handle new reasons.
1094 (print_mve_register_blocks): New print function.
1095 (print_mve_size): Handle new instructions.
1096 (print_insn_mve): Likewise.
1097
9743db03
AV		 10982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1099 Michael Collison <michael.collison@arm.com>
1100
1101 * arm-dis.c (enum mve_instructions): Add new instructions.
1102 (enum mve_unpredictable): Add new reasons.
1103 (enum mve_undefined): Likewise.
1104 (is_mve_encoding_conflict): Handle new instructions.
1105 (is_mve_undefined): Likewise.
1106 (is_mve_unpredictable): Likewise.
1107 (coprocessor_opcodes): Move NEON VDUP from here...
1108 (neon_opcodes): ... to here.
1109 (mve_opcodes): Add new instructions.
1110 (print_mve_undefined): Handle new reasons.
1111 (print_mve_unpredictable): Likewise.
1112 (print_mve_size): Handle new instructions.
1113 (print_insn_neon): Handle vdup.
1114 (print_insn_mve): Handle new operands.
1115
143275ea
AV		 11162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1117 Michael Collison <michael.collison@arm.com>
1118
1119 * arm-dis.c (enum mve_instructions): Add new instructions.
1120 (enum mve_unpredictable): Add new values.
1121 (mve_opcodes): Add new instructions.
1122 (vec_condnames): New array with vector conditions.
1123 (mve_predicatenames): New array with predicate suffixes.
1124 (mve_vec_sizename): New array with vector sizes.
1125 (enum vpt_pred_state): New enum with vector predication states.
1126 (struct vpt_block): New struct type for vpt blocks.
1127 (vpt_block_state): Global struct to keep track of state.
1128 (mve_extract_pred_mask): New helper function.
1129 (num_instructions_vpt_block): Likewise.
1130 (mark_outside_vpt_block): Likewise.
1131 (mark_inside_vpt_block): Likewise.
1132 (invert_next_predicate_state): Likewise.
1133 (update_next_predicate_state): Likewise.
1134 (update_vpt_block_state): Likewise.
1135 (is_vpt_instruction): Likewise.
1136 (is_mve_encoding_conflict): Add entries for new instructions.
1137 (is_mve_unpredictable): Likewise.
1138 (print_mve_unpredictable): Handle new cases.
1139 (print_instruction_predicate): Likewise.
1140 (print_mve_size): New function.
1141 (print_vec_condition): New function.
1142 (print_insn_mve): Handle vpt blocks and new print operands.
1143
f08d8ce3
AV		 11442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1145
1146 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1147 8, 14 and 15 for Armv8.1-M Mainline.
1148
73cd51e5
AV		 11492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1150 Michael Collison <michael.collison@arm.com>
1151
1152 * arm-dis.c (enum mve_instructions): New enum.
1153 (enum mve_unpredictable): Likewise.
1154 (enum mve_undefined): Likewise.
1155 (struct mopcode32): New struct.
1156 (is_mve_okay_in_it): New function.
1157 (is_mve_architecture): Likewise.
1158 (arm_decode_field): Likewise.
1159 (arm_decode_field_multiple): Likewise.
1160 (is_mve_encoding_conflict): Likewise.
1161 (is_mve_undefined): Likewise.
1162 (is_mve_unpredictable): Likewise.
1163 (print_mve_undefined): Likewise.
1164 (print_mve_unpredictable): Likewise.
1165 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1166 (print_insn_mve): New function.
1167 (print_insn_thumb32): Handle MVE architecture.
1168 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1169
3076e594
NC		 11702019-05-10 Nick Clifton <nickc@redhat.com>
1171
1172 PR 24538
1173 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1174 end of the table prematurely.
1175
387e7624
FS		 11762019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1177
1178 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1179 macros for R6.
1180
0067be51
AM		 11812019-05-11 Alan Modra <amodra@gmail.com>
1182
1183 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1184 when -Mraw is in effect.
1185
42e6288f
MM		 11862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1187
1188 * aarch64-dis-2.c: Regenerate.
1189 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1190 (OP_SVE_BBB): New variant set.
1191 (OP_SVE_DDDD): New variant set.
1192 (OP_SVE_HHH): New variant set.
1193 (OP_SVE_HHHU): New variant set.
1194 (OP_SVE_SSS): New variant set.
1195 (OP_SVE_SSSU): New variant set.
1196 (OP_SVE_SHH): New variant set.
1197 (OP_SVE_SBBU): New variant set.
1198 (OP_SVE_DSS): New variant set.
1199 (OP_SVE_DHHU): New variant set.
1200 (OP_SVE_VMV_HSD_BHS): New variant set.
1201 (OP_SVE_VVU_HSD_BHS): New variant set.
1202 (OP_SVE_VVVU_SD_BH): New variant set.
1203 (OP_SVE_VVVU_BHSD): New variant set.
1204 (OP_SVE_VVV_QHD_DBS): New variant set.
1205 (OP_SVE_VVV_HSD_BHS): New variant set.
1206 (OP_SVE_VVV_HSD_BHS2): New variant set.
1207 (OP_SVE_VVV_BHS_HSD): New variant set.
1208 (OP_SVE_VV_BHS_HSD): New variant set.
1209 (OP_SVE_VVV_SD): New variant set.
1210 (OP_SVE_VVU_BHS_HSD): New variant set.
1211 (OP_SVE_VZVV_SD): New variant set.
1212 (OP_SVE_VZVV_BH): New variant set.
1213 (OP_SVE_VZV_SD): New variant set.
1214 (aarch64_opcode_table): Add sve2 instructions.
1215
28ed815a
MM		 12162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1217
1218 * aarch64-asm-2.c: Regenerated.
1219 * aarch64-dis-2.c: Regenerated.
1220 * aarch64-opc-2.c: Regenerated.
1221 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1222 for SVE_SHLIMM_UNPRED_22.
1223 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1224 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1225 operand.
1226
fd1dc4a0
MM		 12272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1228
1229 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1230 sve_size_tsz_bhs iclass encode.
1231 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1232 sve_size_tsz_bhs iclass decode.
1233
31e36ab3
MM		 12342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1235
1236 * aarch64-asm-2.c: Regenerated.
1237 * aarch64-dis-2.c: Regenerated.
1238 * aarch64-opc-2.c: Regenerated.
1239 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1240 for SVE_Zm4_11_INDEX.
1241 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1242 (fields): Handle SVE_i2h field.
1243 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1244 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1245
1be5f94f
MM		 12462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1247
1248 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1249 sve_shift_tsz_bhsd iclass encode.
1250 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1251 sve_shift_tsz_bhsd iclass decode.
1252
3c17238b
MM		 12532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1254
1255 * aarch64-asm-2.c: Regenerated.
1256 * aarch64-dis-2.c: Regenerated.
1257 * aarch64-opc-2.c: Regenerated.
1258 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1259 (aarch64_encode_variant_using_iclass): Handle
1260 sve_shift_tsz_hsd iclass encode.
1261 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1262 sve_shift_tsz_hsd iclass decode.
1263 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1264 for SVE_SHRIMM_UNPRED_22.
1265 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1266 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1267 operand.
1268
cd50a87a
MM		 12692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1270
1271 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1272 sve_size_013 iclass encode.
1273 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1274 sve_size_013 iclass decode.
1275
3c705960
MM		 12762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1277
1278 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1279 sve_size_bh iclass encode.
1280 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1281 sve_size_bh iclass decode.
1282
0a57e14f
MM		 12832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1284
1285 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1286 sve_size_sd2 iclass encode.
1287 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1288 sve_size_sd2 iclass decode.
1289 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1290 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1291
c469c864
MM		 12922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1293
1294 * aarch64-asm-2.c: Regenerated.
1295 * aarch64-dis-2.c: Regenerated.
1296 * aarch64-opc-2.c: Regenerated.
1297 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1298 for SVE_ADDR_ZX.
1299 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1300 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1301
116adc27
MM		 13022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1303
1304 * aarch64-asm-2.c: Regenerated.
1305 * aarch64-dis-2.c: Regenerated.
1306 * aarch64-opc-2.c: Regenerated.
1307 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1308 for SVE_Zm3_11_INDEX.
1309 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1310 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1311 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1312 fields.
1313 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1314
3bd82c86
MM		 13152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1316
1317 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1318 sve_size_hsd2 iclass encode.
1319 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1320 sve_size_hsd2 iclass decode.
1321 * aarch64-opc.c (fields): Handle SVE_size field.
1322 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1323
adccc507
MM		 13242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1325
1326 * aarch64-asm-2.c: Regenerated.
1327 * aarch64-dis-2.c: Regenerated.
1328 * aarch64-opc-2.c: Regenerated.
1329 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1330 for SVE_IMM_ROT3.
1331 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1332 (fields): Handle SVE_rot3 field.
1333 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1334 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1335
5cd99750
MM		 13362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1337
1338 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1339 instructions.
1340
7ce2460a
MM		 13412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1342
1343 * aarch64-tbl.h
1344 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1345 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1346 aarch64_feature_sve2bitperm): New feature sets.
1347 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1348 for feature set addresses.
1349 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1350 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1351
41cee089
FS		 13522019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1353 Faraz Shahbazker <fshahbazker@wavecomp.com>
1354
1355 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1356 argument and set ASE_EVA_R6 appropriately.
1357 (set_default_mips_dis_options): Pass ISA to above.
1358 (parse_mips_dis_option): Likewise.
1359 * mips-opc.c (EVAR6): New macro.
1360 (mips_builtin_opcodes): Add llwpe, scwpe.
1361
b83b4b13
SD		 13622019-05-01 Sudakshina Das <sudi.das@arm.com>
1363
1364 * aarch64-asm-2.c: Regenerated.
1365 * aarch64-dis-2.c: Regenerated.
1366 * aarch64-opc-2.c: Regenerated.
1367 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1368 AARCH64_OPND_TME_UIMM16.
1369 (aarch64_print_operand): Likewise.
1370 * aarch64-tbl.h (QL_IMM_NIL): New.
1371 (TME): New.
1372 (_TME_INSN): New.
1373 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1374
4a90ce95
JD		 13752019-04-29 John Darrington <john@darrington.wattle.id.au>
1376
1377 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1378
a45328b9
AB		 13792019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1380 Faraz Shahbazker <fshahbazker@wavecomp.com>
1381
1382 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1383
d10be0cb
JD		 13842019-04-24 John Darrington <john@darrington.wattle.id.au>
1385
1386 * s12z-opc.h: Add extern "C" bracketing to help
1387 users who wish to use this interface in c++ code.
1388
a679f24e
JD		 13892019-04-24 John Darrington <john@darrington.wattle.id.au>
1390
1391 * s12z-opc.c (bm_decode): Handle bit map operations with the
1392 "reserved0" mode.
1393
32c36c3c
AV		 13942019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1395
1396 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1397 specifier. Add entries for VLDR and VSTR of system registers.
1398 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1399 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1400 of %J and %K format specifier.
1401
efd6b359
AV		 14022019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1403
1404 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1405 Add new entries for VSCCLRM instruction.
1406 (print_insn_coprocessor): Handle new %C format control code.
1407
6b0dd094
AV		 14082019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1409
1410 * arm-dis.c (enum isa): New enum.
1411 (struct sopcode32): New structure.
1412 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1413 set isa field of all current entries to ANY.
1414 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1415 Only match an entry if its isa field allows the current mode.
1416
4b5a202f
AV		 14172019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1418
1419 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1420 CLRM.
1421 (print_insn_thumb32): Add logic to print %n CLRM register list.
1422
60f993ce
AV		 14232019-04-15 Sudakshina Das <sudi.das@arm.com>
1424
1425 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1426 and %Q patterns.
1427
f6b2b12d
AV		 14282019-04-15 Sudakshina Das <sudi.das@arm.com>
1429
1430 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1431 (print_insn_thumb32): Edit the switch case for %Z.
1432
1889da70
AV		 14332019-04-15 Sudakshina Das <sudi.das@arm.com>
1434
1435 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1436
65d1bc05
AV		 14372019-04-15 Sudakshina Das <sudi.das@arm.com>
1438
1439 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1440
1caf72a5
AV		 14412019-04-15 Sudakshina Das <sudi.das@arm.com>
1442
1443 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1444
f1c7f421
AV		 14452019-04-15 Sudakshina Das <sudi.das@arm.com>
1446
1447 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1448 Arm register with r13 and r15 unpredictable.
1449 (thumb32_opcodes): New instructions for bfx and bflx.
1450
4389b29a
AV		 14512019-04-15 Sudakshina Das <sudi.das@arm.com>
1452
1453 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1454
e5d6e09e
AV		 14552019-04-15 Sudakshina Das <sudi.das@arm.com>
1456
1457 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1458
e12437dc
AV		 14592019-04-15 Sudakshina Das <sudi.das@arm.com>
1460
1461 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1462
031254f2
AV		 14632019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1464
1465 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1466
e5a557ac
JD		 14672019-04-12 John Darrington <john@darrington.wattle.id.au>
1468
1469 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1470 "optr". ("operator" is a reserved word in c++).
1471
bd7ceb8d
SD		 14722019-04-11 Sudakshina Das <sudi.das@arm.com>
1473
1474 * aarch64-opc.c (aarch64_print_operand): Add case for
1475 AARCH64_OPND_Rt_SP.
1476 (verify_constraints): Likewise.
1477 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1478 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1479 to accept Rt|SP as first operand.
1480 (AARCH64_OPERANDS): Add new Rt_SP.
1481 * aarch64-asm-2.c: Regenerated.
1482 * aarch64-dis-2.c: Regenerated.
1483 * aarch64-opc-2.c: Regenerated.
1484
e54010f1
SD		 14852019-04-11 Sudakshina Das <sudi.das@arm.com>
1486
1487 * aarch64-asm-2.c: Regenerated.
1488 * aarch64-dis-2.c: Likewise.
1489 * aarch64-opc-2.c: Likewise.
1490 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1491
7e96e219
RS		 14922019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1493
1494 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1495
6f2791d5
L		 14962019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1497
1498 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1499 * i386-init.h: Regenerated.
1500
e392bad3
AM		 15012019-04-07 Alan Modra <amodra@gmail.com>
1502
1503 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1504 op_separator to control printing of spaces, comma and parens
1505 rather than need_comma, need_paren and spaces vars.
1506
dffaa15c
AM		 15072019-04-07 Alan Modra <amodra@gmail.com>
1508
1509 PR 24421
1510 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1511 (print_insn_neon, print_insn_arm): Likewise.
1512
d6aab7a1
XG		 15132019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1514
1515 * i386-dis-evex.h (evex_table): Updated to support BF16
1516 instructions.
1517 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1518 and EVEX_W_0F3872_P_3.
1519 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1520 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1521 * i386-opc.h (enum): Add CpuAVX512_BF16.
1522 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1523 * i386-opc.tbl: Add AVX512 BF16 instructions.
1524 * i386-init.h: Regenerated.
1525 * i386-tbl.h: Likewise.
1526
66e85460
AM		 15272019-04-05 Alan Modra <amodra@gmail.com>
1528
1529 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1530 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1531 to favour printing of "-" branch hint when using the "y" bit.
1532 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1533
c2b1c275
AM		 15342019-04-05 Alan Modra <amodra@gmail.com>
1535
1536 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1537 opcode until first operand is output.
1538
aae9718e
PB		 15392019-04-04 Peter Bergner <bergner@linux.ibm.com>
1540
1541 PR gas/24349
1542 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1543 (valid_bo_post_v2): Add support for 'at' branch hints.
1544 (insert_bo): Only error on branch on ctr.
1545 (get_bo_hint_mask): New function.
1546 (insert_boe): Add new 'branch_taken' formal argument. Add support
1547 for inserting 'at' branch hints.
1548 (extract_boe): Add new 'branch_taken' formal argument. Add support
1549 for extracting 'at' branch hints.
1550 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1551 (BOE): Delete operand.
1552 (BOM, BOP): New operands.
1553 (RM): Update value.
1554 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1555 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1556 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1557 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1558 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1559 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1560 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1561 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1562 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1563 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1564 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1565 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1566 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1567 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1568 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1569 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1570 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1571 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1572 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1573 bttarl+>: New extended mnemonics.
1574
96a86c01
AM		 15752019-03-28 Alan Modra <amodra@gmail.com>
1576
1577 PR 24390
1578 * ppc-opc.c (BTF): Define.
1579 (powerpc_opcodes): Use for mtfsb*.
1580 * ppc-dis.c (print_insn_powerpc): Print fields with both
1581 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1582
796d6298
TC		 15832019-03-25 Tamar Christina <tamar.christina@arm.com>
1584
1585 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1586 (mapping_symbol_for_insn): Implement new algorithm.
1587 (print_insn): Remove duplicate code.
1588
60df3720
TC		 15892019-03-25 Tamar Christina <tamar.christina@arm.com>
1590
1591 * aarch64-dis.c (print_insn_aarch64):
1592 Implement override.
1593
51457761
TC		 15942019-03-25 Tamar Christina <tamar.christina@arm.com>
1595
1596 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1597 order.
1598
53b2f36b
TC		 15992019-03-25 Tamar Christina <tamar.christina@arm.com>
1600
1601 * aarch64-dis.c (last_stop_offset): New.
1602 (print_insn_aarch64): Use stop_offset.
1603
89199bb5
L		 16042019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1605
1606 PR gas/24359
1607 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1608 CPU_ANY_AVX2_FLAGS.
1609 * i386-init.h: Regenerated.
1610
97ed31ae
L		 16112019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1612
1613 PR gas/24348
1614 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1615 vmovdqu16, vmovdqu32 and vmovdqu64.
1616 * i386-tbl.h: Regenerated.
1617
0919bfe9
AK		 16182019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1619
1620 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1621 from vstrszb, vstrszh, and vstrszf.
1622
16232019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1624
1625 * s390-opc.txt: Add instruction descriptions.
1626
21820ebe
JW		 16272019-02-08 Jim Wilson <jimw@sifive.com>
1628
1629 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1630 <bne>: Likewise.
1631
f7dd2fb2
TC		 16322019-02-07 Tamar Christina <tamar.christina@arm.com>
1633
1634 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1635
6456d318
TC		 16362019-02-07 Tamar Christina <tamar.christina@arm.com>
1637
1638 PR binutils/23212
1639 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1640 * aarch64-opc.c (verify_elem_sd): New.
1641 (fields): Add FLD_sz entr.
1642 * aarch64-tbl.h (_SIMD_INSN): New.
1643 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1644 fmulx scalar and vector by element isns.
1645
4a83b610
NC		 16462019-02-07 Nick Clifton <nickc@redhat.com>
1647
1648 * po/sv.po: Updated Swedish translation.
1649
fc60b8c8
AK		 16502019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1651
1652 * s390-mkopc.c (main): Accept arch13 as cpu string.
1653 * s390-opc.c: Add new instruction formats and instruction opcode
1654 masks.
1655 * s390-opc.txt: Add new arch13 instructions.
1656
e10620d3
TC		 16572019-01-25 Sudakshina Das <sudi.das@arm.com>
1658
1659 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1660 (aarch64_opcode): Change encoding for stg, stzg
1661 st2g and st2zg.
1662 * aarch64-asm-2.c: Regenerated.
1663 * aarch64-dis-2.c: Regenerated.
1664 * aarch64-opc-2.c: Regenerated.
1665
20a4ca55
SD		 16662019-01-25 Sudakshina Das <sudi.das@arm.com>
1667
1668 * aarch64-asm-2.c: Regenerated.
1669 * aarch64-dis-2.c: Likewise.
1670 * aarch64-opc-2.c: Likewise.
1671 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1672
550fd7bf
SD		 16732019-01-25 Sudakshina Das <sudi.das@arm.com>
1674 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1675
1676 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1677 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1678 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1679 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1680 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1681 case for ldstgv_indexed.
1682 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1683 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1684 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1685 * aarch64-asm-2.c: Regenerated.
1686 * aarch64-dis-2.c: Regenerated.
1687 * aarch64-opc-2.c: Regenerated.
1688
d9938630
NC		 16892019-01-23 Nick Clifton <nickc@redhat.com>
1690
1691 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1692
375cd423
NC		 16932019-01-21 Nick Clifton <nickc@redhat.com>
1694
1695 * po/de.po: Updated German translation.
1696 * po/uk.po: Updated Ukranian translation.
1697
57299f48
CX		 16982019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1699 * mips-dis.c (mips_arch_choices): Fix typo in
1700 gs464, gs464e and gs264e descriptors.
1701
f48dfe41
NC		 17022019-01-19 Nick Clifton <nickc@redhat.com>
1703
1704 * configure: Regenerate.
1705 * po/opcodes.pot: Regenerate.
1706
f974f26c
NC		 17072018-06-24 Nick Clifton <nickc@redhat.com>
1708
1709 2.32 branch created.
1710
39f286cd
JD		 17112019-01-09 John Darrington <john@darrington.wattle.id.au>
1712
448b8ca8
JD		 1713 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1714 if it is null.
1715 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1716 zero.
1717
3107326d
AP		 17182019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1719
1720 * configure: Regenerate.
1721
7e9ca91e
AM		 17222019-01-07 Alan Modra <amodra@gmail.com>
1723
1724 * configure: Regenerate.
1725 * po/POTFILES.in: Regenerate.
1726
ef1ad42b
JD		 17272019-01-03 John Darrington <john@darrington.wattle.id.au>
1728
1729 * s12z-opc.c: New file.
1730 * s12z-opc.h: New file.
1731 * s12z-dis.c: Removed all code not directly related to display
1732 of instructions. Used the interface provided by the new files
1733 instead.
1734 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1735 * Makefile.in: Regenerate.
ef1ad42b 1736 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1737 * configure: Regenerate.
ef1ad42b 1738
82704155
AM		 17392019-01-01 Alan Modra <amodra@gmail.com>
1740
1741 Update year range in copyright notice of all files.
1742
d5c04e1b 1743For older changes see ChangeLog-2018
3499769a 1744\f
d5c04e1b 1745Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1746
1747Copying and distribution of this file, with or without modification,
1748are permitted in any medium without royalty provided the copyright
1749notice and this notice are preserved.
1750
1751Local Variables:
1752mode: change-log
1753left-margin: 8
1754fill-column: 74
1755version-control: never
1756End:
GDB Binutils - Deliverables
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