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Remove backup ppc struct dis_private.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6f0e0752
AM		 12019-12-10 Alan Modra <amodra@gmail.com>
2
3 * ppc-dis.c (private): Delete variable.
4 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
5 (powerpc_init_dialect): Don't use global private.
6
e7c22a69
AM		 72019-12-10 Alan Modra <amodra@gmail.com>
8
9 * s12z-opc.c: Formatting.
10
0a6aef6b
AM		 112019-12-08 Alan Modra <amodra@gmail.com>
12
13 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
14 registers.
15
2dc4b12f
JB		 162019-12-05 Jan Beulich <jbeulich@suse.com>
17
18 * aarch64-tbl.h (aarch64_feature_crypto,
19 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
20 CRYPTO_V8_2_INSN): Delete.
21
378fd436
AM		 222019-12-05 Alan Modra <amodra@gmail.com>
23
24 PR 25249
25 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
26 (struct string_buf): New.
27 (strbuf): New function.
28 (get_field): Use strbuf rather than strdup of local temp.
29 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
30 (get_field_rfsl, get_field_imm15): Likewise.
31 (get_field_rd, get_field_r1, get_field_r2): Update macros.
32 (get_field_special): Likewise. Don't strcpy spr. Formatting.
33 (print_insn_microblaze): Formatting. Init and pass string_buf to
34 get_field functions.
35
0ba59a29
JB		 362019-12-04 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
39 * i386-tbl.h: Re-generate.
40
77ad8092
JB		 412019-12-04 Jan Beulich <jbeulich@suse.com>
42
43 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
44
3036c899
JB		 452019-12-04 Jan Beulich <jbeulich@suse.com>
46
47 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
48 forms.
49 (xbegin): Drop DefaultSize.
50 * i386-tbl.h: Re-generate.
51
8b301fbb
MI		 522019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
53
54 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
55 Change the coproc CRC conditions to use the extension
56 feature set, second word, base on ARM_EXT2_CRC.
57
6aa385b9
JB		 582019-11-14 Jan Beulich <jbeulich@suse.com>
59
60 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
61 * i386-tbl.h: Re-generate.
62
0cfa3eb3
JB		 632019-11-14 Jan Beulich <jbeulich@suse.com>
64
65 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
66 JumpInterSegment, and JumpAbsolute entries.
67 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
68 JUMP_ABSOLUTE): Define.
69 (struct i386_opcode_modifier): Extend jump field to 3 bits.
70 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
71 fields.
72 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
73 JumpInterSegment): Define.
74 * i386-tbl.h: Re-generate.
75
6f2f06be
JB		 762019-11-14 Jan Beulich <jbeulich@suse.com>
77
78 * i386-gen.c (operand_type_init): Remove
79 OPERAND_TYPE_JUMPABSOLUTE entry.
80 (opcode_modifiers): Add JumpAbsolute entry.
81 (operand_types): Remove JumpAbsolute entry.
82 * i386-opc.h (JumpAbsolute): Move between enums.
83 (struct i386_opcode_modifier): Add jumpabsolute field.
84 (union i386_operand_type): Remove jumpabsolute field.
85 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
86 * i386-init.h, i386-tbl.h: Re-generate.
87
601e8564
JB		 882019-11-14 Jan Beulich <jbeulich@suse.com>
89
90 * i386-gen.c (opcode_modifiers): Add AnySize entry.
91 (operand_types): Remove AnySize entry.
92 * i386-opc.h (AnySize): Move between enums.
93 (struct i386_opcode_modifier): Add anysize field.
94 (OTUnused): Un-comment.
95 (union i386_operand_type): Remove anysize field.
96 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
97 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
98 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
99 AnySize.
100 * i386-tbl.h: Re-generate.
101
7722d40a
JW		 1022019-11-12 Nelson Chu <nelson.chu@sifive.com>
103
104 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
105 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
106 use the floating point register (FPR).
107
ce760a76
MI		 1082019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
109
110 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
111 cmode 1101.
112 (is_mve_encoding_conflict): Update cmode conflict checks for
113 MVE_VMVN_IMM.
114
51c8edf6
JB		 1152019-11-12 Jan Beulich <jbeulich@suse.com>
116
117 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
118 entry.
119 (operand_types): Remove EsSeg entry.
120 (main): Replace stale use of OTMax.
121 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
122 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
123 (EsSeg): Delete.
124 (OTUnused): Comment out.
125 (union i386_operand_type): Remove esseg field.
126 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
127 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
128 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
129 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
130 * i386-init.h, i386-tbl.h: Re-generate.
131
474da251
JB		 1322019-11-12 Jan Beulich <jbeulich@suse.com>
133
134 * i386-gen.c (operand_instances): Add RegB entry.
135 * i386-opc.h (enum operand_instance): Add RegB.
136 * i386-opc.tbl (RegC, RegD, RegB): Define.
137 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
138 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
139 monitorx, mwaitx): Drop ImmExt and convert encodings
140 accordingly.
141 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
142 (edx, rdx): Add Instance=RegD.
143 (ebx, rbx): Add Instance=RegB.
144 * i386-tbl.h: Re-generate.
145
75e5731b
JB		 1462019-11-12 Jan Beulich <jbeulich@suse.com>
147
148 * i386-gen.c (operand_type_init): Adjust
149 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
150 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
151 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
152 (operand_instances): New.
153 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
154 (output_operand_type): New parameter "instance". Process it.
155 (process_i386_operand_type): New local variable "instance".
156 (main): Adjust static assertions.
157 * i386-opc.h (INSTANCE_WIDTH): Define.
158 (enum operand_instance): New.
159 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
160 (union i386_operand_type): Replace acc, inoutportreg, and
161 shiftcount by instance.
162 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
163 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
164 Add Instance=.
165 * i386-init.h, i386-tbl.h: Re-generate.
166
91802f3c
JB		 1672019-11-11 Jan Beulich <jbeulich@suse.com>
168
169 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
170 smaxp/sminp entries' "tied_operand" field to 2.
171
4f5fc85d
JB		 1722019-11-11 Jan Beulich <jbeulich@suse.com>
173
174 * aarch64-opc.c (operand_general_constraint_met_p): Replace
175 "index" local variable by that of the already existing "num".
176
dc2be329
L		 1772019-11-08 H.J. Lu <hongjiu.lu@intel.com>
178
179 PR gas/25167
180 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
181 * i386-tbl.h: Regenerated.
182
f74a6307
JB		 1832019-11-08 Jan Beulich <jbeulich@suse.com>
184
185 * i386-gen.c (operand_type_init): Add Class= to
186 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
187 OPERAND_TYPE_REGBND entry.
188 (operand_classes): Add RegMask and RegBND entries.
189 (operand_types): Drop RegMask and RegBND entry.
190 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
191 (RegMask, RegBND): Delete.
192 (union i386_operand_type): Remove regmask and regbnd fields.
193 * i386-opc.tbl (RegMask, RegBND): Define.
194 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
195 Class=RegBND.
196 * i386-init.h, i386-tbl.h: Re-generate.
197
3528c362
JB		 1982019-11-08 Jan Beulich <jbeulich@suse.com>
199
200 * i386-gen.c (operand_type_init): Add Class= to
201 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
202 OPERAND_TYPE_REGZMM entries.
203 (operand_classes): Add RegMMX and RegSIMD entries.
204 (operand_types): Drop RegMMX and RegSIMD entries.
205 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
206 (RegMMX, RegSIMD): Delete.
207 (union i386_operand_type): Remove regmmx and regsimd fields.
208 * i386-opc.tbl (RegMMX): Define.
209 (RegXMM, RegYMM, RegZMM): Add Class=.
210 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
211 Class=RegSIMD.
212 * i386-init.h, i386-tbl.h: Re-generate.
213
4a5c67ed
JB		 2142019-11-08 Jan Beulich <jbeulich@suse.com>
215
216 * i386-gen.c (operand_type_init): Add Class= to
217 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
218 entries.
219 (operand_classes): Add RegCR, RegDR, and RegTR entries.
220 (operand_types): Drop Control, Debug, and Test entries.
221 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
222 (Control, Debug, Test): Delete.
223 (union i386_operand_type): Remove control, debug, and test
224 fields.
225 * i386-opc.tbl (Control, Debug, Test): Define.
226 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
227 Class=RegDR, and Test by Class=RegTR.
228 * i386-init.h, i386-tbl.h: Re-generate.
229
00cee14f
JB		 2302019-11-08 Jan Beulich <jbeulich@suse.com>
231
232 * i386-gen.c (operand_type_init): Add Class= to
233 OPERAND_TYPE_SREG entry.
234 (operand_classes): Add SReg entry.
235 (operand_types): Drop SReg entry.
236 * i386-opc.h (enum operand_class): Add SReg.
237 (SReg): Delete.
238 (union i386_operand_type): Remove sreg field.
239 * i386-opc.tbl (SReg): Define.
240 * i386-reg.tbl: Replace SReg by Class=SReg.
241 * i386-init.h, i386-tbl.h: Re-generate.
242
bab6aec1
JB		 2432019-11-08 Jan Beulich <jbeulich@suse.com>
244
245 * i386-gen.c (operand_type_init): Add Class=. New
246 OPERAND_TYPE_ANYIMM entry.
247 (operand_classes): New.
248 (operand_types): Drop Reg entry.
249 (output_operand_type): New parameter "class". Process it.
250 (process_i386_operand_type): New local variable "class".
251 (main): Adjust static assertions.
252 * i386-opc.h (CLASS_WIDTH): Define.
253 (enum operand_class): New.
254 (Reg): Replace by Class. Adjust comment.
255 (union i386_operand_type): Replace reg by class.
256 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
257 Class=.
258 * i386-reg.tbl: Replace Reg by Class=Reg.
259 * i386-init.h: Re-generate.
260
1f4cd317
MM		 2612019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
262
263 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
264 (aarch64_opcode_table): Add data gathering hint mnemonic.
265 * opcodes/aarch64-dis-2.c: Account for new instruction.
266
616ce08e
MM		 2672019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
268
269 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
270
271
8382113f
MM		 2722019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
273
274 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
275 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
276 aarch64_feature_f64mm): New feature sets.
277 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
278 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
279 instructions.
280 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
281 macros.
282 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
283 (OP_SVE_QQQ): New qualifier.
284 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
285 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
286 the movprfx constraint.
287 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
288 (aarch64_opcode_table): Define new instructions smmla,
289 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
290 uzip{1/2}, trn{1/2}.
291 * aarch64-opc.c (operand_general_constraint_met_p): Handle
292 AARCH64_OPND_SVE_ADDR_RI_S4x32.
293 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
294 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
295 Account for new instructions.
296 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
297 S4x32 operand.
298 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
299
aab2c27d
MM		 3002019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3012019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
302
303 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
304 Armv8.6-A.
305 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
306 (neon_opcodes): Add bfloat SIMD instructions.
307 (print_insn_coprocessor): Add new control character %b to print
308 condition code without checking cp_num.
309 (print_insn_neon): Account for BFloat16 instructions that have no
310 special top-byte handling.
311
33593eaf
MM		 3122019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3132019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
314
315 * arm-dis.c (print_insn_coprocessor,
316 print_insn_generic_coprocessor): Create wrapper functions around
317 the implementation of the print_insn_coprocessor control codes.
318 (print_insn_coprocessor_1): Original print_insn_coprocessor
319 function that now takes which array to look at as an argument.
320 (print_insn_arm): Use both print_insn_coprocessor and
321 print_insn_generic_coprocessor.
322 (print_insn_thumb32): As above.
323
df678013
MM		 3242019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3252019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
326
327 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
328 in reglane special case.
329 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
330 aarch64_find_next_opcode): Account for new instructions.
331 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
332 in reglane special case.
333 * aarch64-opc.c (struct operand_qualifier_data): Add data for
334 new AARCH64_OPND_QLF_S_2H qualifier.
335 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
336 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
337 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
338 sets.
339 (BFLOAT_SVE, BFLOAT): New feature set macros.
340 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
341 instructions.
342 (aarch64_opcode_table): Define new instructions bfdot,
343 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
344 bfcvtn2, bfcvt.
345
8ae2d3d9
MM		 3462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3472019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
348
349 * aarch64-tbl.h (ARMV8_6): New macro.
350
142861df
JB		 3512019-11-07 Jan Beulich <jbeulich@suse.com>
352
353 * i386-dis.c (prefix_table): Add mcommit.
354 (rm_table): Add rdpru.
355 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
356 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
357 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
358 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
359 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
360 * i386-opc.tbl (mcommit, rdpru): New.
361 * i386-init.h, i386-tbl.h: Re-generate.
362
081e283f
JB		 3632019-11-07 Jan Beulich <jbeulich@suse.com>
364
365 * i386-dis.c (OP_Mwait): Drop local variable "names", use
366 "names32" instead.
367 (OP_Monitor): Drop local variable "op1_names", re-purpose
368 "names" for it instead, and replace former "names" uses by
369 "names32" ones.
370
c050c89a
JB		 3712019-11-07 Jan Beulich <jbeulich@suse.com>
372
373 PR/gas 25167
374 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
375 operand-less forms.
376 * opcodes/i386-tbl.h: Re-generate.
377
7abb8d81
JB		 3782019-11-05 Jan Beulich <jbeulich@suse.com>
379
380 * i386-dis.c (OP_Mwaitx): Delete.
381 (prefix_table): Use OP_Mwait for mwaitx entry.
382 (OP_Mwait): Also handle mwaitx.
383
267b8516
JB		 3842019-11-05 Jan Beulich <jbeulich@suse.com>
385
386 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
387 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
388 (prefix_table): Add respective entries.
389 (rm_table): Link to those entries.
390
f8687e93
JB		 3912019-11-05 Jan Beulich <jbeulich@suse.com>
392
393 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
394 (REG_0F1C_P_0_MOD_0): ... this.
395 (REG_0F1E_MOD_3): Rename to ...
396 (REG_0F1E_P_1_MOD_3): ... this.
397 (RM_0F01_REG_5): Rename to ...
398 (RM_0F01_REG_5_MOD_3): ... this.
399 (RM_0F01_REG_7): Rename to ...
400 (RM_0F01_REG_7_MOD_3): ... this.
401 (RM_0F1E_MOD_3_REG_7): Rename to ...
402 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
403 (RM_0FAE_REG_6): Rename to ...
404 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
405 (RM_0FAE_REG_7): Rename to ...
406 (RM_0FAE_REG_7_MOD_3): ... this.
407 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
408 (PREFIX_0F01_REG_5_MOD_0): ... this.
409 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
410 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
411 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
412 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
413 (PREFIX_0FAE_REG_0): Rename to ...
414 (PREFIX_0FAE_REG_0_MOD_3): ... this.
415 (PREFIX_0FAE_REG_1): Rename to ...
416 (PREFIX_0FAE_REG_1_MOD_3): ... this.
417 (PREFIX_0FAE_REG_2): Rename to ...
418 (PREFIX_0FAE_REG_2_MOD_3): ... this.
419 (PREFIX_0FAE_REG_3): Rename to ...
420 (PREFIX_0FAE_REG_3_MOD_3): ... this.
421 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
422 (PREFIX_0FAE_REG_4_MOD_0): ... this.
423 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
424 (PREFIX_0FAE_REG_4_MOD_3): ... this.
425 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
426 (PREFIX_0FAE_REG_5_MOD_0): ... this.
427 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
428 (PREFIX_0FAE_REG_5_MOD_3): ... this.
429 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
430 (PREFIX_0FAE_REG_6_MOD_0): ... this.
431 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
432 (PREFIX_0FAE_REG_6_MOD_3): ... this.
433 (PREFIX_0FAE_REG_7): Rename to ...
434 (PREFIX_0FAE_REG_7_MOD_0): ... this.
435 (PREFIX_MOD_0_0FC3): Rename to ...
436 (PREFIX_0FC3_MOD_0): ... this.
437 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
438 (PREFIX_0FC7_REG_6_MOD_0): ... this.
439 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
440 (PREFIX_0FC7_REG_6_MOD_3): ... this.
441 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
442 (PREFIX_0FC7_REG_7_MOD_3): ... this.
443 (reg_table, prefix_table, mod_table, rm_table): Adjust
444 accordingly.
445
5103274f
NC		 4462019-11-04 Nick Clifton <nickc@redhat.com>
447
448 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
449 of a v850 system register. Move the v850_sreg_names array into
450 this function.
451 (get_v850_reg_name): Likewise for ordinary register names.
452 (get_v850_vreg_name): Likewise for vector register names.
453 (get_v850_cc_name): Likewise for condition codes.
454 * get_v850_float_cc_name): Likewise for floating point condition
455 codes.
456 (get_v850_cacheop_name): Likewise for cache-ops.
457 (get_v850_prefop_name): Likewise for pref-ops.
458 (disassemble): Use the new accessor functions.
459
1820262b
DB		 4602019-10-30 Delia Burduv <delia.burduv@arm.com>
461
462 * aarch64-opc.c (print_immediate_offset_address): Don't print the
463 immediate for the writeback form of ldraa/ldrab if it is 0.
464 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
465 * aarch64-opc-2.c: Regenerated.
466
3cc17af5
JB		 4672019-10-30 Jan Beulich <jbeulich@suse.com>
468
469 * i386-gen.c (operand_type_shorthands): Delete.
470 (operand_type_init): Expand previous shorthands.
471 (set_bitfield_from_shorthand): Rename back to ...
472 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
473 of operand_type_init[].
474 (set_bitfield): Adjust call to the above function.
475 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
476 RegXMM, RegYMM, RegZMM): Define.
477 * i386-reg.tbl: Expand prior shorthands.
478
a2cebd03
JB		 4792019-10-30 Jan Beulich <jbeulich@suse.com>
480
481 * i386-gen.c (output_i386_opcode): Change order of fields
482 emitted to output.
483 * i386-opc.h (struct insn_template): Move operands field.
484 Convert extension_opcode field to unsigned short.
485 * i386-tbl.h: Re-generate.
486
507916b8
JB		 4872019-10-30 Jan Beulich <jbeulich@suse.com>
488
489 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
490 of W.
491 * i386-opc.h (W): Extend comment.
492 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
493 general purpose variants not allowing for byte operands.
494 * i386-tbl.h: Re-generate.
495
efea62b4
NC		 4962019-10-29 Nick Clifton <nickc@redhat.com>
497
498 * tic30-dis.c (print_branch): Correct size of operand array.
499
9adb2591
NC		 5002019-10-29 Nick Clifton <nickc@redhat.com>
501
502 * d30v-dis.c (print_insn): Check that operand index is valid
503 before attempting to access the operands array.
504
993a00a9
NC		 5052019-10-29 Nick Clifton <nickc@redhat.com>
506
507 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
508 locating the bit to be tested.
509
66a66a17
NC		 5102019-10-29 Nick Clifton <nickc@redhat.com>
511
512 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
513 values.
514 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
515 (print_insn_s12z): Check for illegal size values.
516
1ee3542c
NC		 5172019-10-28 Nick Clifton <nickc@redhat.com>
518
519 * csky-dis.c (csky_chars_to_number): Check for a negative
520 count. Use an unsigned integer to construct the return value.
521
bbf9a0b5
NC		 5222019-10-28 Nick Clifton <nickc@redhat.com>
523
524 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
525 operand buffer. Set value to 15 not 13.
526 (get_register_operand): Use OPERAND_BUFFER_LEN.
527 (get_indirect_operand): Likewise.
528 (print_two_operand): Likewise.
529 (print_three_operand): Likewise.
530 (print_oar_insn): Likewise.
531
d1e304bc
NC		 5322019-10-28 Nick Clifton <nickc@redhat.com>
533
534 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
535 (bit_extract_simple): Likewise.
536 (bit_copy): Likewise.
537 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
538 index_offset array are not accessed.
539
dee33451
NC		 5402019-10-28 Nick Clifton <nickc@redhat.com>
541
542 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
543 operand.
544
27cee81d
NC		 5452019-10-25 Nick Clifton <nickc@redhat.com>
546
547 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
548 access to opcodes.op array element.
549
de6d8dc2
NC		 5502019-10-23 Nick Clifton <nickc@redhat.com>
551
552 * rx-dis.c (get_register_name): Fix spelling typo in error
553 message.
554 (get_condition_name, get_flag_name, get_double_register_name)
555 (get_double_register_high_name, get_double_register_low_name)
556 (get_double_control_register_name, get_double_condition_name)
557 (get_opsize_name, get_size_name): Likewise.
558
6207ed28
NC		 5592019-10-22 Nick Clifton <nickc@redhat.com>
560
561 * rx-dis.c (get_size_name): New function. Provides safe
562 access to name array.
563 (get_opsize_name): Likewise.
564 (print_insn_rx): Use the accessor functions.
565
12234dfd
NC		 5662019-10-16 Nick Clifton <nickc@redhat.com>
567
568 * rx-dis.c (get_register_name): New function. Provides safe
569 access to name array.
570 (get_condition_name, get_flag_name, get_double_register_name)
571 (get_double_register_high_name, get_double_register_low_name)
572 (get_double_control_register_name, get_double_condition_name):
573 Likewise.
574 (print_insn_rx): Use the accessor functions.
575
1d378749
NC		 5762019-10-09 Nick Clifton <nickc@redhat.com>
577
578 PR 25041
579 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
580 instructions.
581
d241b910
JB		 5822019-10-07 Jan Beulich <jbeulich@suse.com>
583
584 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
585 (cmpsd): Likewise. Move EsSeg to other operand.
586 * opcodes/i386-tbl.h: Re-generate.
587
f5c5b7c1
AM		 5882019-09-23 Alan Modra <amodra@gmail.com>
589
590 * m68k-dis.c: Include cpu-m68k.h
591
7beeaeb8
AM		 5922019-09-23 Alan Modra <amodra@gmail.com>
593
594 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
595 "elf/mips.h" earlier.
596
3f9aad11
JB		 5972018-09-20 Jan Beulich <jbeulich@suse.com>
598
599 PR gas/25012
600 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
601 with SReg operand.
602 * i386-tbl.h: Re-generate.
603
fd361982
AM		 6042019-09-18 Alan Modra <amodra@gmail.com>
605
606 * arc-ext.c: Update throughout for bfd section macro changes.
607
e0b2a78c
SM		 6082019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
609
610 * Makefile.in: Re-generate.
611 * configure: Re-generate.
612
7e9ad3a3
JW		 6132019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
614
615 * riscv-opc.c (riscv_opcodes): Change subset field
616 to insn_class field for all instructions.
617 (riscv_insn_types): Likewise.
618
bb695960
PB		 6192019-09-16 Phil Blundell <pb@pbcl.net>
620
621 * configure: Regenerated.
622
8063ab7e
MV		 6232019-09-10 Miod Vallat <miod@online.fr>
624
625 PR 24982
626 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
627
60391a25
PB		 6282019-09-09 Phil Blundell <pb@pbcl.net>
629
630 binutils 2.33 branch created.
631
f44b758d
NC		 6322019-09-03 Nick Clifton <nickc@redhat.com>
633
634 PR 24961
635 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
636 greater than zero before indexing via (bufcnt -1).
637
1e4b5e7d
NC		 6382019-09-03 Nick Clifton <nickc@redhat.com>
639
640 PR 24958
641 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
642 (MAX_SPEC_REG_NAME_LEN): Define.
643 (struct mmix_dis_info): Use defined constants for array lengths.
644 (get_reg_name): New function.
645 (get_sprec_reg_name): New function.
646 (print_insn_mmix): Use new functions.
647
c4a23bf8
SP		 6482019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
649
650 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
651 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
652 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
653
a051e2f3
KT		 6542019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
655
656 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
657 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
658 (aarch64_sys_reg_supported_p): Update checks for the above.
659
08132bdd
SP		 6602019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
661
662 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
663 cases MVE_SQRSHRL and MVE_UQRSHLL.
664 (print_insn_mve): Add case for specifier 'k' to check
665 specific bit of the instruction.
666
d88bdcb4
PA		 6672019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
668
669 PR 24854
670 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
671 encountering an unknown machine type.
672 (print_insn_arc): Handle arc_insn_length returning 0. In error
673 cases return -1 rather than calling abort.
674
bc750500
JB		 6752019-08-07 Jan Beulich <jbeulich@suse.com>
676
677 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
678 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
679 IgnoreSize.
680 * i386-tbl.h: Re-generate.
681
23d188c7
BW		 6822019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
683
684 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
685 instructions.
686
c0d6f62f
JW		 6872019-07-30 Mel Chen <mel.chen@sifive.com>
688
689 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
690 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
691
692 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
693 fscsr.
694
0f3f7167
CZ		 6952019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
696
697 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
698 and MPY class instructions.
699 (parse_option): Add nps400 option.
700 (print_arc_disassembler_options): Add nps400 info.
701
7e126ba3
CZ		 7022019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
703
704 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
705 (bspop): Likewise.
706 (modapp): Likewise.
707 * arc-opc.c (RAD_CHK): Add.
708 * arc-tbl.h: Regenerate.
709
a028026d
KT		 7102019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
711
712 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
713 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
714
ac79ff9e
NC		 7152019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
716
717 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
718 instructions as UNPREDICTABLE.
719
231097b0
JM		 7202019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
721
722 * bpf-desc.c: Regenerated.
723
1d942ae9
JB		 7242019-07-17 Jan Beulich <jbeulich@suse.com>
725
726 * i386-gen.c (static_assert): Define.
727 (main): Use it.
728 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
729 (Opcode_Modifier_Num): ... this.
730 (Mem): Delete.
731
dfd69174
JB		 7322019-07-16 Jan Beulich <jbeulich@suse.com>
733
734 * i386-gen.c (operand_types): Move RegMem ...
735 (opcode_modifiers): ... here.
736 * i386-opc.h (RegMem): Move to opcode modifer enum.
737 (union i386_operand_type): Move regmem field ...
738 (struct i386_opcode_modifier): ... here.
739 * i386-opc.tbl (RegMem): Define.
740 (mov, movq): Move RegMem on segment, control, debug, and test
741 register flavors.
742 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
743 to non-SSE2AVX flavor.
744 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
745 Move RegMem on register only flavors. Drop IgnoreSize from
746 legacy encoding flavors.
747 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
748 flavors.
749 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
750 register only flavors.
751 (vmovd): Move RegMem and drop IgnoreSize on register only
752 flavor. Change opcode and operand order to store form.
753 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
754
21df382b
JB		 7552019-07-16 Jan Beulich <jbeulich@suse.com>
756
757 * i386-gen.c (operand_type_init, operand_types): Replace SReg
758 entries.
759 * i386-opc.h (SReg2, SReg3): Replace by ...
760 (SReg): ... this.
761 (union i386_operand_type): Replace sreg fields.
762 * i386-opc.tbl (mov, ): Use SReg.
763 (push, pop): Likewies. Drop i386 and x86-64 specific segment
764 register flavors.
765 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
766 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
767
3719fd55
JM		 7682019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
769
770 * bpf-desc.c: Regenerate.
771 * bpf-opc.c: Likewise.
772 * bpf-opc.h: Likewise.
773
92434a14
JM		 7742019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
775
776 * bpf-desc.c: Regenerate.
777 * bpf-opc.c: Likewise.
778
43dd7626
HPN		 7792019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
780
781 * arm-dis.c (print_insn_coprocessor): Rename index to
782 index_operand.
783
98602811
JW		 7842019-07-05 Kito Cheng <kito.cheng@sifive.com>
785
786 * riscv-opc.c (riscv_insn_types): Add r4 type.
787
788 * riscv-opc.c (riscv_insn_types): Add b and j type.
789
790 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
791 format for sb type and correct s type.
792
01c1ee4a
RS		 7932019-07-02 Richard Sandiford <richard.sandiford@arm.com>
794
795 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
796 SVE FMOV alias of FCPY.
797
83adff69
RS		 7982019-07-02 Richard Sandiford <richard.sandiford@arm.com>
799
800 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
801 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
802
89418844
RS		 8032019-07-02 Richard Sandiford <richard.sandiford@arm.com>
804
805 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
806 registers in an instruction prefixed by MOVPRFX.
807
41be57ca
MM		 8082019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
809
810 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
811 sve_size_13 icode to account for variant behaviour of
812 pmull{t,b}.
813 * aarch64-dis-2.c: Regenerate.
814 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
815 sve_size_13 icode to account for variant behaviour of
816 pmull{t,b}.
817 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
818 (OP_SVE_VVV_Q_D): Add new qualifier.
819 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
820 (struct aarch64_opcode): Split pmull{t,b} into those requiring
821 AES and those not.
822
9d3bf266
JB		 8232019-07-01 Jan Beulich <jbeulich@suse.com>
824
825 * opcodes/i386-gen.c (operand_type_init): Remove
826 OPERAND_TYPE_VEC_IMM4 entry.
827 (operand_types): Remove Vec_Imm4.
828 * opcodes/i386-opc.h (Vec_Imm4): Delete.
829 (union i386_operand_type): Remove vec_imm4.
830 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
831 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
832
c3949f43
JB		 8332019-07-01 Jan Beulich <jbeulich@suse.com>
834
835 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
836 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
837 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
838 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
839 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
840 monitorx, mwaitx): Drop ImmExt from operand-less forms.
841 * i386-tbl.h: Re-generate.
842
5641ec01
JB		 8432019-07-01 Jan Beulich <jbeulich@suse.com>
844
845 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
846 register operands.
847 * i386-tbl.h: Re-generate.
848
79dec6b7
JB		 8492019-07-01 Jan Beulich <jbeulich@suse.com>
850
851 * i386-opc.tbl (C): New.
852 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
853 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
854 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
855 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
856 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
857 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
858 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
859 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
860 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
861 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
862 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
863 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
864 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
865 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
866 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
867 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
868 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
869 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
870 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
871 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
872 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
873 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
874 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
875 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
876 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
877 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
878 flavors.
879 * i386-tbl.h: Re-generate.
880
a0a1771e
JB		 8812019-07-01 Jan Beulich <jbeulich@suse.com>
882
883 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
884 register operands.
885 * i386-tbl.h: Re-generate.
886
cd546e7b
JB		 8872019-07-01 Jan Beulich <jbeulich@suse.com>
888
889 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
890 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
891 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
892 * i386-tbl.h: Re-generate.
893
e3bba3fc
JB		 8942019-07-01 Jan Beulich <jbeulich@suse.com>
895
896 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
897 Disp8MemShift from register only templates.
898 * i386-tbl.h: Re-generate.
899
36cc073e
JB		 9002019-07-01 Jan Beulich <jbeulich@suse.com>
901
902 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
903 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
904 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
905 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
906 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
907 EVEX_W_0F11_P_3_M_1): Delete.
908 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
909 EVEX_W_0F11_P_3): New.
910 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
911 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
912 MOD_EVEX_0F11_PREFIX_3 table entries.
913 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
914 PREFIX_EVEX_0F11 table entries.
915 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
916 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
917 EVEX_W_0F11_P_3_M_{0,1} table entries.
918
219920a7
JB		 9192019-07-01 Jan Beulich <jbeulich@suse.com>
920
921 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
922 Delete.
923
e395f487
L		 9242019-06-27 H.J. Lu <hongjiu.lu@intel.com>
925
926 PR binutils/24719
927 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
928 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
929 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
930 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
931 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
932 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
933 EVEX_LEN_0F38C7_R_6_P_2_W_1.
934 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
935 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
936 PREFIX_EVEX_0F38C6_REG_6 entries.
937 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
938 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
939 EVEX_W_0F38C7_R_6_P_2 entries.
940 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
941 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
942 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
943 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
944 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
945 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
946 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
947
2b7bcc87
JB		 9482019-06-27 Jan Beulich <jbeulich@suse.com>
949
950 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
951 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
952 VEX_LEN_0F2D_P_3): Delete.
953 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
954 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
955 (prefix_table): ... here.
956
c1dc7af5
JB		 9572019-06-27 Jan Beulich <jbeulich@suse.com>
958
959 * i386-dis.c (Iq): Delete.
960 (Id): New.
961 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
962 TBM insns.
963 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
964 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
965 (OP_E_memory): Also honor needindex when deciding whether an
966 address size prefix needs printing.
967 (OP_I): Remove handling of q_mode. Add handling of d_mode.
968
d7560e2d
JW		 9692019-06-26 Jim Wilson <jimw@sifive.com>
970
971 PR binutils/24739
972 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
973 Set info->display_endian to info->endian_code.
974
2c703856
JB		 9752019-06-25 Jan Beulich <jbeulich@suse.com>
976
977 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
978 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
979 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
980 OPERAND_TYPE_ACC64 entries.
981 * i386-init.h: Re-generate.
982
54fbadc0
JB		 9832019-06-25 Jan Beulich <jbeulich@suse.com>
984
985 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
986 Delete.
987 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
988 of dqa_mode.
989 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
990 entries here.
991 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
992 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
993
a280ab8e
JB		 9942019-06-25 Jan Beulich <jbeulich@suse.com>
995
996 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
997 variables.
998
e1a1babd
JB		 9992019-06-25 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1002 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1003 movnti.
d7560e2d 1004 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1005 * i386-tbl.h: Re-generate.
1006
b8364fa7
JB		 10072019-06-25 Jan Beulich <jbeulich@suse.com>
1008
1009 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1010 * i386-tbl.h: Re-generate.
1011
ad692897
L		 10122019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 * i386-dis-evex.h: Break into ...
1015 * i386-dis-evex-len.h: New file.
1016 * i386-dis-evex-mod.h: Likewise.
1017 * i386-dis-evex-prefix.h: Likewise.
1018 * i386-dis-evex-reg.h: Likewise.
1019 * i386-dis-evex-w.h: Likewise.
1020 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1021 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1022 i386-dis-evex-mod.h.
1023
f0a6222e
L		 10242019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1025
1026 PR binutils/24700
1027 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1028 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1029 EVEX_W_0F385B_P_2.
1030 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1031 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1032 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1033 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1034 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1035 EVEX_LEN_0F385B_P_2_W_1.
1036 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1037 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1038 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1039 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1040 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1041 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1042 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1043 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1044 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1045 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1046
6e1c90b7
L		 10472019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1048
1049 PR binutils/24691
1050 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1051 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1052 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1053 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1054 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1055 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1056 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1057 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1058 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1059 EVEX_LEN_0F3A43_P_2_W_1.
1060 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1061 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1062 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1063 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1064 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1065 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1066 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1067 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1068 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1069 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1070 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1071 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1072
bcc5a6eb
NC		 10732019-06-14 Nick Clifton <nickc@redhat.com>
1074
1075 * po/fr.po; Updated French translation.
1076
e4c4ac46
SH		 10772019-06-13 Stafford Horne <shorne@gmail.com>
1078
1079 * or1k-asm.c: Regenerated.
1080 * or1k-desc.c: Regenerated.
1081 * or1k-desc.h: Regenerated.
1082 * or1k-dis.c: Regenerated.
1083 * or1k-ibld.c: Regenerated.
1084 * or1k-opc.c: Regenerated.
1085 * or1k-opc.h: Regenerated.
1086 * or1k-opinst.c: Regenerated.
1087
a0e44ef5
PB		 10882019-06-12 Peter Bergner <bergner@linux.ibm.com>
1089
1090 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1091
12efd68d
L		 10922019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1093
1094 PR binutils/24633
1095 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1096 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1097 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1098 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1099 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1100 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1101 EVEX_LEN_0F3A1B_P_2_W_1.
1102 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1103 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1104 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1105 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1106 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1107 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1108 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1109 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1110
63c6fc6c
L		 11112019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1112
1113 PR binutils/24626
1114 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1115 EVEX.vvvv when disassembling VEX and EVEX instructions.
1116 (OP_VEX): Set vex.register_specifier to 0 after readding
1117 vex.register_specifier.
1118 (OP_Vex_2src_1): Likewise.
1119 (OP_Vex_2src_2): Likewise.
1120 (OP_LWP_E): Likewise.
1121 (OP_EX_Vex): Don't check vex.register_specifier.
1122 (OP_XMM_Vex): Likewise.
1123
9186c494
L		 11242019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1125 Lili Cui <lili.cui@intel.com>
1126
1127 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1128 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1129 instructions.
1130 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1131 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1132 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1133 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1134 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1135 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1136 * i386-init.h: Regenerated.
1137 * i386-tbl.h: Likewise.
1138
5d79adc4
L		 11392019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1140 Lili Cui <lili.cui@intel.com>
1141
1142 * doc/c-i386.texi: Document enqcmd.
1143 * testsuite/gas/i386/enqcmd-intel.d: New file.
1144 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1145 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1146 * testsuite/gas/i386/enqcmd.d: Likewise.
1147 * testsuite/gas/i386/enqcmd.s: Likewise.
1148 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1149 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1150 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1151 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1152 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1153 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1154 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1155 and x86-64-enqcmd.
1156
a9d96ab9
AH		 11572019-06-04 Alan Hayward <alan.hayward@arm.com>
1158
1159 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1160
4f6d070a
AM		 11612019-06-03 Alan Modra <amodra@gmail.com>
1162
1163 * ppc-dis.c (prefix_opcd_indices): Correct size.
1164
a2f4b66c
L		 11652019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1166
1167 PR gas/24625
1168 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1169 Disp8ShiftVL.
1170 * i386-tbl.h: Regenerated.
1171
405b5bd8
AM		 11722019-05-24 Alan Modra <amodra@gmail.com>
1173
1174 * po/POTFILES.in: Regenerate.
1175
8acf1435
PB		 11762019-05-24 Peter Bergner <bergner@linux.ibm.com>
1177 Alan Modra <amodra@gmail.com>
1178
1179 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1180 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1181 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1182 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1183 XTOP>): Define and add entries.
1184 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1185 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1186 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1187 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1188
dd7efa79
PB		 11892019-05-24 Peter Bergner <bergner@linux.ibm.com>
1190 Alan Modra <amodra@gmail.com>
1191
1192 * ppc-dis.c (ppc_opts): Add "future" entry.
1193 (PREFIX_OPCD_SEGS): Define.
1194 (prefix_opcd_indices): New array.
1195 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1196 (lookup_prefix): New function.
1197 (print_insn_powerpc): Handle 64-bit prefix instructions.
1198 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1199 (PMRR, POWERXX): Define.
1200 (prefix_opcodes): New instruction table.
1201 (prefix_num_opcodes): New constant.
1202
79472b45
JM		 12032019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1204
1205 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1206 * configure: Regenerated.
1207 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1208 and cpu/bpf.opc.
1209 (HFILES): Add bpf-desc.h and bpf-opc.h.
1210 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1211 bpf-ibld.c and bpf-opc.c.
1212 (BPF_DEPS): Define.
1213 * Makefile.in: Regenerated.
1214 * disassemble.c (ARCH_bpf): Define.
1215 (disassembler): Add case for bfd_arch_bpf.
1216 (disassemble_init_for_target): Likewise.
1217 (enum epbf_isa_attr): Define.
1218 * disassemble.h: extern print_insn_bpf.
1219 * bpf-asm.c: Generated.
1220 * bpf-opc.h: Likewise.
1221 * bpf-opc.c: Likewise.
1222 * bpf-ibld.c: Likewise.
1223 * bpf-dis.c: Likewise.
1224 * bpf-desc.h: Likewise.
1225 * bpf-desc.c: Likewise.
1226
ba6cd17f
SD		 12272019-05-21 Sudakshina Das <sudi.das@arm.com>
1228
1229 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1230 and VMSR with the new operands.
1231
e39c1607
SD		 12322019-05-21 Sudakshina Das <sudi.das@arm.com>
1233
1234 * arm-dis.c (enum mve_instructions): New enum
1235 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1236 and cneg.
1237 (mve_opcodes): New instructions as above.
1238 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1239 csneg and csel.
1240 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1241
23d00a41
SD		 12422019-05-21 Sudakshina Das <sudi.das@arm.com>
1243
1244 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1245 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1246 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1247 uqshl, urshrl and urshr.
1248 (is_mve_okay_in_it): Add new instructions to TRUE list.
1249 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1250 (print_insn_mve): Updated to accept new %j,
1251 %<bitfield>m and %<bitfield>n patterns.
1252
cd4797ee
FS		 12532019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1254
1255 * mips-opc.c (mips_builtin_opcodes): Change source register
1256 constraint for DAUI.
1257
999b073b
NC		 12582019-05-20 Nick Clifton <nickc@redhat.com>
1259
1260 * po/fr.po: Updated French translation.
1261
14b456f2
AV		 12622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1263 Michael Collison <michael.collison@arm.com>
1264
1265 * arm-dis.c (thumb32_opcodes): Add new instructions.
1266 (enum mve_instructions): Likewise.
1267 (enum mve_undefined): Add new reasons.
1268 (is_mve_encoding_conflict): Handle new instructions.
1269 (is_mve_undefined): Likewise.
1270 (is_mve_unpredictable): Likewise.
1271 (print_mve_undefined): Likewise.
1272 (print_mve_size): Likewise.
1273
f49bb598
AV		 12742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1275 Michael Collison <michael.collison@arm.com>
1276
1277 * arm-dis.c (thumb32_opcodes): Add new instructions.
1278 (enum mve_instructions): Likewise.
1279 (is_mve_encoding_conflict): Handle new instructions.
1280 (is_mve_undefined): Likewise.
1281 (is_mve_unpredictable): Likewise.
1282 (print_mve_size): Likewise.
1283
56858bea
AV		 12842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1285 Michael Collison <michael.collison@arm.com>
1286
1287 * arm-dis.c (thumb32_opcodes): Add new instructions.
1288 (enum mve_instructions): Likewise.
1289 (is_mve_encoding_conflict): Likewise.
1290 (is_mve_unpredictable): Likewise.
1291 (print_mve_size): Likewise.
1292
e523f101
AV		 12932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1295
1296 * arm-dis.c (thumb32_opcodes): Add new instructions.
1297 (enum mve_instructions): Likewise.
1298 (is_mve_encoding_conflict): Handle new instructions.
1299 (is_mve_undefined): Likewise.
1300 (is_mve_unpredictable): Likewise.
1301 (print_mve_size): Likewise.
1302
66dcaa5d
AV		 13032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1304 Michael Collison <michael.collison@arm.com>
1305
1306 * arm-dis.c (thumb32_opcodes): Add new instructions.
1307 (enum mve_instructions): Likewise.
1308 (is_mve_encoding_conflict): Handle new instructions.
1309 (is_mve_undefined): Likewise.
1310 (is_mve_unpredictable): Likewise.
1311 (print_mve_size): Likewise.
1312 (print_insn_mve): Likewise.
1313
d052b9b7
AV		 13142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1315 Michael Collison <michael.collison@arm.com>
1316
1317 * arm-dis.c (thumb32_opcodes): Add new instructions.
1318 (print_insn_thumb32): Handle new instructions.
1319
ed63aa17
AV		 13202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1321 Michael Collison <michael.collison@arm.com>
1322
1323 * arm-dis.c (enum mve_instructions): Add new instructions.
1324 (enum mve_undefined): Add new reasons.
1325 (is_mve_encoding_conflict): Handle new instructions.
1326 (is_mve_undefined): Likewise.
1327 (is_mve_unpredictable): Likewise.
1328 (print_mve_undefined): Likewise.
1329 (print_mve_size): Likewise.
1330 (print_mve_shift_n): Likewise.
1331 (print_insn_mve): Likewise.
1332
897b9bbc
AV		 13332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1334 Michael Collison <michael.collison@arm.com>
1335
1336 * arm-dis.c (enum mve_instructions): Add new instructions.
1337 (is_mve_encoding_conflict): Handle new instructions.
1338 (is_mve_unpredictable): Likewise.
1339 (print_mve_rotate): Likewise.
1340 (print_mve_size): Likewise.
1341 (print_insn_mve): Likewise.
1342
1c8f2df8
AV		 13432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1344 Michael Collison <michael.collison@arm.com>
1345
1346 * arm-dis.c (enum mve_instructions): Add new instructions.
1347 (is_mve_encoding_conflict): Handle new instructions.
1348 (is_mve_unpredictable): Likewise.
1349 (print_mve_size): Likewise.
1350 (print_insn_mve): Likewise.
1351
d3b63143
AV		 13522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1353 Michael Collison <michael.collison@arm.com>
1354
1355 * arm-dis.c (enum mve_instructions): Add new instructions.
1356 (enum mve_undefined): Add new reasons.
1357 (is_mve_encoding_conflict): Handle new instructions.
1358 (is_mve_undefined): Likewise.
1359 (is_mve_unpredictable): Likewise.
1360 (print_mve_undefined): Likewise.
1361 (print_mve_size): Likewise.
1362 (print_insn_mve): Likewise.
1363
14925797
AV		 13642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1365 Michael Collison <michael.collison@arm.com>
1366
1367 * arm-dis.c (enum mve_instructions): Add new instructions.
1368 (is_mve_encoding_conflict): Handle new instructions.
1369 (is_mve_undefined): Likewise.
1370 (is_mve_unpredictable): Likewise.
1371 (print_mve_size): Likewise.
1372 (print_insn_mve): Likewise.
1373
c507f10b
AV		 13742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1375 Michael Collison <michael.collison@arm.com>
1376
1377 * arm-dis.c (enum mve_instructions): Add new instructions.
1378 (enum mve_unpredictable): Add new reasons.
1379 (enum mve_undefined): Likewise.
1380 (is_mve_okay_in_it): Handle new isntructions.
1381 (is_mve_encoding_conflict): Likewise.
1382 (is_mve_undefined): Likewise.
1383 (is_mve_unpredictable): Likewise.
1384 (print_mve_vmov_index): Likewise.
1385 (print_simd_imm8): Likewise.
1386 (print_mve_undefined): Likewise.
1387 (print_mve_unpredictable): Likewise.
1388 (print_mve_size): Likewise.
1389 (print_insn_mve): Likewise.
1390
bf0b396d
AV		 13912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1392 Michael Collison <michael.collison@arm.com>
1393
1394 * arm-dis.c (enum mve_instructions): Add new instructions.
1395 (enum mve_unpredictable): Add new reasons.
1396 (enum mve_undefined): Likewise.
1397 (is_mve_encoding_conflict): Handle new instructions.
1398 (is_mve_undefined): Likewise.
1399 (is_mve_unpredictable): Likewise.
1400 (print_mve_undefined): Likewise.
1401 (print_mve_unpredictable): Likewise.
1402 (print_mve_rounding_mode): Likewise.
1403 (print_mve_vcvt_size): Likewise.
1404 (print_mve_size): Likewise.
1405 (print_insn_mve): Likewise.
1406
ef1576a1
AV		 14072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1408 Michael Collison <michael.collison@arm.com>
1409
1410 * arm-dis.c (enum mve_instructions): Add new instructions.
1411 (enum mve_unpredictable): Add new reasons.
1412 (enum mve_undefined): Likewise.
1413 (is_mve_undefined): Handle new instructions.
1414 (is_mve_unpredictable): Likewise.
1415 (print_mve_undefined): Likewise.
1416 (print_mve_unpredictable): Likewise.
1417 (print_mve_size): Likewise.
1418 (print_insn_mve): Likewise.
1419
aef6d006
AV		 14202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1421 Michael Collison <michael.collison@arm.com>
1422
1423 * arm-dis.c (enum mve_instructions): Add new instructions.
1424 (enum mve_undefined): Add new reasons.
1425 (insns): Add new instructions.
1426 (is_mve_encoding_conflict):
1427 (print_mve_vld_str_addr): New print function.
1428 (is_mve_undefined): Handle new instructions.
1429 (is_mve_unpredictable): Likewise.
1430 (print_mve_undefined): Likewise.
1431 (print_mve_size): Likewise.
1432 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1433 (print_insn_mve): Handle new operands.
1434
04d54ace
AV		 14352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1436 Michael Collison <michael.collison@arm.com>
1437
1438 * arm-dis.c (enum mve_instructions): Add new instructions.
1439 (enum mve_unpredictable): Add new reasons.
1440 (is_mve_encoding_conflict): Handle new instructions.
1441 (is_mve_unpredictable): Likewise.
1442 (mve_opcodes): Add new instructions.
1443 (print_mve_unpredictable): Handle new reasons.
1444 (print_mve_register_blocks): New print function.
1445 (print_mve_size): Handle new instructions.
1446 (print_insn_mve): Likewise.
1447
9743db03
AV		 14482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1450
1451 * arm-dis.c (enum mve_instructions): Add new instructions.
1452 (enum mve_unpredictable): Add new reasons.
1453 (enum mve_undefined): Likewise.
1454 (is_mve_encoding_conflict): Handle new instructions.
1455 (is_mve_undefined): Likewise.
1456 (is_mve_unpredictable): Likewise.
1457 (coprocessor_opcodes): Move NEON VDUP from here...
1458 (neon_opcodes): ... to here.
1459 (mve_opcodes): Add new instructions.
1460 (print_mve_undefined): Handle new reasons.
1461 (print_mve_unpredictable): Likewise.
1462 (print_mve_size): Handle new instructions.
1463 (print_insn_neon): Handle vdup.
1464 (print_insn_mve): Handle new operands.
1465
143275ea
AV		 14662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1467 Michael Collison <michael.collison@arm.com>
1468
1469 * arm-dis.c (enum mve_instructions): Add new instructions.
1470 (enum mve_unpredictable): Add new values.
1471 (mve_opcodes): Add new instructions.
1472 (vec_condnames): New array with vector conditions.
1473 (mve_predicatenames): New array with predicate suffixes.
1474 (mve_vec_sizename): New array with vector sizes.
1475 (enum vpt_pred_state): New enum with vector predication states.
1476 (struct vpt_block): New struct type for vpt blocks.
1477 (vpt_block_state): Global struct to keep track of state.
1478 (mve_extract_pred_mask): New helper function.
1479 (num_instructions_vpt_block): Likewise.
1480 (mark_outside_vpt_block): Likewise.
1481 (mark_inside_vpt_block): Likewise.
1482 (invert_next_predicate_state): Likewise.
1483 (update_next_predicate_state): Likewise.
1484 (update_vpt_block_state): Likewise.
1485 (is_vpt_instruction): Likewise.
1486 (is_mve_encoding_conflict): Add entries for new instructions.
1487 (is_mve_unpredictable): Likewise.
1488 (print_mve_unpredictable): Handle new cases.
1489 (print_instruction_predicate): Likewise.
1490 (print_mve_size): New function.
1491 (print_vec_condition): New function.
1492 (print_insn_mve): Handle vpt blocks and new print operands.
1493
f08d8ce3
AV		 14942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495
1496 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1497 8, 14 and 15 for Armv8.1-M Mainline.
1498
73cd51e5
AV		 14992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1500 Michael Collison <michael.collison@arm.com>
1501
1502 * arm-dis.c (enum mve_instructions): New enum.
1503 (enum mve_unpredictable): Likewise.
1504 (enum mve_undefined): Likewise.
1505 (struct mopcode32): New struct.
1506 (is_mve_okay_in_it): New function.
1507 (is_mve_architecture): Likewise.
1508 (arm_decode_field): Likewise.
1509 (arm_decode_field_multiple): Likewise.
1510 (is_mve_encoding_conflict): Likewise.
1511 (is_mve_undefined): Likewise.
1512 (is_mve_unpredictable): Likewise.
1513 (print_mve_undefined): Likewise.
1514 (print_mve_unpredictable): Likewise.
1515 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1516 (print_insn_mve): New function.
1517 (print_insn_thumb32): Handle MVE architecture.
1518 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1519
3076e594
NC		 15202019-05-10 Nick Clifton <nickc@redhat.com>
1521
1522 PR 24538
1523 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1524 end of the table prematurely.
1525
387e7624
FS		 15262019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1527
1528 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1529 macros for R6.
1530
0067be51
AM		 15312019-05-11 Alan Modra <amodra@gmail.com>
1532
1533 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1534 when -Mraw is in effect.
1535
42e6288f
MM		 15362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1537
1538 * aarch64-dis-2.c: Regenerate.
1539 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1540 (OP_SVE_BBB): New variant set.
1541 (OP_SVE_DDDD): New variant set.
1542 (OP_SVE_HHH): New variant set.
1543 (OP_SVE_HHHU): New variant set.
1544 (OP_SVE_SSS): New variant set.
1545 (OP_SVE_SSSU): New variant set.
1546 (OP_SVE_SHH): New variant set.
1547 (OP_SVE_SBBU): New variant set.
1548 (OP_SVE_DSS): New variant set.
1549 (OP_SVE_DHHU): New variant set.
1550 (OP_SVE_VMV_HSD_BHS): New variant set.
1551 (OP_SVE_VVU_HSD_BHS): New variant set.
1552 (OP_SVE_VVVU_SD_BH): New variant set.
1553 (OP_SVE_VVVU_BHSD): New variant set.
1554 (OP_SVE_VVV_QHD_DBS): New variant set.
1555 (OP_SVE_VVV_HSD_BHS): New variant set.
1556 (OP_SVE_VVV_HSD_BHS2): New variant set.
1557 (OP_SVE_VVV_BHS_HSD): New variant set.
1558 (OP_SVE_VV_BHS_HSD): New variant set.
1559 (OP_SVE_VVV_SD): New variant set.
1560 (OP_SVE_VVU_BHS_HSD): New variant set.
1561 (OP_SVE_VZVV_SD): New variant set.
1562 (OP_SVE_VZVV_BH): New variant set.
1563 (OP_SVE_VZV_SD): New variant set.
1564 (aarch64_opcode_table): Add sve2 instructions.
1565
28ed815a
MM		 15662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1567
1568 * aarch64-asm-2.c: Regenerated.
1569 * aarch64-dis-2.c: Regenerated.
1570 * aarch64-opc-2.c: Regenerated.
1571 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1572 for SVE_SHLIMM_UNPRED_22.
1573 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1574 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1575 operand.
1576
fd1dc4a0
MM		 15772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1578
1579 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1580 sve_size_tsz_bhs iclass encode.
1581 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1582 sve_size_tsz_bhs iclass decode.
1583
31e36ab3
MM		 15842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1585
1586 * aarch64-asm-2.c: Regenerated.
1587 * aarch64-dis-2.c: Regenerated.
1588 * aarch64-opc-2.c: Regenerated.
1589 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1590 for SVE_Zm4_11_INDEX.
1591 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1592 (fields): Handle SVE_i2h field.
1593 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1594 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1595
1be5f94f
MM		 15962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1597
1598 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1599 sve_shift_tsz_bhsd iclass encode.
1600 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1601 sve_shift_tsz_bhsd iclass decode.
1602
3c17238b
MM		 16032019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1604
1605 * aarch64-asm-2.c: Regenerated.
1606 * aarch64-dis-2.c: Regenerated.
1607 * aarch64-opc-2.c: Regenerated.
1608 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1609 (aarch64_encode_variant_using_iclass): Handle
1610 sve_shift_tsz_hsd iclass encode.
1611 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1612 sve_shift_tsz_hsd iclass decode.
1613 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1614 for SVE_SHRIMM_UNPRED_22.
1615 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1616 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1617 operand.
1618
cd50a87a
MM		 16192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1620
1621 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1622 sve_size_013 iclass encode.
1623 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1624 sve_size_013 iclass decode.
1625
3c705960
MM		 16262019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1627
1628 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1629 sve_size_bh iclass encode.
1630 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1631 sve_size_bh iclass decode.
1632
0a57e14f
MM		 16332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1634
1635 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1636 sve_size_sd2 iclass encode.
1637 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1638 sve_size_sd2 iclass decode.
1639 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1640 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1641
c469c864
MM		 16422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1643
1644 * aarch64-asm-2.c: Regenerated.
1645 * aarch64-dis-2.c: Regenerated.
1646 * aarch64-opc-2.c: Regenerated.
1647 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1648 for SVE_ADDR_ZX.
1649 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1650 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1651
116adc27
MM		 16522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1653
1654 * aarch64-asm-2.c: Regenerated.
1655 * aarch64-dis-2.c: Regenerated.
1656 * aarch64-opc-2.c: Regenerated.
1657 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1658 for SVE_Zm3_11_INDEX.
1659 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1660 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1661 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1662 fields.
1663 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1664
3bd82c86
MM		 16652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1666
1667 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1668 sve_size_hsd2 iclass encode.
1669 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1670 sve_size_hsd2 iclass decode.
1671 * aarch64-opc.c (fields): Handle SVE_size field.
1672 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1673
adccc507
MM		 16742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1675
1676 * aarch64-asm-2.c: Regenerated.
1677 * aarch64-dis-2.c: Regenerated.
1678 * aarch64-opc-2.c: Regenerated.
1679 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1680 for SVE_IMM_ROT3.
1681 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1682 (fields): Handle SVE_rot3 field.
1683 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1684 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1685
5cd99750
MM		 16862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1687
1688 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1689 instructions.
1690
7ce2460a
MM		 16912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1692
1693 * aarch64-tbl.h
1694 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1695 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1696 aarch64_feature_sve2bitperm): New feature sets.
1697 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1698 for feature set addresses.
1699 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1700 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1701
41cee089
FS		 17022019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1703 Faraz Shahbazker <fshahbazker@wavecomp.com>
1704
1705 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1706 argument and set ASE_EVA_R6 appropriately.
1707 (set_default_mips_dis_options): Pass ISA to above.
1708 (parse_mips_dis_option): Likewise.
1709 * mips-opc.c (EVAR6): New macro.
1710 (mips_builtin_opcodes): Add llwpe, scwpe.
1711
b83b4b13
SD		 17122019-05-01 Sudakshina Das <sudi.das@arm.com>
1713
1714 * aarch64-asm-2.c: Regenerated.
1715 * aarch64-dis-2.c: Regenerated.
1716 * aarch64-opc-2.c: Regenerated.
1717 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1718 AARCH64_OPND_TME_UIMM16.
1719 (aarch64_print_operand): Likewise.
1720 * aarch64-tbl.h (QL_IMM_NIL): New.
1721 (TME): New.
1722 (_TME_INSN): New.
1723 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1724
4a90ce95
JD		 17252019-04-29 John Darrington <john@darrington.wattle.id.au>
1726
1727 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1728
a45328b9
AB		 17292019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1730 Faraz Shahbazker <fshahbazker@wavecomp.com>
1731
1732 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1733
d10be0cb
JD		 17342019-04-24 John Darrington <john@darrington.wattle.id.au>
1735
1736 * s12z-opc.h: Add extern "C" bracketing to help
1737 users who wish to use this interface in c++ code.
1738
a679f24e
JD		 17392019-04-24 John Darrington <john@darrington.wattle.id.au>
1740
1741 * s12z-opc.c (bm_decode): Handle bit map operations with the
1742 "reserved0" mode.
1743
32c36c3c
AV		 17442019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1745
1746 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1747 specifier. Add entries for VLDR and VSTR of system registers.
1748 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1749 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1750 of %J and %K format specifier.
1751
efd6b359
AV		 17522019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1753
1754 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1755 Add new entries for VSCCLRM instruction.
1756 (print_insn_coprocessor): Handle new %C format control code.
1757
6b0dd094
AV		 17582019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1759
1760 * arm-dis.c (enum isa): New enum.
1761 (struct sopcode32): New structure.
1762 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1763 set isa field of all current entries to ANY.
1764 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1765 Only match an entry if its isa field allows the current mode.
1766
4b5a202f
AV		 17672019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1768
1769 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1770 CLRM.
1771 (print_insn_thumb32): Add logic to print %n CLRM register list.
1772
60f993ce
AV		 17732019-04-15 Sudakshina Das <sudi.das@arm.com>
1774
1775 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1776 and %Q patterns.
1777
f6b2b12d
AV		 17782019-04-15 Sudakshina Das <sudi.das@arm.com>
1779
1780 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1781 (print_insn_thumb32): Edit the switch case for %Z.
1782
1889da70
AV		 17832019-04-15 Sudakshina Das <sudi.das@arm.com>
1784
1785 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1786
65d1bc05
AV		 17872019-04-15 Sudakshina Das <sudi.das@arm.com>
1788
1789 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1790
1caf72a5
AV		 17912019-04-15 Sudakshina Das <sudi.das@arm.com>
1792
1793 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1794
f1c7f421
AV		 17952019-04-15 Sudakshina Das <sudi.das@arm.com>
1796
1797 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1798 Arm register with r13 and r15 unpredictable.
1799 (thumb32_opcodes): New instructions for bfx and bflx.
1800
4389b29a
AV		 18012019-04-15 Sudakshina Das <sudi.das@arm.com>
1802
1803 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1804
e5d6e09e
AV		 18052019-04-15 Sudakshina Das <sudi.das@arm.com>
1806
1807 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1808
e12437dc
AV		 18092019-04-15 Sudakshina Das <sudi.das@arm.com>
1810
1811 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1812
031254f2
AV		 18132019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1814
1815 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1816
e5a557ac
JD		 18172019-04-12 John Darrington <john@darrington.wattle.id.au>
1818
1819 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1820 "optr". ("operator" is a reserved word in c++).
1821
bd7ceb8d
SD		 18222019-04-11 Sudakshina Das <sudi.das@arm.com>
1823
1824 * aarch64-opc.c (aarch64_print_operand): Add case for
1825 AARCH64_OPND_Rt_SP.
1826 (verify_constraints): Likewise.
1827 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1828 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1829 to accept Rt|SP as first operand.
1830 (AARCH64_OPERANDS): Add new Rt_SP.
1831 * aarch64-asm-2.c: Regenerated.
1832 * aarch64-dis-2.c: Regenerated.
1833 * aarch64-opc-2.c: Regenerated.
1834
e54010f1
SD		 18352019-04-11 Sudakshina Das <sudi.das@arm.com>
1836
1837 * aarch64-asm-2.c: Regenerated.
1838 * aarch64-dis-2.c: Likewise.
1839 * aarch64-opc-2.c: Likewise.
1840 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1841
7e96e219
RS		 18422019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1843
1844 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1845
6f2791d5
L		 18462019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1847
1848 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1849 * i386-init.h: Regenerated.
1850
e392bad3
AM		 18512019-04-07 Alan Modra <amodra@gmail.com>
1852
1853 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1854 op_separator to control printing of spaces, comma and parens
1855 rather than need_comma, need_paren and spaces vars.
1856
dffaa15c
AM		 18572019-04-07 Alan Modra <amodra@gmail.com>
1858
1859 PR 24421
1860 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1861 (print_insn_neon, print_insn_arm): Likewise.
1862
d6aab7a1
XG		 18632019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1864
1865 * i386-dis-evex.h (evex_table): Updated to support BF16
1866 instructions.
1867 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1868 and EVEX_W_0F3872_P_3.
1869 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1870 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1871 * i386-opc.h (enum): Add CpuAVX512_BF16.
1872 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1873 * i386-opc.tbl: Add AVX512 BF16 instructions.
1874 * i386-init.h: Regenerated.
1875 * i386-tbl.h: Likewise.
1876
66e85460
AM		 18772019-04-05 Alan Modra <amodra@gmail.com>
1878
1879 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1880 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1881 to favour printing of "-" branch hint when using the "y" bit.
1882 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1883
c2b1c275
AM		 18842019-04-05 Alan Modra <amodra@gmail.com>
1885
1886 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1887 opcode until first operand is output.
1888
aae9718e
PB		 18892019-04-04 Peter Bergner <bergner@linux.ibm.com>
1890
1891 PR gas/24349
1892 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1893 (valid_bo_post_v2): Add support for 'at' branch hints.
1894 (insert_bo): Only error on branch on ctr.
1895 (get_bo_hint_mask): New function.
1896 (insert_boe): Add new 'branch_taken' formal argument. Add support
1897 for inserting 'at' branch hints.
1898 (extract_boe): Add new 'branch_taken' formal argument. Add support
1899 for extracting 'at' branch hints.
1900 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1901 (BOE): Delete operand.
1902 (BOM, BOP): New operands.
1903 (RM): Update value.
1904 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1905 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1906 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1907 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1908 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1909 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1910 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1911 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1912 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1913 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1914 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1915 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1916 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1917 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1918 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1919 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1920 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1921 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1922 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1923 bttarl+>: New extended mnemonics.
1924
96a86c01
AM		 19252019-03-28 Alan Modra <amodra@gmail.com>
1926
1927 PR 24390
1928 * ppc-opc.c (BTF): Define.
1929 (powerpc_opcodes): Use for mtfsb*.
1930 * ppc-dis.c (print_insn_powerpc): Print fields with both
1931 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1932
796d6298
TC		 19332019-03-25 Tamar Christina <tamar.christina@arm.com>
1934
1935 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1936 (mapping_symbol_for_insn): Implement new algorithm.
1937 (print_insn): Remove duplicate code.
1938
60df3720
TC		 19392019-03-25 Tamar Christina <tamar.christina@arm.com>
1940
1941 * aarch64-dis.c (print_insn_aarch64):
1942 Implement override.
1943
51457761
TC		 19442019-03-25 Tamar Christina <tamar.christina@arm.com>
1945
1946 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1947 order.
1948
53b2f36b
TC		 19492019-03-25 Tamar Christina <tamar.christina@arm.com>
1950
1951 * aarch64-dis.c (last_stop_offset): New.
1952 (print_insn_aarch64): Use stop_offset.
1953
89199bb5
L		 19542019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1955
1956 PR gas/24359
1957 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1958 CPU_ANY_AVX2_FLAGS.
1959 * i386-init.h: Regenerated.
1960
97ed31ae
L		 19612019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1962
1963 PR gas/24348
1964 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1965 vmovdqu16, vmovdqu32 and vmovdqu64.
1966 * i386-tbl.h: Regenerated.
1967
0919bfe9
AK		 19682019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1969
1970 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1971 from vstrszb, vstrszh, and vstrszf.
1972
19732019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1974
1975 * s390-opc.txt: Add instruction descriptions.
1976
21820ebe
JW		 19772019-02-08 Jim Wilson <jimw@sifive.com>
1978
1979 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1980 <bne>: Likewise.
1981
f7dd2fb2
TC		 19822019-02-07 Tamar Christina <tamar.christina@arm.com>
1983
1984 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1985
6456d318
TC		 19862019-02-07 Tamar Christina <tamar.christina@arm.com>
1987
1988 PR binutils/23212
1989 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1990 * aarch64-opc.c (verify_elem_sd): New.
1991 (fields): Add FLD_sz entr.
1992 * aarch64-tbl.h (_SIMD_INSN): New.
1993 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1994 fmulx scalar and vector by element isns.
1995
4a83b610
NC		 19962019-02-07 Nick Clifton <nickc@redhat.com>
1997
1998 * po/sv.po: Updated Swedish translation.
1999
fc60b8c8
AK		 20002019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2001
2002 * s390-mkopc.c (main): Accept arch13 as cpu string.
2003 * s390-opc.c: Add new instruction formats and instruction opcode
2004 masks.
2005 * s390-opc.txt: Add new arch13 instructions.
2006
e10620d3
TC		 20072019-01-25 Sudakshina Das <sudi.das@arm.com>
2008
2009 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2010 (aarch64_opcode): Change encoding for stg, stzg
2011 st2g and st2zg.
2012 * aarch64-asm-2.c: Regenerated.
2013 * aarch64-dis-2.c: Regenerated.
2014 * aarch64-opc-2.c: Regenerated.
2015
20a4ca55
SD		 20162019-01-25 Sudakshina Das <sudi.das@arm.com>
2017
2018 * aarch64-asm-2.c: Regenerated.
2019 * aarch64-dis-2.c: Likewise.
2020 * aarch64-opc-2.c: Likewise.
2021 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2022
550fd7bf
SD		 20232019-01-25 Sudakshina Das <sudi.das@arm.com>
2024 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2025
2026 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2027 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2028 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2029 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2030 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2031 case for ldstgv_indexed.
2032 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2033 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2034 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2035 * aarch64-asm-2.c: Regenerated.
2036 * aarch64-dis-2.c: Regenerated.
2037 * aarch64-opc-2.c: Regenerated.
2038
d9938630
NC		 20392019-01-23 Nick Clifton <nickc@redhat.com>
2040
2041 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2042
375cd423
NC		 20432019-01-21 Nick Clifton <nickc@redhat.com>
2044
2045 * po/de.po: Updated German translation.
2046 * po/uk.po: Updated Ukranian translation.
2047
57299f48
CX		 20482019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2049 * mips-dis.c (mips_arch_choices): Fix typo in
2050 gs464, gs464e and gs264e descriptors.
2051
f48dfe41
NC		 20522019-01-19 Nick Clifton <nickc@redhat.com>
2053
2054 * configure: Regenerate.
2055 * po/opcodes.pot: Regenerate.
2056
f974f26c
NC		 20572018-06-24 Nick Clifton <nickc@redhat.com>
2058
2059 2.32 branch created.
2060
39f286cd
JD		 20612019-01-09 John Darrington <john@darrington.wattle.id.au>
2062
448b8ca8
JD		 2063 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2064 if it is null.
2065 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2066 zero.
2067
3107326d
AP		 20682019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2069
2070 * configure: Regenerate.
2071
7e9ca91e
AM		 20722019-01-07 Alan Modra <amodra@gmail.com>
2073
2074 * configure: Regenerate.
2075 * po/POTFILES.in: Regenerate.
2076
ef1ad42b
JD		 20772019-01-03 John Darrington <john@darrington.wattle.id.au>
2078
2079 * s12z-opc.c: New file.
2080 * s12z-opc.h: New file.
2081 * s12z-dis.c: Removed all code not directly related to display
2082 of instructions. Used the interface provided by the new files
2083 instead.
2084 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2085 * Makefile.in: Regenerate.
ef1ad42b 2086 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2087 * configure: Regenerate.
ef1ad42b 2088
82704155
AM		 20892019-01-01 Alan Modra <amodra@gmail.com>
2090
2091 Update year range in copyright notice of all files.
2092
d5c04e1b 2093For older changes see ChangeLog-2018
3499769a 2094\f
d5c04e1b 2095Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2096
2097Copying and distribution of this file, with or without modification,
2098are permitted in any medium without royalty provided the copyright
2099notice and this notice are preserved.
2100
2101Local Variables:
2102mode: change-log
2103left-margin: 8
2104fill-column: 74
2105version-control: never
2106End:
GDB Binutils - Deliverables
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