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x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9819647a
JB		 12018-11-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
4 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
5 cases up one level in the hierarchy.
6
58a211d2
JB		 72018-11-06 Jan Beulich <jbeulich@suse.com>
8
9 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
10 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
11 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
12 into MOD_VEX_0F93_P_3_LEN_0.
13 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
14 operand cases up one level in the hierarchy.
15
b50c9f31
JB		 162018-11-06 Jan Beulich <jbeulich@suse.com>
17
18 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
19 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
20 EVEX_W_0F3A22_P_2): Delete.
21 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
22 entries up one level in the hierarchy.
23 (OP_E_memory): Handle dq_mode when determining Disp8 shift
24 value.
25 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
26 entries up one level in the hierarchy.
27 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
28 VexWIG for AVX flavors.
29 * i386-tbl.h: Re-generate.
30
931d03b7
JB		 312018-11-06 Jan Beulich <jbeulich@suse.com>
32
33 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
34 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
35 vcvtusi2ss, kmovd): Drop VexW=1.
36 * i386-tbl.h: Re-generate.
37
fd71a375
JB		 382018-11-06 Jan Beulich <jbeulich@suse.com>
39
40 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
41 EVex512, EVexLIG, EVexDYN): New.
42 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
43 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
44 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
45 of EVex=4 (aka EVexLIG).
46 * i386-tbl.h: Re-generate.
47
563c7eef
JB		 482018-11-06 Jan Beulich <jbeulich@suse.com>
49
50 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
51 (vpmaxub): Re-order attributes on AVX512BW flavor.
52 * i386-tbl.h: Re-generate.
53
0aaca1d9
JB		 542018-11-06 Jan Beulich <jbeulich@suse.com>
55
56 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
57 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
58 Vex=1 on AVX / AVX2 flavors.
59 (vpmaxub): Re-order attributes on AVX512BW flavor.
60 * i386-tbl.h: Re-generate.
61
bbae6b11
JB		 622018-11-06 Jan Beulich <jbeulich@suse.com>
63
64 * i386-opc.tbl (VexW0, VexW1): New.
65 (vphadd*, vphsub*): Use VexW0 on XOP variants.
66 * i386-tbl.h: Re-generate.
67
192c2bfb
JD		 682018-10-22 John Darrington <john@darrington.wattle.id.au>
69
70 * s12z-dis.c (decode_possible_symbol): Add fallback case.
71 (rel_15_7): Likewise.
72
0b347048
TC		 732018-10-19 Tamar Christina <tamar.christina@arm.com>
74
75 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
76 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
77 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
78
66e6f0b7
MM		 792018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
80
81 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
82 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
83
673fe0f0
JB		 842018-10-10 Jan Beulich <jbeulich@suse.com>
85
86 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
87 Size64. Add Size.
88 * i386-opc.h (Size16, Size32, Size64): Delete.
89 (Size): New.
90 (SIZE16, SIZE32, SIZE64): Define.
91 (struct i386_opcode_modifier): Drop size16, size32, and size64.
92 Add size.
93 * i386-opc.tbl (Size16, Size32, Size64): Define.
94 * i386-tbl.h: Re-generate.
95
104fefee
SD		 962018-10-09 Sudakshina Das <sudi.das@arm.com>
97
98 * aarch64-opc.c (operand_general_constraint_met_p): Add
99 SSBS in the check for one-bit immediate.
100 (aarch64_sys_regs): New entry for SSBS.
101 (aarch64_sys_reg_supported_p): New check for above.
102 (aarch64_pstatefields): New entry for SSBS.
103 (aarch64_pstatefield_supported_p): New check for above.
104
a97330e7
SD		 1052018-10-09 Sudakshina Das <sudi.das@arm.com>
106
107 * aarch64-opc.c (aarch64_sys_regs): New entries for
108 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
109 (aarch64_sys_reg_supported_p): New checks for above.
110
ff605452
SD		 1112018-10-09 Sudakshina Das <sudi.das@arm.com>
112
113 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
114 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
115 with the hint immediate.
116 * aarch64-opc.c (aarch64_hint_options): New entries for
117 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
118 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
119 while checking for HINT_OPD_F_NOPRINT flag.
120 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
121 extract value.
122 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
123 (aarch64_opcode_table): Add entry for BTI.
124 (AARCH64_OPERANDS): Add new description for BTI targets.
125 * aarch64-asm-2.c: Regenerate.
126 * aarch64-dis-2.c: Regenerate.
127 * aarch64-opc-2.c: Regenerate.
128
af4bcb4c
SD		 1292018-10-09 Sudakshina Das <sudi.das@arm.com>
130
131 * aarch64-opc.c (aarch64_sys_regs): New entries for
132 rndr and rndrrs.
133 (aarch64_sys_reg_supported_p): New check for above.
134
3fd229a4
SD		 1352018-10-09 Sudakshina Das <sudi.das@arm.com>
136
137 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
138 (aarch64_sys_ins_reg_supported_p): New check for above.
139
2ac435d4
SD		 1402018-10-09 Sudakshina Das <sudi.das@arm.com>
141
142 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
143 AARCH64_OPND_SYSREG_SR.
144 * aarch64-opc.c (aarch64_print_operand): Likewise.
145 (aarch64_sys_regs_sr): Define table.
146 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
147 AARCH64_FEATURE_PREDRES.
148 * aarch64-tbl.h (aarch64_feature_predres): New.
149 (PREDRES, PREDRES_INSN): New.
150 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
151 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
152 * aarch64-asm-2.c: Regenerate.
153 * aarch64-dis-2.c: Regenerate.
154 * aarch64-opc-2.c: Regenerate.
155
68dfbb92
SD		 1562018-10-09 Sudakshina Das <sudi.das@arm.com>
157
158 * aarch64-tbl.h (aarch64_feature_sb): New.
159 (SB, SB_INSN): New.
160 (aarch64_opcode_table): Add entry for sb.
161 * aarch64-asm-2.c: Regenerate.
162 * aarch64-dis-2.c: Regenerate.
163 * aarch64-opc-2.c: Regenerate.
164
13c60ad7
SD		 1652018-10-09 Sudakshina Das <sudi.das@arm.com>
166
167 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
168 (aarch64_feature_frintts): New.
169 (FLAGMANIP, FRINTTS): New.
170 (aarch64_opcode_table): Add entries for xaflag, axflag
171 and frint[32,64][x,z] instructions.
172 * aarch64-asm-2.c: Regenerate.
173 * aarch64-dis-2.c: Regenerate.
174 * aarch64-opc-2.c: Regenerate.
175
70d56181
SD		 1762018-10-09 Sudakshina Das <sudi.das@arm.com>
177
178 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
179 (ARMV8_5, V8_5_INSN): New.
180
780f601c
TC		 1812018-10-08 Tamar Christina <tamar.christina@arm.com>
182
183 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
184
a4e78aa5
L		 1852018-10-05 H.J. Lu <hongjiu.lu@intel.com>
186
187 * i386-dis.c (rm_table): Add enclv.
188 * i386-opc.tbl: Add enclv.
189 * i386-tbl.h: Regenerated.
190
7fadb25d
SD		 1912018-10-05 Sudakshina Das <sudi.das@arm.com>
192
193 * arm-dis.c (arm_opcodes): Add sb.
194 (thumb32_opcodes): Likewise.
195
07f5f4c6
RH		 1962018-10-05 Richard Henderson <rth@twiddle.net>
197 Stafford Horne <shorne@gmail.com>
198
199 * or1k-desc.c: Regenerate.
200 * or1k-desc.h: Regenerate.
201 * or1k-opc.c: Regenerate.
202 * or1k-opc.h: Regenerate.
203 * or1k-opinst.c: Regenerate.
204
c8e98e36
SH		 2052018-10-05 Richard Henderson <rth@twiddle.net>
206
207 * or1k-asm.c: Regenerated.
208 * or1k-desc.c: Regenerated.
209 * or1k-desc.h: Regenerated.
210 * or1k-dis.c: Regenerated.
211 * or1k-ibld.c: Regenerated.
212 * or1k-opc.c: Regenerated.
213 * or1k-opc.h: Regenerated.
214 * or1k-opinst.c: Regenerated.
215
1c4f3780
RH		 2162018-10-05 Richard Henderson <rth@twiddle.net>
217
218 * or1k-asm.c: Regenerate.
219
bde90be2
TC		 2202018-10-03 Tamar Christina <tamar.christina@arm.com>
221
222 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
223 * aarch64-dis.c (print_operands): Refactor to take notes.
224 (print_verifier_notes): New.
225 (print_aarch64_insn): Apply constraint verifier.
226 (print_insn_aarch64_word): Update call to print_aarch64_insn.
227 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
228
a68f4cd2
TC		 2292018-10-03 Tamar Christina <tamar.christina@arm.com>
230
231 * aarch64-opc.c (init_insn_block): New.
232 (verify_constraints, aarch64_is_destructive_by_operands): New.
233 * aarch64-opc.h (verify_constraints): New.
234
755b748f
TC		 2352018-10-03 Tamar Christina <tamar.christina@arm.com>
236
237 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
238 * aarch64-opc.c (verify_ldpsw): Update arguments.
239
1d482394
TC		 2402018-10-03 Tamar Christina <tamar.christina@arm.com>
241
242 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
243 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
244
7e84b55d
TC		 2452018-10-03 Tamar Christina <tamar.christina@arm.com>
246
247 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
248 * aarch64-dis.c (insn_sequence): New.
249
eae424ae
TC		 2502018-10-03 Tamar Christina <tamar.christina@arm.com>
251
252 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
253 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
254 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
255 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
256 constraints.
257 (_SVE_INSNC): New.
258 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
259 constraints.
260 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
261 F_SCAN flags.
262 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
263 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
264 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
265 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
266 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
267 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
268 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
269
64a336ac
PD		 2702018-10-02 Palmer Dabbelt <palmer@sifive.com>
271
272 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
273
6031ac35
SL		 2742018-09-23 Sandra Loosemore <sandra@codesourcery.com>
275
276 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
277 are used when extracting signed fields and converting them to
278 potentially 64-bit types.
279
f24ff6e9
SM		 2802018-09-21 Simon Marchi <simon.marchi@ericsson.com>
281
282 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
283 * Makefile.in: Re-generate.
284 * aclocal.m4: Re-generate.
285 * configure: Re-generate.
286 * configure.ac: Remove check for -Wno-missing-field-initializers.
287 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
288 (csky_v2_opcodes): Likewise.
289
53b6d6f5
MR		 2902018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
291
292 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
293
fbaf61ad
NC		 2942018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
295
296 * nds32-asm.c (operand_fields): Remove the unused fields.
297 (nds32_opcodes): Remove the unused instructions.
298 * nds32-dis.c (nds32_ex9_info): Removed.
299 (nds32_parse_opcode): Updated.
300 (print_insn_nds32): Likewise.
301 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
302 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
303 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
304 build_opcode_hash_table): New functions.
305 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
306 nds32_opcode_table): New.
307 (hw_ktabs): Declare it to a pointer rather than an array.
308 (build_hash_table): Removed.
309 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
310 SYN_ROPT and upadte HW_GPR and HW_INT.
311 * nds32-dis.c (keywords): Remove const.
312 (match_field): New function.
313 (nds32_parse_opcode): Updated.
314 * disassemble.c (disassemble_init_for_target):
315 Add disassemble_init_nds32.
316 * nds32-dis.c (eum map_type): New.
317 (nds32_private_data): Likewise.
318 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
319 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
320 (print_insn_nds32): Updated.
321 * nds32-asm.c (parse_aext_reg): Add new parameter.
322 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
323 are allowed to use.
324 All callers changed.
325 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
326 (operand_fields): Add new fields.
327 (nds32_opcodes): Add new instructions.
328 (keyword_aridxi_mx): New keyword.
329 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
330 and NASM_ATTR_ZOL.
331 (ALU2_1, ALU2_2, ALU2_3): New macros.
332 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
333
4e2b1898
JW		 3342018-09-17 Kito Cheng <kito@andestech.com>
335
336 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
337
04e2a182
L		 3382018-09-17 H.J. Lu <hongjiu.lu@intel.com>
339
340 PR gas/23670
341 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
342 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
343 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
344 (EVEX_LEN_0F7E_P_1): Likewise.
345 (EVEX_LEN_0F7E_P_2): Likewise.
346 (EVEX_LEN_0FD6_P_2): Likewise.
347 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
348 (EVEX_LEN_TABLE): Likewise.
349 (EVEX_LEN_0F6E_P_2): New enum.
350 (EVEX_LEN_0F7E_P_1): Likewise.
351 (EVEX_LEN_0F7E_P_2): Likewise.
352 (EVEX_LEN_0FD6_P_2): Likewise.
353 (evex_len_table): New.
354 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
355 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
356 * i386-tbl.h: Regenerated.
357
d5f787c2
L		 3582018-09-17 H.J. Lu <hongjiu.lu@intel.com>
359
360 PR gas/23665
361 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
362 VEX_LEN_0F7E_P_2 entries.
363 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
364 * i386-tbl.h: Regenerated.
365
ec6f095a
L		 3662018-09-17 H.J. Lu <hongjiu.lu@intel.com>
367
368 * i386-dis.c (VZERO_Fixup): Removed.
369 (VZERO): Likewise.
370 (VEX_LEN_0F10_P_1): Likewise.
371 (VEX_LEN_0F10_P_3): Likewise.
372 (VEX_LEN_0F11_P_1): Likewise.
373 (VEX_LEN_0F11_P_3): Likewise.
374 (VEX_LEN_0F2E_P_0): Likewise.
375 (VEX_LEN_0F2E_P_2): Likewise.
376 (VEX_LEN_0F2F_P_0): Likewise.
377 (VEX_LEN_0F2F_P_2): Likewise.
378 (VEX_LEN_0F51_P_1): Likewise.
379 (VEX_LEN_0F51_P_3): Likewise.
380 (VEX_LEN_0F52_P_1): Likewise.
381 (VEX_LEN_0F53_P_1): Likewise.
382 (VEX_LEN_0F58_P_1): Likewise.
383 (VEX_LEN_0F58_P_3): Likewise.
384 (VEX_LEN_0F59_P_1): Likewise.
385 (VEX_LEN_0F59_P_3): Likewise.
386 (VEX_LEN_0F5A_P_1): Likewise.
387 (VEX_LEN_0F5A_P_3): Likewise.
388 (VEX_LEN_0F5C_P_1): Likewise.
389 (VEX_LEN_0F5C_P_3): Likewise.
390 (VEX_LEN_0F5D_P_1): Likewise.
391 (VEX_LEN_0F5D_P_3): Likewise.
392 (VEX_LEN_0F5E_P_1): Likewise.
393 (VEX_LEN_0F5E_P_3): Likewise.
394 (VEX_LEN_0F5F_P_1): Likewise.
395 (VEX_LEN_0F5F_P_3): Likewise.
396 (VEX_LEN_0FC2_P_1): Likewise.
397 (VEX_LEN_0FC2_P_3): Likewise.
398 (VEX_LEN_0F3A0A_P_2): Likewise.
399 (VEX_LEN_0F3A0B_P_2): Likewise.
400 (VEX_W_0F10_P_0): Likewise.
401 (VEX_W_0F10_P_1): Likewise.
402 (VEX_W_0F10_P_2): Likewise.
403 (VEX_W_0F10_P_3): Likewise.
404 (VEX_W_0F11_P_0): Likewise.
405 (VEX_W_0F11_P_1): Likewise.
406 (VEX_W_0F11_P_2): Likewise.
407 (VEX_W_0F11_P_3): Likewise.
408 (VEX_W_0F12_P_0_M_0): Likewise.
409 (VEX_W_0F12_P_0_M_1): Likewise.
410 (VEX_W_0F12_P_1): Likewise.
411 (VEX_W_0F12_P_2): Likewise.
412 (VEX_W_0F12_P_3): Likewise.
413 (VEX_W_0F13_M_0): Likewise.
414 (VEX_W_0F14): Likewise.
415 (VEX_W_0F15): Likewise.
416 (VEX_W_0F16_P_0_M_0): Likewise.
417 (VEX_W_0F16_P_0_M_1): Likewise.
418 (VEX_W_0F16_P_1): Likewise.
419 (VEX_W_0F16_P_2): Likewise.
420 (VEX_W_0F17_M_0): Likewise.
421 (VEX_W_0F28): Likewise.
422 (VEX_W_0F29): Likewise.
423 (VEX_W_0F2B_M_0): Likewise.
424 (VEX_W_0F2E_P_0): Likewise.
425 (VEX_W_0F2E_P_2): Likewise.
426 (VEX_W_0F2F_P_0): Likewise.
427 (VEX_W_0F2F_P_2): Likewise.
428 (VEX_W_0F50_M_0): Likewise.
429 (VEX_W_0F51_P_0): Likewise.
430 (VEX_W_0F51_P_1): Likewise.
431 (VEX_W_0F51_P_2): Likewise.
432 (VEX_W_0F51_P_3): Likewise.
433 (VEX_W_0F52_P_0): Likewise.
434 (VEX_W_0F52_P_1): Likewise.
435 (VEX_W_0F53_P_0): Likewise.
436 (VEX_W_0F53_P_1): Likewise.
437 (VEX_W_0F58_P_0): Likewise.
438 (VEX_W_0F58_P_1): Likewise.
439 (VEX_W_0F58_P_2): Likewise.
440 (VEX_W_0F58_P_3): Likewise.
441 (VEX_W_0F59_P_0): Likewise.
442 (VEX_W_0F59_P_1): Likewise.
443 (VEX_W_0F59_P_2): Likewise.
444 (VEX_W_0F59_P_3): Likewise.
445 (VEX_W_0F5A_P_0): Likewise.
446 (VEX_W_0F5A_P_1): Likewise.
447 (VEX_W_0F5A_P_3): Likewise.
448 (VEX_W_0F5B_P_0): Likewise.
449 (VEX_W_0F5B_P_1): Likewise.
450 (VEX_W_0F5B_P_2): Likewise.
451 (VEX_W_0F5C_P_0): Likewise.
452 (VEX_W_0F5C_P_1): Likewise.
453 (VEX_W_0F5C_P_2): Likewise.
454 (VEX_W_0F5C_P_3): Likewise.
455 (VEX_W_0F5D_P_0): Likewise.
456 (VEX_W_0F5D_P_1): Likewise.
457 (VEX_W_0F5D_P_2): Likewise.
458 (VEX_W_0F5D_P_3): Likewise.
459 (VEX_W_0F5E_P_0): Likewise.
460 (VEX_W_0F5E_P_1): Likewise.
461 (VEX_W_0F5E_P_2): Likewise.
462 (VEX_W_0F5E_P_3): Likewise.
463 (VEX_W_0F5F_P_0): Likewise.
464 (VEX_W_0F5F_P_1): Likewise.
465 (VEX_W_0F5F_P_2): Likewise.
466 (VEX_W_0F5F_P_3): Likewise.
467 (VEX_W_0F60_P_2): Likewise.
468 (VEX_W_0F61_P_2): Likewise.
469 (VEX_W_0F62_P_2): Likewise.
470 (VEX_W_0F63_P_2): Likewise.
471 (VEX_W_0F64_P_2): Likewise.
472 (VEX_W_0F65_P_2): Likewise.
473 (VEX_W_0F66_P_2): Likewise.
474 (VEX_W_0F67_P_2): Likewise.
475 (VEX_W_0F68_P_2): Likewise.
476 (VEX_W_0F69_P_2): Likewise.
477 (VEX_W_0F6A_P_2): Likewise.
478 (VEX_W_0F6B_P_2): Likewise.
479 (VEX_W_0F6C_P_2): Likewise.
480 (VEX_W_0F6D_P_2): Likewise.
481 (VEX_W_0F6F_P_1): Likewise.
482 (VEX_W_0F6F_P_2): Likewise.
483 (VEX_W_0F70_P_1): Likewise.
484 (VEX_W_0F70_P_2): Likewise.
485 (VEX_W_0F70_P_3): Likewise.
486 (VEX_W_0F71_R_2_P_2): Likewise.
487 (VEX_W_0F71_R_4_P_2): Likewise.
488 (VEX_W_0F71_R_6_P_2): Likewise.
489 (VEX_W_0F72_R_2_P_2): Likewise.
490 (VEX_W_0F72_R_4_P_2): Likewise.
491 (VEX_W_0F72_R_6_P_2): Likewise.
492 (VEX_W_0F73_R_2_P_2): Likewise.
493 (VEX_W_0F73_R_3_P_2): Likewise.
494 (VEX_W_0F73_R_6_P_2): Likewise.
495 (VEX_W_0F73_R_7_P_2): Likewise.
496 (VEX_W_0F74_P_2): Likewise.
497 (VEX_W_0F75_P_2): Likewise.
498 (VEX_W_0F76_P_2): Likewise.
499 (VEX_W_0F77_P_0): Likewise.
500 (VEX_W_0F7C_P_2): Likewise.
501 (VEX_W_0F7C_P_3): Likewise.
502 (VEX_W_0F7D_P_2): Likewise.
503 (VEX_W_0F7D_P_3): Likewise.
504 (VEX_W_0F7E_P_1): Likewise.
505 (VEX_W_0F7F_P_1): Likewise.
506 (VEX_W_0F7F_P_2): Likewise.
507 (VEX_W_0FAE_R_2_M_0): Likewise.
508 (VEX_W_0FAE_R_3_M_0): Likewise.
509 (VEX_W_0FC2_P_0): Likewise.
510 (VEX_W_0FC2_P_1): Likewise.
511 (VEX_W_0FC2_P_2): Likewise.
512 (VEX_W_0FC2_P_3): Likewise.
513 (VEX_W_0FD0_P_2): Likewise.
514 (VEX_W_0FD0_P_3): Likewise.
515 (VEX_W_0FD1_P_2): Likewise.
516 (VEX_W_0FD2_P_2): Likewise.
517 (VEX_W_0FD3_P_2): Likewise.
518 (VEX_W_0FD4_P_2): Likewise.
519 (VEX_W_0FD5_P_2): Likewise.
520 (VEX_W_0FD6_P_2): Likewise.
521 (VEX_W_0FD7_P_2_M_1): Likewise.
522 (VEX_W_0FD8_P_2): Likewise.
523 (VEX_W_0FD9_P_2): Likewise.
524 (VEX_W_0FDA_P_2): Likewise.
525 (VEX_W_0FDB_P_2): Likewise.
526 (VEX_W_0FDC_P_2): Likewise.
527 (VEX_W_0FDD_P_2): Likewise.
528 (VEX_W_0FDE_P_2): Likewise.
529 (VEX_W_0FDF_P_2): Likewise.
530 (VEX_W_0FE0_P_2): Likewise.
531 (VEX_W_0FE1_P_2): Likewise.
532 (VEX_W_0FE2_P_2): Likewise.
533 (VEX_W_0FE3_P_2): Likewise.
534 (VEX_W_0FE4_P_2): Likewise.
535 (VEX_W_0FE5_P_2): Likewise.
536 (VEX_W_0FE6_P_1): Likewise.
537 (VEX_W_0FE6_P_2): Likewise.
538 (VEX_W_0FE6_P_3): Likewise.
539 (VEX_W_0FE7_P_2_M_0): Likewise.
540 (VEX_W_0FE8_P_2): Likewise.
541 (VEX_W_0FE9_P_2): Likewise.
542 (VEX_W_0FEA_P_2): Likewise.
543 (VEX_W_0FEB_P_2): Likewise.
544 (VEX_W_0FEC_P_2): Likewise.
545 (VEX_W_0FED_P_2): Likewise.
546 (VEX_W_0FEE_P_2): Likewise.
547 (VEX_W_0FEF_P_2): Likewise.
548 (VEX_W_0FF0_P_3_M_0): Likewise.
549 (VEX_W_0FF1_P_2): Likewise.
550 (VEX_W_0FF2_P_2): Likewise.
551 (VEX_W_0FF3_P_2): Likewise.
552 (VEX_W_0FF4_P_2): Likewise.
553 (VEX_W_0FF5_P_2): Likewise.
554 (VEX_W_0FF6_P_2): Likewise.
555 (VEX_W_0FF7_P_2): Likewise.
556 (VEX_W_0FF8_P_2): Likewise.
557 (VEX_W_0FF9_P_2): Likewise.
558 (VEX_W_0FFA_P_2): Likewise.
559 (VEX_W_0FFB_P_2): Likewise.
560 (VEX_W_0FFC_P_2): Likewise.
561 (VEX_W_0FFD_P_2): Likewise.
562 (VEX_W_0FFE_P_2): Likewise.
563 (VEX_W_0F3800_P_2): Likewise.
564 (VEX_W_0F3801_P_2): Likewise.
565 (VEX_W_0F3802_P_2): Likewise.
566 (VEX_W_0F3803_P_2): Likewise.
567 (VEX_W_0F3804_P_2): Likewise.
568 (VEX_W_0F3805_P_2): Likewise.
569 (VEX_W_0F3806_P_2): Likewise.
570 (VEX_W_0F3807_P_2): Likewise.
571 (VEX_W_0F3808_P_2): Likewise.
572 (VEX_W_0F3809_P_2): Likewise.
573 (VEX_W_0F380A_P_2): Likewise.
574 (VEX_W_0F380B_P_2): Likewise.
575 (VEX_W_0F3817_P_2): Likewise.
576 (VEX_W_0F381C_P_2): Likewise.
577 (VEX_W_0F381D_P_2): Likewise.
578 (VEX_W_0F381E_P_2): Likewise.
579 (VEX_W_0F3820_P_2): Likewise.
580 (VEX_W_0F3821_P_2): Likewise.
581 (VEX_W_0F3822_P_2): Likewise.
582 (VEX_W_0F3823_P_2): Likewise.
583 (VEX_W_0F3824_P_2): Likewise.
584 (VEX_W_0F3825_P_2): Likewise.
585 (VEX_W_0F3828_P_2): Likewise.
586 (VEX_W_0F3829_P_2): Likewise.
587 (VEX_W_0F382A_P_2_M_0): Likewise.
588 (VEX_W_0F382B_P_2): Likewise.
589 (VEX_W_0F3830_P_2): Likewise.
590 (VEX_W_0F3831_P_2): Likewise.
591 (VEX_W_0F3832_P_2): Likewise.
592 (VEX_W_0F3833_P_2): Likewise.
593 (VEX_W_0F3834_P_2): Likewise.
594 (VEX_W_0F3835_P_2): Likewise.
595 (VEX_W_0F3837_P_2): Likewise.
596 (VEX_W_0F3838_P_2): Likewise.
597 (VEX_W_0F3839_P_2): Likewise.
598 (VEX_W_0F383A_P_2): Likewise.
599 (VEX_W_0F383B_P_2): Likewise.
600 (VEX_W_0F383C_P_2): Likewise.
601 (VEX_W_0F383D_P_2): Likewise.
602 (VEX_W_0F383E_P_2): Likewise.
603 (VEX_W_0F383F_P_2): Likewise.
604 (VEX_W_0F3840_P_2): Likewise.
605 (VEX_W_0F3841_P_2): Likewise.
606 (VEX_W_0F38DB_P_2): Likewise.
607 (VEX_W_0F3A08_P_2): Likewise.
608 (VEX_W_0F3A09_P_2): Likewise.
609 (VEX_W_0F3A0A_P_2): Likewise.
610 (VEX_W_0F3A0B_P_2): Likewise.
611 (VEX_W_0F3A0C_P_2): Likewise.
612 (VEX_W_0F3A0D_P_2): Likewise.
613 (VEX_W_0F3A0E_P_2): Likewise.
614 (VEX_W_0F3A0F_P_2): Likewise.
615 (VEX_W_0F3A21_P_2): Likewise.
616 (VEX_W_0F3A40_P_2): Likewise.
617 (VEX_W_0F3A41_P_2): Likewise.
618 (VEX_W_0F3A42_P_2): Likewise.
619 (VEX_W_0F3A62_P_2): Likewise.
620 (VEX_W_0F3A63_P_2): Likewise.
621 (VEX_W_0F3ADF_P_2): Likewise.
622 (VEX_LEN_0F77_P_0): New.
623 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
624 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
625 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
626 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
627 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
628 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
629 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
630 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
631 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
632 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
633 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
634 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
635 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
636 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
637 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
638 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
639 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
640 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
641 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
642 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
643 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
644 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
645 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
646 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
647 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
648 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
649 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
650 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
651 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
652 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
653 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
654 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
655 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
656 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
657 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
658 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
659 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
660 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
661 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
662 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
663 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
664 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
665 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
666 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
667 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
668 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
669 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
670 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
671 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
672 (vex_table): Update VEX 0F28 and 0F29 entries.
673 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
674 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
675 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
676 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
677 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
678 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
679 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
680 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
681 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
682 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
683 VEX_LEN_0F3A0B_P_2 entries.
684 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
685 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
686 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
687 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
688 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
689 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
690 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
691 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
692 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
693 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
694 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
695 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
696 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
697 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
698 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
699 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
700 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
701 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
702 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
703 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
704 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
705 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
706 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
707 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
708 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
709 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
710 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
711 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
712 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
713 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
714 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
715 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
716 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
717 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
718 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
719 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
720 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
721 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
722 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
723 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
724 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
725 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
726 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
727 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
728 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
729 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
730 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
731 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
732 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
733 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
734 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
735 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
736 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
737 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
738 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
739 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
740 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
741 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
742 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
743 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
744 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
745 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
746 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
747 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
748 VEX_W_0F3ADF_P_2 entries.
749 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
750 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
751 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
752
6fa52824
L		 7532018-09-17 H.J. Lu <hongjiu.lu@intel.com>
754
755 * i386-opc.tbl (VexWIG): New.
756 Replace VexW=3 with VexWIG.
757
db4cc665
L		 7582018-09-15 H.J. Lu <hongjiu.lu@intel.com>
759
760 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
761 * i386-tbl.h: Regenerated.
762
3c374143
L		 7632018-09-15 H.J. Lu <hongjiu.lu@intel.com>
764
765 PR gas/23665
766 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
767 VEX_LEN_0FD6_P_2 entries.
768 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
769 * i386-tbl.h: Regenerated.
770
6865c043
L		 7712018-09-14 H.J. Lu <hongjiu.lu@intel.com>
772
773 PR gas/23642
774 * i386-opc.h (VEXWIG): New.
775 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
776 * i386-tbl.h: Regenerated.
777
70df6fc9
L		 7782018-09-14 H.J. Lu <hongjiu.lu@intel.com>
779
780 PR binutils/23655
781 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
782 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
783 * i386-dis.c (EXxEVexR64): New.
784 (evex_rounding_64_mode): Likewise.
785 (OP_Rounding): Handle evex_rounding_64_mode.
786
d20dee9e
L		 7872018-09-14 H.J. Lu <hongjiu.lu@intel.com>
788
789 PR binutils/23655
790 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
791 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
792 * i386-dis.c (Edqa): New.
793 (dqa_mode): Likewise.
794 (intel_operand_size): Handle dqa_mode as m_mode.
795 (OP_E_register): Handle dqa_mode as dq_mode.
796 (OP_E_memory): Set shift for dqa_mode based on address_mode.
797
5074ad8a
L		 7982018-09-14 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-dis.c (OP_E_memory): Reformat.
801
556059dd
JB		 8022018-09-14 Jan Beulich <jbeulich@suse.com>
803
804 * i386-opc.tbl (crc32): Fold byte and word forms.
805 * i386-tbl.h: Re-generate.
806
41d1ab6a
L		 8072018-09-13 H.J. Lu <hongjiu.lu@intel.com>
808
809 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
810 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
811 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
812 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
813 * i386-tbl.h: Regenerated.
814
57f6375e
JB		 8152018-09-13 Jan Beulich <jbeulich@suse.com>
816
817 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
818 meaningless.
819 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
820 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
821 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
822 * i386-tbl.h: Re-generate.
823
2589a7e5
JB		 8242018-09-13 Jan Beulich <jbeulich@suse.com>
825
826 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
827 AVX512_4VNNIW insns.
828 * i386-tbl.h: Re-generate.
829
a760eb41
JB		 8302018-09-13 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
833 meaningless.
834 * i386-tbl.h: Re-generate.
835
e9042658
JB		 8362018-09-13 Jan Beulich <jbeulich@suse.com>
837
838 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
839 meaningless.
840 * i386-tbl.h: Re-generate.
841
9caa306f
JB		 8422018-09-13 Jan Beulich <jbeulich@suse.com>
843
844 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
845 meaningless.
846 * i386-tbl.h: Re-generate.
847
fb6ce599
JB		 8482018-09-13 Jan Beulich <jbeulich@suse.com>
849
850 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
851 meaningless.
852 * i386-tbl.h: Re-generate.
853
6a8da886
JB		 8542018-09-13 Jan Beulich <jbeulich@suse.com>
855
856 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
857 meaningless.
858 * i386-tbl.h: Re-generate.
859
c7f27919
JB		 8602018-09-13 Jan Beulich <jbeulich@suse.com>
861
862 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
863 * i386-tbl.h: Re-generate.
864
0f407ee9
JB		 8652018-09-13 Jan Beulich <jbeulich@suse.com>
866
867 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
868 * i386-tbl.h: Re-generate.
869
2fbbbee5
JB		 8702018-09-13 Jan Beulich <jbeulich@suse.com>
871
872 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
873 meaningless.
874 * i386-tbl.h: Re-generate.
875
2b02b9a2
JB		 8762018-09-13 Jan Beulich <jbeulich@suse.com>
877
878 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
879 meaningless.
880 * i386-tbl.h: Re-generate.
881
963c68aa
JB		 8822018-09-13 Jan Beulich <jbeulich@suse.com>
883
884 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
885 * i386-tbl.h: Re-generate.
886
64e025c3
JB		 8872018-09-13 Jan Beulich <jbeulich@suse.com>
888
889 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
890 * i386-tbl.h: Re-generate.
891
47603f88
JB		 8922018-09-13 Jan Beulich <jbeulich@suse.com>
893
894 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
895 * i386-tbl.h: Re-generate.
896
0001cfd0
JB		 8972018-09-13 Jan Beulich <jbeulich@suse.com>
898
899 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
900 meaningless.
901 * i386-tbl.h: Re-generate.
902
be4b452e
JB		 9032018-09-13 Jan Beulich <jbeulich@suse.com>
904
905 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
906 meaningless.
907 * i386-tbl.h: Re-generate.
908
d09a1394
JB		 9092018-09-13 Jan Beulich <jbeulich@suse.com>
910
911 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
912 meaningless.
913 * i386-tbl.h: Re-generate.
914
07599e13
JB		 9152018-09-13 Jan Beulich <jbeulich@suse.com>
916
917 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
918 * i386-tbl.h: Re-generate.
919
1ee3e487
JB		 9202018-09-13 Jan Beulich <jbeulich@suse.com>
921
922 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
923 * i386-tbl.h: Re-generate.
924
a5f580e5
JB		 9252018-09-13 Jan Beulich <jbeulich@suse.com>
926
927 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
928 * i386-tbl.h: Re-generate.
929
49d5d12d
JB		 9302018-09-13 Jan Beulich <jbeulich@suse.com>
931
932 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
933 (vpbroadcastw, rdpid): Drop NoRex64.
934 * i386-tbl.h: Re-generate.
935
f5eb1d70
JB		 9362018-09-13 Jan Beulich <jbeulich@suse.com>
937
938 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
939 store templates, adding D.
940 * i386-tbl.h: Re-generate.
941
dbbc8b7e
JB		 9422018-09-13 Jan Beulich <jbeulich@suse.com>
943
944 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
945 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
946 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
947 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
948 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
949 Fold load and store templates where possible, adding D. Drop
950 IgnoreSize where it was pointlessly present. Drop redundant
951 *word.
952 * i386-tbl.h: Re-generate.
953
d276ec69
JB		 9542018-09-13 Jan Beulich <jbeulich@suse.com>
955
956 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
957 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
958 (intel_operand_size): Handle v_bndmk_mode.
959 (OP_E_memory): Likewise. Produce (bad) when also riprel.
960
9da4dfd6
JD		 9612018-09-08 John Darrington <john@darrington.wattle.id.au>
962
963 * disassemble.c (ARCH_s12z): Define if ARCH_all.
964
be192bc2
JW		 9652018-08-31 Kito Cheng <kito@andestech.com>
966
967 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
968 compressed floating point instructions.
969
43135d3b
JW		 9702018-08-30 Kito Cheng <kito@andestech.com>
971
972 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
973 riscv_opcode.xlen_requirement.
974 * riscv-opc.c (riscv_opcodes): Update for struct change.
975
df28970f
MA		 9762018-08-29 Martin Aberg <maberg@gaisler.com>
977
978 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
979 psr (PWRPSR) instruction.
980
9108bc33
CX		 9812018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
982
983 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
984
bd782c07
CX		 9852018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
986
987 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
988
ac8cb70f
CX		 9892018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
990
991 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
992 loongson3a as an alias of gs464 for compatibility.
993 * mips-opc.c (mips_opcodes): Change Comments.
994
a693765e
CX		 9952018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
996
997 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
998 option.
999 (print_mips_disassembler_options): Document -M loongson-ext.
1000 * mips-opc.c (LEXT2): New macro.
1001 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1002
bdc6c06e
CX		 10032018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1004
1005 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1006 descriptors.
1007 (parse_mips_ase_option): Handle -M loongson-ext option.
1008 (print_mips_disassembler_options): Document -M loongson-ext.
1009 * mips-opc.c (IL3A): Delete.
1010 * mips-opc.c (LEXT): New macro.
1011 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1012 instructions.
1013
716c08de
CX		 10142018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1015
1016 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1017 descriptors.
1018 (parse_mips_ase_option): Handle -M loongson-cam option.
1019 (print_mips_disassembler_options): Document -M loongson-cam.
1020 * mips-opc.c (LCAM): New macro.
1021 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1022 instructions.
1023
9cf7e568
AM		 10242018-08-21 Alan Modra <amodra@gmail.com>
1025
1026 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1027 (skip_optional_operands): Count optional operands, and update
1028 ppc_optional_operand_value call.
1029 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1030 (extract_vlensi): Likewise.
1031 (extract_fxm): Return default value for missing optional operand.
1032 (extract_ls, extract_raq, extract_tbr): Likewise.
1033 (insert_sxl, extract_sxl): New functions.
1034 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1035 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1036 flag and extra entry.
1037 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1038 extract_sxl.
1039
d203b41a 10402018-08-20 Alan Modra <amodra@gmail.com>
f4107842 1041
d203b41a 1042 * sh-opc.h (MASK): Simplify.
f4107842 1043
08a8fe2f 10442018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 1045
d203b41a
AM		 1046 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1047 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 1048 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 1049
08a8fe2f 10502018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 1051
1052 * s12z.h: Delete.
7ba3ba91 1053
1bc60e56
L		 10542018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1055
1056 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1057 address with the addr32 prefix and without base nor index
1058 registers.
1059
d871f3f4
L		 10602018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1061
1062 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1063 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1064 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1065 (cpu_flags): Add CpuCMOV and CpuFXSR.
1066 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1067 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1068 * i386-init.h: Regenerated.
1069 * i386-tbl.h: Likewise.
1070
b6523c37 10712018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1072
1073 * arc-regs.h: Update auxiliary registers.
1074
e968fc9b
JB		 10752018-08-06 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1078 (RegIP, RegIZ): Define.
1079 * i386-reg.tbl: Adjust comments.
1080 (rip): Use Qword instead of BaseIndex. Use RegIP.
1081 (eip): Use Dword instead of BaseIndex. Use RegIP.
1082 (riz): Add Qword. Use RegIZ.
1083 (eiz): Add Dword. Use RegIZ.
1084 * i386-tbl.h: Re-generate.
1085
dbf8be89
JB		 10862018-08-03 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1089 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1090 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1091 * i386-tbl.h: Re-generate.
1092
c48dadc9
JB		 10932018-08-03 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-gen.c (operand_types): Remove Mem field.
1096 * i386-opc.h (union i386_operand_type): Remove mem field.
1097 * i386-init.h, i386-tbl.h: Re-generate.
1098
cb86a42a
AM		 10992018-08-01 Alan Modra <amodra@gmail.com>
1100
1101 * po/POTFILES.in: Regenerate.
1102
07cc0450
NC		 11032018-07-31 Nick Clifton <nickc@redhat.com>
1104
1105 * po/sv.po: Updated Swedish translation.
1106
1424ad86
JB		 11072018-07-31 Jan Beulich <jbeulich@suse.com>
1108
1109 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1110 * i386-init.h, i386-tbl.h: Re-generate.
1111
ae2387fe
JB		 11122018-07-31 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-opc.h (ZEROING_MASKING) Rename to ...
1115 (DYNAMIC_MASKING): ... this. Adjust comment.
1116 * i386-opc.tbl (MaskingMorZ): Define.
1117 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1118 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1119 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1120 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1121 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1122 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1123 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1124 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1125 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1126
6ff00b5e
JB		 11272018-07-31 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-opc.tbl: Use element rather than vector size for AVX512*
1130 scatter/gather insns.
1131 * i386-tbl.h: Re-generate.
1132
e951d5ca
JB		 11332018-07-31 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1136 (cpu_flags): Drop CpuVREX.
1137 * i386-opc.h (CpuVREX): Delete.
1138 (union i386_cpu_flags): Remove cpuvrex.
1139 * i386-init.h, i386-tbl.h: Re-generate.
1140
eb41b248
JW		 11412018-07-30 Jim Wilson <jimw@sifive.com>
1142
1143 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1144 fields.
1145 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1146
b8891f8d
AJ		 11472018-07-30 Andrew Jenner <andrew@codesourcery.com>
1148
1149 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1150 * Makefile.in: Regenerated.
1151 * configure.ac: Add C-SKY.
1152 * configure: Regenerated.
1153 * csky-dis.c: New file.
1154 * csky-opc.h: New file.
1155 * disassemble.c (ARCH_csky): Define.
1156 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1157 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1158
16065af1
AM		 11592018-07-27 Alan Modra <amodra@gmail.com>
1160
1161 * ppc-opc.c (insert_sprbat): Correct function parameter and
1162 return type.
1163 (extract_sprbat): Likewise, variable too.
1164
fa758a70
AC		 11652018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1166 Alan Modra <amodra@gmail.com>
1167
1168 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1169 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1170 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1171 support disjointed BAT.
1172 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1173 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1174 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1175
4a1b91ea
L		 11762018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1177 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1178
1179 * i386-gen.c (adjust_broadcast_modifier): New function.
1180 (process_i386_opcode_modifier): Add an argument for operands.
1181 Adjust the Broadcast value based on operands.
1182 (output_i386_opcode): Pass operand_types to
1183 process_i386_opcode_modifier.
1184 (process_i386_opcodes): Pass NULL as operands to
1185 process_i386_opcode_modifier.
1186 * i386-opc.h (BYTE_BROADCAST): New.
1187 (WORD_BROADCAST): Likewise.
1188 (DWORD_BROADCAST): Likewise.
1189 (QWORD_BROADCAST): Likewise.
1190 (i386_opcode_modifier): Expand broadcast to 3 bits.
1191 * i386-tbl.h: Regenerated.
1192
67ce483b
AM		 11932018-07-24 Alan Modra <amodra@gmail.com>
1194
1195 PR 23430
1196 * or1k-desc.h: Regenerate.
1197
4174bfff
JB		 11982018-07-24 Jan Beulich <jbeulich@suse.com>
1199
1200 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1201 vcvtusi2ss, and vcvtusi2sd.
1202 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1203 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1204 * i386-tbl.h: Re-generate.
1205
04e65276
CZ		 12062018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1207
1208 * arc-opc.c (extract_w6): Fix extending the sign.
1209
47e6f81c
CZ		 12102018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1211
1212 * arc-tbl.h (vewt): Allow it for ARC EM family.
1213
bb71536f
AM		 12142018-07-23 Alan Modra <amodra@gmail.com>
1215
1216 PR 23419
1217 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1218 opcode variants for mtspr/mfspr encodings.
1219
8095d2f7
CX		 12202018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1221 Maciej W. Rozycki <macro@mips.com>
1222
1223 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1224 loongson3a descriptors.
1225 (parse_mips_ase_option): Handle -M loongson-mmi option.
1226 (print_mips_disassembler_options): Document -M loongson-mmi.
1227 * mips-opc.c (LMMI): New macro.
1228 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1229 instructions.
1230
5f32791e
JB		 12312018-07-19 Jan Beulich <jbeulich@suse.com>
1232
1233 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1234 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1235 IgnoreSize and [XYZ]MMword where applicable.
1236 * i386-tbl.h: Re-generate.
1237
625cbd7a
JB		 12382018-07-19 Jan Beulich <jbeulich@suse.com>
1239
1240 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1241 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1242 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1243 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1244 * i386-tbl.h: Re-generate.
1245
86b15c32
JB		 12462018-07-19 Jan Beulich <jbeulich@suse.com>
1247
1248 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1249 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1250 VPCLMULQDQ templates into their respective AVX512VL counterparts
1251 where possible, using Disp8ShiftVL and CheckRegSize instead of
1252 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1253 * i386-tbl.h: Re-generate.
1254
cf769ed5
JB		 12552018-07-19 Jan Beulich <jbeulich@suse.com>
1256
1257 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1258 AVX512VL counterparts where possible, using Disp8ShiftVL and
1259 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1260 IgnoreSize) as appropriate.
1261 * i386-tbl.h: Re-generate.
1262
8282b7ad
JB		 12632018-07-19 Jan Beulich <jbeulich@suse.com>
1264
1265 * i386-opc.tbl: Fold AVX512BW templates into their respective
1266 AVX512VL counterparts where possible, using Disp8ShiftVL and
1267 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1268 IgnoreSize) as appropriate.
1269 * i386-tbl.h: Re-generate.
1270
755908cc
JB		 12712018-07-19 Jan Beulich <jbeulich@suse.com>
1272
1273 * i386-opc.tbl: Fold AVX512CD templates into their respective
1274 AVX512VL counterparts where possible, using Disp8ShiftVL and
1275 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1276 IgnoreSize) as appropriate.
1277 * i386-tbl.h: Re-generate.
1278
7091c612
JB		 12792018-07-19 Jan Beulich <jbeulich@suse.com>
1280
1281 * i386-opc.h (DISP8_SHIFT_VL): New.
1282 * i386-opc.tbl (Disp8ShiftVL): Define.
1283 (various): Fold AVX512VL templates into their respective
1284 AVX512F counterparts where possible, using Disp8ShiftVL and
1285 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1286 IgnoreSize) as appropriate.
1287 * i386-tbl.h: Re-generate.
1288
c30be56e
JB		 12892018-07-19 Jan Beulich <jbeulich@suse.com>
1290
1291 * Makefile.am: Change dependencies and rule for
1292 $(srcdir)/i386-init.h.
1293 * Makefile.in: Re-generate.
1294 * i386-gen.c (process_i386_opcodes): New local variable
1295 "marker". Drop opening of input file. Recognize marker and line
1296 number directives.
1297 * i386-opc.tbl (OPCODE_I386_H): Define.
1298 (i386-opc.h): Include it.
1299 (None): Undefine.
1300
11a322db
L		 13012018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 PR gas/23418
1304 * i386-opc.h (Byte): Update comments.
1305 (Word): Likewise.
1306 (Dword): Likewise.
1307 (Fword): Likewise.
1308 (Qword): Likewise.
1309 (Tbyte): Likewise.
1310 (Xmmword): Likewise.
1311 (Ymmword): Likewise.
1312 (Zmmword): Likewise.
1313 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1314 vcvttps2uqq.
1315 * i386-tbl.h: Regenerated.
1316
cde3679e
NC		 13172018-07-12 Sudakshina Das <sudi.das@arm.com>
1318
1319 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1320 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1321 * aarch64-asm-2.c: Regenerate.
1322 * aarch64-dis-2.c: Regenerate.
1323 * aarch64-opc-2.c: Regenerate.
1324
45a28947
TC		 13252018-07-12 Tamar Christina <tamar.christina@arm.com>
1326
1327 PR binutils/23192
1328 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1329 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1330 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1331 sqdmulh, sqrdmulh): Use Em16.
1332
c597cc3d
SD		 13332018-07-11 Sudakshina Das <sudi.das@arm.com>
1334
1335 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1336 csdb together with them.
1337 (thumb32_opcodes): Likewise.
1338
a79eaed6
JB		 13392018-07-11 Jan Beulich <jbeulich@suse.com>
1340
1341 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1342 requiring 32-bit registers as operands 2 and 3. Improve
1343 comments.
1344 (mwait, mwaitx): Fold templates. Improve comments.
1345 OPERAND_TYPE_INOUTPORTREG.
1346 * i386-tbl.h: Re-generate.
1347
2fb5be8d
JB		 13482018-07-11 Jan Beulich <jbeulich@suse.com>
1349
1350 * i386-gen.c (operand_type_init): Remove
1351 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1352 OPERAND_TYPE_INOUTPORTREG.
1353 * i386-init.h: Re-generate.
1354
7f5cad30
JB		 13552018-07-11 Jan Beulich <jbeulich@suse.com>
1356
1357 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1358 (wrssq, wrussq): Add Qword.
1359 * i386-tbl.h: Re-generate.
1360
f0a85b07
JB		 13612018-07-11 Jan Beulich <jbeulich@suse.com>
1362
1363 * i386-opc.h: Rename OTMax to OTNum.
1364 (OTNumOfUints): Adjust calculation.
1365 (OTUnused): Directly alias to OTNum.
1366
9dcb0ba4
MR		 13672018-07-09 Maciej W. Rozycki <macro@mips.com>
1368
1369 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1370 `reg_xys'.
1371 (lea_reg_xys): Likewise.
1372 (print_insn_loop_primitive): Rename `reg' local variable to
1373 `reg_dxy'.
1374
f311ba7e
TC		 13752018-07-06 Tamar Christina <tamar.christina@arm.com>
1376
1377 PR binutils/23242
1378 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1379
cba05feb
TC		 13802018-07-06 Tamar Christina <tamar.christina@arm.com>
1381
1382 PR binutils/23369
1383 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1384 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1385
471b9d15
MR		 13862018-07-02 Maciej W. Rozycki <macro@mips.com>
1387
1388 PR tdep/8282
1389 * mips-dis.c (mips_option_arg_t): New enumeration.
1390 (mips_options): New variable.
1391 (disassembler_options_mips): New function.
1392 (print_mips_disassembler_options): Reimplement in terms of
1393 `disassembler_options_mips'.
1394 * arm-dis.c (disassembler_options_arm): Adapt to using the
1395 `disasm_options_and_args_t' structure.
1396 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1397 * s390-dis.c (disassembler_options_s390): Likewise.
1398
c0c468d5
TP		 13992018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1400
1401 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1402 expected result.
1403 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1404 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1405 * testsuite/ld-arm/tls-longplt.d: Likewise.
1406
369c9167
TC		 14072018-06-29 Tamar Christina <tamar.christina@arm.com>
1408
1409 PR binutils/23192
1410 * aarch64-asm-2.c: Regenerate.
1411 * aarch64-dis-2.c: Likewise.
1412 * aarch64-opc-2.c: Likewise.
1413 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1414 * aarch64-opc.c (operand_general_constraint_met_p,
1415 aarch64_print_operand): Likewise.
1416 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1417 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1418 fmlal2, fmlsl2.
1419 (AARCH64_OPERANDS): Add Em2.
1420
30aa1306
NC		 14212018-06-26 Nick Clifton <nickc@redhat.com>
1422
1423 * po/uk.po: Updated Ukranian translation.
1424 * po/de.po: Updated German translation.
1425 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1426
eca4b721
NC		 14272018-06-26 Nick Clifton <nickc@redhat.com>
1428
1429 * nfp-dis.c: Fix spelling mistake.
1430
71300e2c
NC		 14312018-06-24 Nick Clifton <nickc@redhat.com>
1432
1433 * configure: Regenerate.
1434 * po/opcodes.pot: Regenerate.
1435
719d8288
NC		 14362018-06-24 Nick Clifton <nickc@redhat.com>
1437
1438 2.31 branch created.
1439
514cd3a0
TC		 14402018-06-19 Tamar Christina <tamar.christina@arm.com>
1441
1442 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1443 * aarch64-asm-2.c: Regenerate.
1444 * aarch64-dis-2.c: Likewise.
1445
385e4d0f
MR		 14462018-06-21 Maciej W. Rozycki <macro@mips.com>
1447
1448 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1449 `-M ginv' option description.
1450
160d1b3d
SH		 14512018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1452
1453 PR gas/23305
1454 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1455 la and lla.
1456
d0ac1c44
SM		 14572018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1458
1459 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1460 * configure.ac: Remove AC_PREREQ.
1461 * Makefile.in: Re-generate.
1462 * aclocal.m4: Re-generate.
1463 * configure: Re-generate.
1464
6f20c942
FS		 14652018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1466
1467 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1468 mips64r6 descriptors.
1469 (parse_mips_ase_option): Handle -Mginv option.
1470 (print_mips_disassembler_options): Document -Mginv.
1471 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1472 (GINV): New macro.
1473 (mips_opcodes): Define ginvi and ginvt.
1474
730c3174
SE		 14752018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1476 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1477
1478 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1479 * mips-opc.c (CRC, CRC64): New macros.
1480 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1481 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1482 crc32cd for CRC64.
1483
cb366992
EB		 14842018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1485
1486 PR 20319
1487 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1488 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1489
ce72cd46
AM		 14902018-06-06 Alan Modra <amodra@gmail.com>
1491
1492 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1493 setjmp. Move init for some other vars later too.
1494
4b8e28c7
MF		 14952018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1496
1497 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1498 (dis_private): Add new fields for property section tracking.
1499 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1500 (xtensa_instruction_fits): New functions.
1501 (fetch_data): Bump minimal fetch size to 4.
1502 (print_insn_xtensa): Make struct dis_private static.
1503 Load and prepare property table on section change.
1504 Don't disassemble literals. Don't disassemble instructions that
1505 cross property table boundaries.
1506
55e99962
L		 15072018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1508
1509 * configure: Regenerated.
1510
733bd0ab
JB		 15112018-06-01 Jan Beulich <jbeulich@suse.com>
1512
1513 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1514 * i386-tbl.h: Re-generate.
1515
dfd27d41
JB		 15162018-06-01 Jan Beulich <jbeulich@suse.com>
1517
1518 * i386-opc.tbl (sldt, str): Add NoRex64.
1519 * i386-tbl.h: Re-generate.
1520
64795710
JB		 15212018-06-01 Jan Beulich <jbeulich@suse.com>
1522
1523 * i386-opc.tbl (invpcid): Add Oword.
1524 * i386-tbl.h: Re-generate.
1525
030157d8
AM		 15262018-06-01 Alan Modra <amodra@gmail.com>
1527
1528 * sysdep.h (_bfd_error_handler): Don't declare.
1529 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1530 * rl78-decode.opc: Likewise.
1531 * msp430-decode.c: Regenerate.
1532 * rl78-decode.c: Regenerate.
1533
a9660a6f
AP		 15342018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1535
1536 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1537 * i386-init.h : Regenerated.
1538
277eb7f6
AM		 15392018-05-25 Alan Modra <amodra@gmail.com>
1540
1541 * Makefile.in: Regenerate.
1542 * po/POTFILES.in: Regenerate.
1543
98553ad3
PB		 15442018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1545
1546 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1547 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1548 (insert_bab, extract_bab, insert_btab, extract_btab,
1549 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1550 (BAT, BBA VBA RBS XB6S): Delete macros.
1551 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1552 (BB, BD, RBX, XC6): Update for new macros.
1553 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1554 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1555 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1556 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1557
7b4ae824
JD		 15582018-05-18 John Darrington <john@darrington.wattle.id.au>
1559
1560 * Makefile.am: Add support for s12z architecture.
1561 * configure.ac: Likewise.
1562 * disassemble.c: Likewise.
1563 * disassemble.h: Likewise.
1564 * Makefile.in: Regenerate.
1565 * configure: Regenerate.
1566 * s12z-dis.c: New file.
1567 * s12z.h: New file.
1568
29e0f0a1
AM		 15692018-05-18 Alan Modra <amodra@gmail.com>
1570
1571 * nfp-dis.c: Don't #include libbfd.h.
1572 (init_nfp3200_priv): Use bfd_get_section_contents.
1573 (nit_nfp6000_mecsr_sec): Likewise.
1574
809276d2
NC		 15752018-05-17 Nick Clifton <nickc@redhat.com>
1576
1577 * po/zh_CN.po: Updated simplified Chinese translation.
1578
ff329288
TC		 15792018-05-16 Tamar Christina <tamar.christina@arm.com>
1580
1581 PR binutils/23109
1582 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1583 * aarch64-dis-2.c: Regenerate.
1584
f9830ec1
TC		 15852018-05-15 Tamar Christina <tamar.christina@arm.com>
1586
1587 PR binutils/21446
1588 * aarch64-asm.c (opintl.h): Include.
1589 (aarch64_ins_sysreg): Enforce read/write constraints.
1590 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1591 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1592 (F_REG_READ, F_REG_WRITE): New.
1593 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1594 AARCH64_OPND_SYSREG.
1595 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1596 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1597 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1598 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1599 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1600 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1601 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1602 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1603 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1604 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1605 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1606 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1607 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1608 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1609 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1610 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1611 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1612
7d02540a
TC		 16132018-05-15 Tamar Christina <tamar.christina@arm.com>
1614
1615 PR binutils/21446
1616 * aarch64-dis.c (no_notes: New.
1617 (parse_aarch64_dis_option): Support notes.
1618 (aarch64_decode_insn, print_operands): Likewise.
1619 (print_aarch64_disassembler_options): Document notes.
1620 * aarch64-opc.c (aarch64_print_operand): Support notes.
1621
561a72d4
TC		 16222018-05-15 Tamar Christina <tamar.christina@arm.com>
1623
1624 PR binutils/21446
1625 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1626 and take error struct.
1627 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1628 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1629 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1630 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1631 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1632 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1633 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1634 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1635 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1636 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1637 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1638 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1639 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1640 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1641 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1642 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1643 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1644 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1645 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1646 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1647 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1648 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1649 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1650 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1651 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1652 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1653 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1654 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1655 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1656 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1657 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1658 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1659 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1660 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1661 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1662 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1663 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1664 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1665 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1666 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1667 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1668 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1669 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1670 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1671 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1672 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1673 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1674 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1675 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1676 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1677 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1678 (determine_disassembling_preference, aarch64_decode_insn,
1679 print_insn_aarch64_word, print_insn_data): Take errors struct.
1680 (print_insn_aarch64): Use errors.
1681 * aarch64-asm-2.c: Regenerate.
1682 * aarch64-dis-2.c: Regenerate.
1683 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1684 boolean in aarch64_insert_operan.
1685 (print_operand_extractor): Likewise.
1686 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1687
1678bd35
FT		 16882018-05-15 Francois H. Theron <francois.theron@netronome.com>
1689
1690 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1691
06cfb1c8
L		 16922018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1693
1694 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1695
84f9f8c3
AM		 16962018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1697
1698 * cr16-opc.c (cr16_instruction): Comment typo fix.
1699 * hppa-dis.c (print_insn_hppa): Likewise.
1700
e6f372ba
JW		 17012018-05-08 Jim Wilson <jimw@sifive.com>
1702
1703 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1704 (match_c_slli64, match_srxi_as_c_srxi): New.
1705 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1706 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1707 <c.slli, c.srli, c.srai>: Use match_s_slli.
1708 <c.slli64, c.srli64, c.srai64>: New.
1709
f413a913
AM		 17102018-05-08 Alan Modra <amodra@gmail.com>
1711
1712 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1713 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1714 partition opcode space for index lookup.
1715
a87a6478
PB		 17162018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1717
1718 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1719 <insn_length>: ...with this. Update usage.
1720 Remove duplicate call to *info->memory_error_func.
1721
c0a30a9f
L		 17222018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1723 H.J. Lu <hongjiu.lu@intel.com>
1724
1725 * i386-dis.c (Gva): New.
1726 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1727 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1728 (prefix_table): New instructions (see prefix above).
1729 (mod_table): New instructions (see prefix above).
1730 (OP_G): Handle va_mode.
1731 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1732 CPU_MOVDIR64B_FLAGS.
1733 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1734 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1735 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1736 * i386-opc.tbl: Add movidir{i,64b}.
1737 * i386-init.h: Regenerated.
1738 * i386-tbl.h: Likewise.
1739
75c0a438
L		 17402018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1741
1742 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1743 AddrPrefixOpReg.
1744 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1745 (AddrPrefixOpReg): This.
1746 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1747 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1748
2ceb7719
PB		 17492018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1750
1751 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1752 (vle_num_opcodes): Likewise.
1753 (spe2_num_opcodes): Likewise.
1754 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1755 initialization loop.
1756 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1757 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1758 only once.
1759
b3ac5c6c
TC		 17602018-05-01 Tamar Christina <tamar.christina@arm.com>
1761
1762 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1763
fe944acf
FT		 17642018-04-30 Francois H. Theron <francois.theron@netronome.com>
1765
1766 Makefile.am: Added nfp-dis.c.
1767 configure.ac: Added bfd_nfp_arch.
1768 disassemble.h: Added print_insn_nfp prototype.
1769 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1770 nfp-dis.c: New, for NFP support.
1771 po/POTFILES.in: Added nfp-dis.c to the list.
1772 Makefile.in: Regenerate.
1773 configure: Regenerate.
1774
e2195274
JB		 17752018-04-26 Jan Beulich <jbeulich@suse.com>
1776
1777 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1778 templates into their base ones.
1779 * i386-tlb.h: Re-generate.
1780
59ef5df4
JB		 17812018-04-26 Jan Beulich <jbeulich@suse.com>
1782
1783 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1784 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1785 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1786 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1787 * i386-init.h: Re-generate.
1788
6e041cf4
JB		 17892018-04-26 Jan Beulich <jbeulich@suse.com>
1790
1791 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1792 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1793 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1794 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1795 comment.
1796 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1797 and CpuRegMask.
1798 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1799 CpuRegMask: Delete.
1800 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1801 cpuregzmm, and cpuregmask.
1802 * i386-init.h: Re-generate.
1803 * i386-tbl.h: Re-generate.
1804
0e0eea78
JB		 18052018-04-26 Jan Beulich <jbeulich@suse.com>
1806
1807 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1808 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1809 * i386-init.h: Re-generate.
1810
2f1bada2
JB		 18112018-04-26 Jan Beulich <jbeulich@suse.com>
1812
1813 * i386-gen.c (VexImmExt): Delete.
1814 * i386-opc.h (VexImmExt, veximmext): Delete.
1815 * i386-opc.tbl: Drop all VexImmExt uses.
1816 * i386-tlb.h: Re-generate.
1817
bacd1457
JB		 18182018-04-25 Jan Beulich <jbeulich@suse.com>
1819
1820 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1821 register-only forms.
1822 * i386-tlb.h: Re-generate.
1823
10bba94b
TC		 18242018-04-25 Tamar Christina <tamar.christina@arm.com>
1825
1826 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1827
c48935d7
IT		 18282018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1829
1830 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1831 PREFIX_0F1C.
1832 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1833 (cpu_flags): Add CpuCLDEMOTE.
1834 * i386-init.h: Regenerate.
1835 * i386-opc.h (enum): Add CpuCLDEMOTE,
1836 (i386_cpu_flags): Add cpucldemote.
1837 * i386-opc.tbl: Add cldemote.
1838 * i386-tbl.h: Regenerate.
1839
211dc24b
AM		 18402018-04-16 Alan Modra <amodra@gmail.com>
1841
1842 * Makefile.am: Remove sh5 and sh64 support.
1843 * configure.ac: Likewise.
1844 * disassemble.c: Likewise.
1845 * disassemble.h: Likewise.
1846 * sh-dis.c: Likewise.
1847 * sh64-dis.c: Delete.
1848 * sh64-opc.c: Delete.
1849 * sh64-opc.h: Delete.
1850 * Makefile.in: Regenerate.
1851 * configure: Regenerate.
1852 * po/POTFILES.in: Regenerate.
1853
a9a4b302
AM		 18542018-04-16 Alan Modra <amodra@gmail.com>
1855
1856 * Makefile.am: Remove w65 support.
1857 * configure.ac: Likewise.
1858 * disassemble.c: Likewise.
1859 * disassemble.h: Likewise.
1860 * w65-dis.c: Delete.
1861 * w65-opc.h: Delete.
1862 * Makefile.in: Regenerate.
1863 * configure: Regenerate.
1864 * po/POTFILES.in: Regenerate.
1865
04cb01fd
AM		 18662018-04-16 Alan Modra <amodra@gmail.com>
1867
1868 * configure.ac: Remove we32k support.
1869 * configure: Regenerate.
1870
c2bf1eec
AM		 18712018-04-16 Alan Modra <amodra@gmail.com>
1872
1873 * Makefile.am: Remove m88k support.
1874 * configure.ac: Likewise.
1875 * disassemble.c: Likewise.
1876 * disassemble.h: Likewise.
1877 * m88k-dis.c: Delete.
1878 * Makefile.in: Regenerate.
1879 * configure: Regenerate.
1880 * po/POTFILES.in: Regenerate.
1881
6793974d
AM		 18822018-04-16 Alan Modra <amodra@gmail.com>
1883
1884 * Makefile.am: Remove i370 support.
1885 * configure.ac: Likewise.
1886 * disassemble.c: Likewise.
1887 * disassemble.h: Likewise.
1888 * i370-dis.c: Delete.
1889 * i370-opc.c: Delete.
1890 * Makefile.in: Regenerate.
1891 * configure: Regenerate.
1892 * po/POTFILES.in: Regenerate.
1893
e82aa794
AM		 18942018-04-16 Alan Modra <amodra@gmail.com>
1895
1896 * Makefile.am: Remove h8500 support.
1897 * configure.ac: Likewise.
1898 * disassemble.c: Likewise.
1899 * disassemble.h: Likewise.
1900 * h8500-dis.c: Delete.
1901 * h8500-opc.h: Delete.
1902 * Makefile.in: Regenerate.
1903 * configure: Regenerate.
1904 * po/POTFILES.in: Regenerate.
1905
fceadf09
AM		 19062018-04-16 Alan Modra <amodra@gmail.com>
1907
1908 * configure.ac: Remove tahoe support.
1909 * configure: Regenerate.
1910
ae1d3843
L		 19112018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1912
1913 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1914 umwait.
1915 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1916 64-bit mode.
1917 * i386-tbl.h: Regenerated.
1918
de89d0a3
IT		 19192018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1920
1921 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1922 PREFIX_MOD_1_0FAE_REG_6.
1923 (va_mode): New.
1924 (OP_E_register): Use va_mode.
1925 * i386-dis-evex.h (prefix_table):
1926 New instructions (see prefixes above).
1927 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1928 (cpu_flags): Likewise.
1929 * i386-opc.h (enum): Likewise.
1930 (i386_cpu_flags): Likewise.
1931 * i386-opc.tbl: Add umonitor, umwait, tpause.
1932 * i386-init.h: Regenerate.
1933 * i386-tbl.h: Likewise.
1934
a8eb42a8
AM		 19352018-04-11 Alan Modra <amodra@gmail.com>
1936
1937 * opcodes/i860-dis.c: Delete.
1938 * opcodes/i960-dis.c: Delete.
1939 * Makefile.am: Remove i860 and i960 support.
1940 * configure.ac: Likewise.
1941 * disassemble.c: Likewise.
1942 * disassemble.h: Likewise.
1943 * Makefile.in: Regenerate.
1944 * configure: Regenerate.
1945 * po/POTFILES.in: Regenerate.
1946
caf0678c
L		 19472018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1948
1949 PR binutils/23025
1950 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1951 to 0.
1952 (print_insn): Clear vex instead of vex.evex.
1953
4fb0d2b9
NC		 19542018-04-04 Nick Clifton <nickc@redhat.com>
1955
1956 * po/es.po: Updated Spanish translation.
1957
c39e5b26
JB		 19582018-03-28 Jan Beulich <jbeulich@suse.com>
1959
1960 * i386-gen.c (opcode_modifiers): Delete VecESize.
1961 * i386-opc.h (VecESize): Delete.
1962 (struct i386_opcode_modifier): Delete vecesize.
1963 * i386-opc.tbl: Drop VecESize.
1964 * i386-tlb.h: Re-generate.
1965
8e6e0792
JB		 19662018-03-28 Jan Beulich <jbeulich@suse.com>
1967
1968 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1969 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1970 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1971 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1972 * i386-tlb.h: Re-generate.
1973
9f123b91
JB		 19742018-03-28 Jan Beulich <jbeulich@suse.com>
1975
1976 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1977 Fold AVX512 forms
1978 * i386-tlb.h: Re-generate.
1979
9646c87b
JB		 19802018-03-28 Jan Beulich <jbeulich@suse.com>
1981
1982 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1983 (vex_len_table): Drop Y for vcvt*2si.
1984 (putop): Replace plain 'Y' handling by abort().
1985
c8d59609
NC		 19862018-03-28 Nick Clifton <nickc@redhat.com>
1987
1988 PR 22988
1989 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1990 instructions with only a base address register.
1991 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1992 handle AARHC64_OPND_SVE_ADDR_R.
1993 (aarch64_print_operand): Likewise.
1994 * aarch64-asm-2.c: Regenerate.
1995 * aarch64_dis-2.c: Regenerate.
1996 * aarch64-opc-2.c: Regenerate.
1997
b8c169f3
JB		 19982018-03-22 Jan Beulich <jbeulich@suse.com>
1999
2000 * i386-opc.tbl: Drop VecESize from register only insn forms and
2001 memory forms not allowing broadcast.
2002 * i386-tlb.h: Re-generate.
2003
96bc132a
JB		 20042018-03-22 Jan Beulich <jbeulich@suse.com>
2005
2006 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2007 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2008 sha256*): Drop Disp<N>.
2009
9f79e886
JB		 20102018-03-22 Jan Beulich <jbeulich@suse.com>
2011
2012 * i386-dis.c (EbndS, bnd_swap_mode): New.
2013 (prefix_table): Use EbndS.
2014 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2015 * i386-opc.tbl (bndmov): Move misplaced Load.
2016 * i386-tlb.h: Re-generate.
2017
d6793fa1
JB		 20182018-03-22 Jan Beulich <jbeulich@suse.com>
2019
2020 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2021 templates allowing memory operands and folded ones for register
2022 only flavors.
2023 * i386-tlb.h: Re-generate.
2024
f7768225
JB		 20252018-03-22 Jan Beulich <jbeulich@suse.com>
2026
2027 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2028 256-bit templates. Drop redundant leftover Disp<N>.
2029 * i386-tlb.h: Re-generate.
2030
0e35537d
JW		 20312018-03-14 Kito Cheng <kito.cheng@gmail.com>
2032
2033 * riscv-opc.c (riscv_insn_types): New.
2034
b4a3689a
NC		 20352018-03-13 Nick Clifton <nickc@redhat.com>
2036
2037 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2038
d3d50934
L		 20392018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2040
2041 * i386-opc.tbl: Add Optimize to clr.
2042 * i386-tbl.h: Regenerated.
2043
bd5dea88
L		 20442018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2045
2046 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2047 * i386-opc.h (OldGcc): Removed.
2048 (i386_opcode_modifier): Remove oldgcc.
2049 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2050 instructions for old (<= 2.8.1) versions of gcc.
2051 * i386-tbl.h: Regenerated.
2052
e771e7c9
JB		 20532018-03-08 Jan Beulich <jbeulich@suse.com>
2054
2055 * i386-opc.h (EVEXDYN): New.
2056 * i386-opc.tbl: Fold various AVX512VL templates.
2057 * i386-tlb.h: Re-generate.
2058
ed438a93
JB		 20592018-03-08 Jan Beulich <jbeulich@suse.com>
2060
2061 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2062 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2063 vpexpandd, vpexpandq): Fold AFX512VF templates.
2064 * i386-tlb.h: Re-generate.
2065
454172a9
JB		 20662018-03-08 Jan Beulich <jbeulich@suse.com>
2067
2068 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2069 Fold 128- and 256-bit VEX-encoded templates.
2070 * i386-tlb.h: Re-generate.
2071
36824150
JB		 20722018-03-08 Jan Beulich <jbeulich@suse.com>
2073
2074 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2075 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2076 vpexpandd, vpexpandq): Fold AVX512F templates.
2077 * i386-tlb.h: Re-generate.
2078
e7f5c0a9
JB		 20792018-03-08 Jan Beulich <jbeulich@suse.com>
2080
2081 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2082 64-bit templates. Drop Disp<N>.
2083 * i386-tlb.h: Re-generate.
2084
25a4277f
JB		 20852018-03-08 Jan Beulich <jbeulich@suse.com>
2086
2087 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2088 and 256-bit templates.
2089 * i386-tlb.h: Re-generate.
2090
d2224064
JB		 20912018-03-08 Jan Beulich <jbeulich@suse.com>
2092
2093 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2094 * i386-tlb.h: Re-generate.
2095
1b193f0b
JB		 20962018-03-08 Jan Beulich <jbeulich@suse.com>
2097
2098 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2099 Drop NoAVX.
2100 * i386-tlb.h: Re-generate.
2101
f2f6a710
JB		 21022018-03-08 Jan Beulich <jbeulich@suse.com>
2103
2104 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2105 * i386-tlb.h: Re-generate.
2106
38e314eb
JB		 21072018-03-08 Jan Beulich <jbeulich@suse.com>
2108
2109 * i386-gen.c (opcode_modifiers): Delete FloatD.
2110 * i386-opc.h (FloatD): Delete.
2111 (struct i386_opcode_modifier): Delete floatd.
2112 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2113 FloatD by D.
2114 * i386-tlb.h: Re-generate.
2115
d53e6b98
JB		 21162018-03-08 Jan Beulich <jbeulich@suse.com>
2117
2118 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2119
2907c2f5
JB		 21202018-03-08 Jan Beulich <jbeulich@suse.com>
2121
2122 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2123 * i386-tlb.h: Re-generate.
2124
73053c1f
JB		 21252018-03-08 Jan Beulich <jbeulich@suse.com>
2126
2127 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2128 forms.
2129 * i386-tlb.h: Re-generate.
2130
52fe4420
AM		 21312018-03-07 Alan Modra <amodra@gmail.com>
2132
2133 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2134 bfd_arch_rs6000.
2135 * disassemble.h (print_insn_rs6000): Delete.
2136 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2137 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2138 (print_insn_rs6000): Delete.
2139
a6743a54
AM		 21402018-03-03 Alan Modra <amodra@gmail.com>
2141
2142 * sysdep.h (opcodes_error_handler): Define.
2143 (_bfd_error_handler): Declare.
2144 * Makefile.am: Remove stray #.
2145 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2146 EDIT" comment.
2147 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2148 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2149 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2150 opcodes_error_handler to print errors. Standardize error messages.
2151 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2152 and include opintl.h.
2153 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2154 * i386-gen.c: Standardize error messages.
2155 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2156 * Makefile.in: Regenerate.
2157 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2158 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2159 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2160 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2161 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2162 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2163 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2164 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2165 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2166 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2167 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2168 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2169 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2170
8305403a
L		 21712018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2172
2173 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2174 vpsub[bwdq] instructions.
2175 * i386-tbl.h: Regenerated.
2176
e184813f
AM		 21772018-03-01 Alan Modra <amodra@gmail.com>
2178
2179 * configure.ac (ALL_LINGUAS): Sort.
2180 * configure: Regenerate.
2181
5b616bef
TP		 21822018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2183
2184 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2185 macro by assignements.
2186
b6f8c7c4
L		 21872018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2188
2189 PR gas/22871
2190 * i386-gen.c (opcode_modifiers): Add Optimize.
2191 * i386-opc.h (Optimize): New enum.
2192 (i386_opcode_modifier): Add optimize.
2193 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2194 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2195 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2196 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2197 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2198 vpxord and vpxorq.
2199 * i386-tbl.h: Regenerated.
2200
e95b887f
AM		 22012018-02-26 Alan Modra <amodra@gmail.com>
2202
2203 * crx-dis.c (getregliststring): Allocate a large enough buffer
2204 to silence false positive gcc8 warning.
2205
0bccfb29
JW		 22062018-02-22 Shea Levy <shea@shealevy.com>
2207
2208 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2209
6b6b6807
L		 22102018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2211
2212 * i386-opc.tbl: Add {rex},
2213 * i386-tbl.h: Regenerated.
2214
75f31665
MR		 22152018-02-20 Maciej W. Rozycki <macro@mips.com>
2216
2217 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2218 (mips16_opcodes): Replace `M' with `m' for "restore".
2219
e207bc53
TP		 22202018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2221
2222 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2223
87993319
MR		 22242018-02-13 Maciej W. Rozycki <macro@mips.com>
2225
2226 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2227 variable to `function_index'.
2228
68d20676
NC		 22292018-02-13 Nick Clifton <nickc@redhat.com>
2230
2231 PR 22823
2232 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2233 about truncation of printing.
2234
d2159fdc
HW		 22352018-02-12 Henry Wong <henry@stuffedcow.net>
2236
2237 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2238
f174ef9f
NC		 22392018-02-05 Nick Clifton <nickc@redhat.com>
2240
2241 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2242
be3a8dca
IT		 22432018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2244
2245 * i386-dis.c (enum): Add pconfig.
2246 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2247 (cpu_flags): Add CpuPCONFIG.
2248 * i386-opc.h (enum): Add CpuPCONFIG.
2249 (i386_cpu_flags): Add cpupconfig.
2250 * i386-opc.tbl: Add PCONFIG instruction.
2251 * i386-init.h: Regenerate.
2252 * i386-tbl.h: Likewise.
2253
3233d7d0
IT		 22542018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2255
2256 * i386-dis.c (enum): Add PREFIX_0F09.
2257 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2258 (cpu_flags): Add CpuWBNOINVD.
2259 * i386-opc.h (enum): Add CpuWBNOINVD.
2260 (i386_cpu_flags): Add cpuwbnoinvd.
2261 * i386-opc.tbl: Add WBNOINVD instruction.
2262 * i386-init.h: Regenerate.
2263 * i386-tbl.h: Likewise.
2264
e925c834
JW		 22652018-01-17 Jim Wilson <jimw@sifive.com>
2266
2267 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2268
d777820b
IT		 22692018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2270
2271 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2272 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2273 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2274 (cpu_flags): Add CpuIBT, CpuSHSTK.
2275 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2276 (i386_cpu_flags): Add cpuibt, cpushstk.
2277 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2278 * i386-init.h: Regenerate.
2279 * i386-tbl.h: Likewise.
2280
f6efed01
NC		 22812018-01-16 Nick Clifton <nickc@redhat.com>
2282
2283 * po/pt_BR.po: Updated Brazilian Portugese translation.
2284 * po/de.po: Updated German translation.
2285
2721d702
JW		 22862018-01-15 Jim Wilson <jimw@sifive.com>
2287
2288 * riscv-opc.c (match_c_nop): New.
2289 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2290
616dcb87
NC		 22912018-01-15 Nick Clifton <nickc@redhat.com>
2292
2293 * po/uk.po: Updated Ukranian translation.
2294
3957a496
NC		 22952018-01-13 Nick Clifton <nickc@redhat.com>
2296
2297 * po/opcodes.pot: Regenerated.
2298
769c7ea5
NC		 22992018-01-13 Nick Clifton <nickc@redhat.com>
2300
2301 * configure: Regenerate.
2302
faf766e3
NC		 23032018-01-13 Nick Clifton <nickc@redhat.com>
2304
2305 2.30 branch created.
2306
888a89da
IT		 23072018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2308
2309 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2310 * i386-tbl.h: Regenerate.
2311
cbda583a
JB		 23122018-01-10 Jan Beulich <jbeulich@suse.com>
2313
2314 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2315 * i386-tbl.h: Re-generate.
2316
c9e92278
JB		 23172018-01-10 Jan Beulich <jbeulich@suse.com>
2318
2319 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2320 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2321 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2322 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2323 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2324 Disp8MemShift of AVX512VL forms.
2325 * i386-tbl.h: Re-generate.
2326
35fd2b2b
JW		 23272018-01-09 Jim Wilson <jimw@sifive.com>
2328
2329 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2330 then the hi_addr value is zero.
2331
91d8b670
JG		 23322018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2333
2334 * arm-dis.c (arm_opcodes): Add csdb.
2335 (thumb32_opcodes): Add csdb.
2336
be2e7d95
JG		 23372018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2338
2339 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2340 * aarch64-asm-2.c: Regenerate.
2341 * aarch64-dis-2.c: Regenerate.
2342 * aarch64-opc-2.c: Regenerate.
2343
704a705d
L		 23442018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2345
2346 PR gas/22681
2347 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2348 Remove AVX512 vmovd with 64-bit operands.
2349 * i386-tbl.h: Regenerated.
2350
35eeb78f
JW		 23512018-01-05 Jim Wilson <jimw@sifive.com>
2352
2353 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2354 jalr.
2355
219d1afa
AM		 23562018-01-03 Alan Modra <amodra@gmail.com>
2357
2358 Update year range in copyright notice of all files.
2359
1508bbf5
JB		 23602018-01-02 Jan Beulich <jbeulich@suse.com>
2361
2362 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2363 and OPERAND_TYPE_REGZMM entries.
2364
1e563868 2365For older changes see ChangeLog-2017
3499769a 2366\f
1e563868 2367Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2368
2369Copying and distribution of this file, with or without modification,
2370are permitted in any medium without royalty provided the copyright
2371notice and this notice are preserved.
2372
2373Local Variables:
2374mode: change-log
2375left-margin: 8
2376fill-column: 74
2377version-control: never
2378End:
GDB Binutils - Deliverables
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