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Merge forward-search/reverse-search, use gdb::def_vector, remove limit
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f50fabe4
JW		 12018-12-07 Jim Wilson <jimw@sifive.com>
2
3 PR gas/23956
4 * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
5
7fb45a68
AB		 62018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
7
8 * configure.ac (enable-cgen-maint): Support passing path to cgen
9 source tree.
10 * configure: Regenerate.
11
884b49e3
AB		 122018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
13
14 * disassembler.c (disassemble_init_for_target): Add RISC-V
15 initialisation.
16 * riscv-dis.c (riscv_symbol_is_valid): New function.
17
1080bf78
JW		 182018-12-03 Kito Cheng <kito@andestech.com>
19
20 * riscv-opc.c: Change the type of xlen, because type of
21 xlen_requirement changed.
22
57b64c41
EB		 232018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
24
25 PR 23193
26 PR 19721
27 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
28 encoding as MOV if the shift operation is a left shift of zero.
29
12951a2f
JW		 302018-11-29 Jim Wilson <jimw@sifive.com>
31
32 * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
33 (c.unimp): New.
34
4765cd61
JW		 352018-11-27 Jim Wilson <jimw@sifive.com>
36
37 * riscv-opc.c (ciw): Fix whitespace to align columns.
38 (ca): New.
39
27f42a4d
JD		 402018-11-21 John Darrington <john@darrington.wattle.id.au>
41
42 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
43 if the postbyte matches the appropriate pattern.
44
97b3f392
FT		 452018-11-13 Francois H. Theron <francois.theron@netronome.com>
46
47 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
48
3a0f69be
SD		 492018-11-12 Sudakshina Das <sudi.das@arm.com>
50
51 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
52 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
53 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
54 CIGDVAC and GZVA.
55 (aarch64_sys_ins_reg_supported_p): New check for above.
56
70f3d23a
SD		 572018-11-12 Sudakshina Das <sudi.das@arm.com>
58
59 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
60 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
61 RGSR_EL1 and GCR_EL1.
62 (aarch64_sys_reg_supported_p): New check for above.
63 (aarch64_pstatefields): New entry for TCO.
64 (aarch64_pstatefield_supported_p): New check for above.
65
503ba600
SD		 662018-11-12 Sudakshina Das <sudi.das@arm.com>
67
68 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
69 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
70 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
71 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
72 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
73 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
74 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
75 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
76 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
77 * aarch64-asm-2.c: Regenerated.
78 * aarch64-dis-2.c: Regenerated.
79 * aarch64-opc-2.c: Regenerated.
80
e6025b54
SD		 812018-11-12 Sudakshina Das <sudi.das@arm.com>
82
83 * aarch64-tbl.h (QL_LDG): New.
84 (aarch64_opcode_table): Add ldg.
85 * aarch64-asm-2.c: Regenerated.
86 * aarch64-dis-2.c: Regenerated.
87 * aarch64-opc-2.c: Regenerated.
88
fb3265b3
SD		 892018-11-12 Sudakshina Das <sudi.das@arm.com>
90
91 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
92 for AARCH64_OPND_QLF_imm_tag.
93 (operand_general_constraint_met_p): Add case for
94 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
95 (aarch64_print_operand): Likewise.
96 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
97 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
98 for both offset and pre/post indexed versions.
99 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
100 * aarch64-asm-2.c: Regenerated.
101 * aarch64-dis-2.c: Regenerated.
102 * aarch64-opc-2.c: Regenerated.
103
b731bc3b
SD		 1042018-11-12 Sudakshina Das <sudi.das@arm.com>
105
106 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
107 * aarch64-asm-2.c: Regenerated.
108 * aarch64-dis-2.c: Regenerated.
109 * aarch64-opc-2.c: Regenerated.
110
193614f2
SD		 1112018-11-12 Sudakshina Das <sudi.das@arm.com>
112
113 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
114 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
115 * aarch64-opc.c (fields): Add entry for imm4_3.
116 (operand_general_constraint_met_p): Add cases for
117 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
118 (aarch64_print_operand): Likewise.
119 * aarch64-tbl.h (QL_ADDG): New.
120 (aarch64_opcode_table): Add addg, subg, irg and gmi.
121 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
122 * aarch64-asm.c (aarch64_ins_imm): Add case for
123 operand_need_shift_by_four.
124 * aarch64-asm-2.c: Regenerated.
125 * aarch64-dis-2.c: Regenerated.
126 * aarch64-opc-2.c: Regenerated.
127
73b605ec
SD		 1282018-11-12 Sudakshina Das <sudi.das@arm.com>
129
130 * aarch64-tbl.h (aarch64_feature_memtag): New.
131 (MEMTAG, MEMTAG_INSN): New.
132
0632eeea
SD		 1332018-11-06 Sudakshina Das <sudi.das@arm.com>
134
135 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
136 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
137
71553718
AM		 1382018-11-06 Alan Modra <amodra@gmail.com>
139
140 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
141 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
142 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
143 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
144 Don't return zero on error, insert mask bits instead.
145 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
146 (insert_sh6, extract_sh6): Delete dead code.
147 (insert_sprbat, insert_sprg): Use unsigned comparisions.
148 (powerpc_operands <OIMM>): Set shift count rather than using
149 PPC_OPSHIFT_INV.
150 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
151
4dd4e639
JB		 1522018-11-06 Jan Beulich <jbeulich@suse.com>
153
154 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
155 vpbroadcast{d,q} with GPR operand.
156
9819647a
JB		 1572018-11-06 Jan Beulich <jbeulich@suse.com>
158
159 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
160 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
161 cases up one level in the hierarchy.
162
58a211d2
JB		 1632018-11-06 Jan Beulich <jbeulich@suse.com>
164
165 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
166 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
167 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
168 into MOD_VEX_0F93_P_3_LEN_0.
169 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
170 operand cases up one level in the hierarchy.
171
b50c9f31
JB		 1722018-11-06 Jan Beulich <jbeulich@suse.com>
173
174 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
175 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
176 EVEX_W_0F3A22_P_2): Delete.
177 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
178 entries up one level in the hierarchy.
179 (OP_E_memory): Handle dq_mode when determining Disp8 shift
180 value.
181 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
182 entries up one level in the hierarchy.
183 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
184 VexWIG for AVX flavors.
185 * i386-tbl.h: Re-generate.
186
931d03b7
JB		 1872018-11-06 Jan Beulich <jbeulich@suse.com>
188
189 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
190 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
191 vcvtusi2ss, kmovd): Drop VexW=1.
192 * i386-tbl.h: Re-generate.
193
fd71a375
JB		 1942018-11-06 Jan Beulich <jbeulich@suse.com>
195
196 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
197 EVex512, EVexLIG, EVexDYN): New.
198 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
199 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
200 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
201 of EVex=4 (aka EVexLIG).
202 * i386-tbl.h: Re-generate.
203
563c7eef
JB		 2042018-11-06 Jan Beulich <jbeulich@suse.com>
205
206 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
207 (vpmaxub): Re-order attributes on AVX512BW flavor.
208 * i386-tbl.h: Re-generate.
209
0aaca1d9
JB		 2102018-11-06 Jan Beulich <jbeulich@suse.com>
211
212 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
213 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
214 Vex=1 on AVX / AVX2 flavors.
215 (vpmaxub): Re-order attributes on AVX512BW flavor.
216 * i386-tbl.h: Re-generate.
217
bbae6b11
JB		 2182018-11-06 Jan Beulich <jbeulich@suse.com>
219
220 * i386-opc.tbl (VexW0, VexW1): New.
221 (vphadd*, vphsub*): Use VexW0 on XOP variants.
222 * i386-tbl.h: Re-generate.
223
192c2bfb
JD		 2242018-10-22 John Darrington <john@darrington.wattle.id.au>
225
226 * s12z-dis.c (decode_possible_symbol): Add fallback case.
227 (rel_15_7): Likewise.
228
0b347048
TC		 2292018-10-19 Tamar Christina <tamar.christina@arm.com>
230
231 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
232 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
233 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
234
66e6f0b7
MM		 2352018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
236
237 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
238 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
239
673fe0f0
JB		 2402018-10-10 Jan Beulich <jbeulich@suse.com>
241
242 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
243 Size64. Add Size.
244 * i386-opc.h (Size16, Size32, Size64): Delete.
245 (Size): New.
246 (SIZE16, SIZE32, SIZE64): Define.
247 (struct i386_opcode_modifier): Drop size16, size32, and size64.
248 Add size.
249 * i386-opc.tbl (Size16, Size32, Size64): Define.
250 * i386-tbl.h: Re-generate.
251
104fefee
SD		 2522018-10-09 Sudakshina Das <sudi.das@arm.com>
253
254 * aarch64-opc.c (operand_general_constraint_met_p): Add
255 SSBS in the check for one-bit immediate.
256 (aarch64_sys_regs): New entry for SSBS.
257 (aarch64_sys_reg_supported_p): New check for above.
258 (aarch64_pstatefields): New entry for SSBS.
259 (aarch64_pstatefield_supported_p): New check for above.
260
a97330e7
SD		 2612018-10-09 Sudakshina Das <sudi.das@arm.com>
262
263 * aarch64-opc.c (aarch64_sys_regs): New entries for
264 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
265 (aarch64_sys_reg_supported_p): New checks for above.
266
ff605452
SD		 2672018-10-09 Sudakshina Das <sudi.das@arm.com>
268
269 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
270 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
271 with the hint immediate.
272 * aarch64-opc.c (aarch64_hint_options): New entries for
273 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
274 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
275 while checking for HINT_OPD_F_NOPRINT flag.
276 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
277 extract value.
278 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
279 (aarch64_opcode_table): Add entry for BTI.
280 (AARCH64_OPERANDS): Add new description for BTI targets.
281 * aarch64-asm-2.c: Regenerate.
282 * aarch64-dis-2.c: Regenerate.
283 * aarch64-opc-2.c: Regenerate.
284
af4bcb4c
SD		 2852018-10-09 Sudakshina Das <sudi.das@arm.com>
286
287 * aarch64-opc.c (aarch64_sys_regs): New entries for
288 rndr and rndrrs.
289 (aarch64_sys_reg_supported_p): New check for above.
290
3fd229a4
SD		 2912018-10-09 Sudakshina Das <sudi.das@arm.com>
292
293 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
294 (aarch64_sys_ins_reg_supported_p): New check for above.
295
2ac435d4
SD		 2962018-10-09 Sudakshina Das <sudi.das@arm.com>
297
298 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
299 AARCH64_OPND_SYSREG_SR.
300 * aarch64-opc.c (aarch64_print_operand): Likewise.
301 (aarch64_sys_regs_sr): Define table.
302 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
303 AARCH64_FEATURE_PREDRES.
304 * aarch64-tbl.h (aarch64_feature_predres): New.
305 (PREDRES, PREDRES_INSN): New.
306 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
307 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
308 * aarch64-asm-2.c: Regenerate.
309 * aarch64-dis-2.c: Regenerate.
310 * aarch64-opc-2.c: Regenerate.
311
68dfbb92
SD		 3122018-10-09 Sudakshina Das <sudi.das@arm.com>
313
314 * aarch64-tbl.h (aarch64_feature_sb): New.
315 (SB, SB_INSN): New.
316 (aarch64_opcode_table): Add entry for sb.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis-2.c: Regenerate.
319 * aarch64-opc-2.c: Regenerate.
320
13c60ad7
SD		 3212018-10-09 Sudakshina Das <sudi.das@arm.com>
322
323 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
324 (aarch64_feature_frintts): New.
325 (FLAGMANIP, FRINTTS): New.
326 (aarch64_opcode_table): Add entries for xaflag, axflag
327 and frint[32,64][x,z] instructions.
328 * aarch64-asm-2.c: Regenerate.
329 * aarch64-dis-2.c: Regenerate.
330 * aarch64-opc-2.c: Regenerate.
331
70d56181
SD		 3322018-10-09 Sudakshina Das <sudi.das@arm.com>
333
334 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
335 (ARMV8_5, V8_5_INSN): New.
336
780f601c
TC		 3372018-10-08 Tamar Christina <tamar.christina@arm.com>
338
339 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
340
a4e78aa5
L		 3412018-10-05 H.J. Lu <hongjiu.lu@intel.com>
342
343 * i386-dis.c (rm_table): Add enclv.
344 * i386-opc.tbl: Add enclv.
345 * i386-tbl.h: Regenerated.
346
7fadb25d
SD		 3472018-10-05 Sudakshina Das <sudi.das@arm.com>
348
349 * arm-dis.c (arm_opcodes): Add sb.
350 (thumb32_opcodes): Likewise.
351
07f5f4c6
RH		 3522018-10-05 Richard Henderson <rth@twiddle.net>
353 Stafford Horne <shorne@gmail.com>
354
355 * or1k-desc.c: Regenerate.
356 * or1k-desc.h: Regenerate.
357 * or1k-opc.c: Regenerate.
358 * or1k-opc.h: Regenerate.
359 * or1k-opinst.c: Regenerate.
360
c8e98e36
SH		 3612018-10-05 Richard Henderson <rth@twiddle.net>
362
363 * or1k-asm.c: Regenerated.
364 * or1k-desc.c: Regenerated.
365 * or1k-desc.h: Regenerated.
366 * or1k-dis.c: Regenerated.
367 * or1k-ibld.c: Regenerated.
368 * or1k-opc.c: Regenerated.
369 * or1k-opc.h: Regenerated.
370 * or1k-opinst.c: Regenerated.
371
1c4f3780
RH		 3722018-10-05 Richard Henderson <rth@twiddle.net>
373
374 * or1k-asm.c: Regenerate.
375
bde90be2
TC		 3762018-10-03 Tamar Christina <tamar.christina@arm.com>
377
378 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
379 * aarch64-dis.c (print_operands): Refactor to take notes.
380 (print_verifier_notes): New.
381 (print_aarch64_insn): Apply constraint verifier.
382 (print_insn_aarch64_word): Update call to print_aarch64_insn.
383 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
384
a68f4cd2
TC		 3852018-10-03 Tamar Christina <tamar.christina@arm.com>
386
387 * aarch64-opc.c (init_insn_block): New.
388 (verify_constraints, aarch64_is_destructive_by_operands): New.
389 * aarch64-opc.h (verify_constraints): New.
390
755b748f
TC		 3912018-10-03 Tamar Christina <tamar.christina@arm.com>
392
393 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
394 * aarch64-opc.c (verify_ldpsw): Update arguments.
395
1d482394
TC		 3962018-10-03 Tamar Christina <tamar.christina@arm.com>
397
398 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
399 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
400
7e84b55d
TC		 4012018-10-03 Tamar Christina <tamar.christina@arm.com>
402
403 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
404 * aarch64-dis.c (insn_sequence): New.
405
eae424ae
TC		 4062018-10-03 Tamar Christina <tamar.christina@arm.com>
407
408 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
409 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
410 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
411 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
412 constraints.
413 (_SVE_INSNC): New.
414 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
415 constraints.
416 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
417 F_SCAN flags.
418 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
419 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
420 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
421 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
422 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
423 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
424 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
425
64a336ac
PD		 4262018-10-02 Palmer Dabbelt <palmer@sifive.com>
427
428 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
429
6031ac35
SL		 4302018-09-23 Sandra Loosemore <sandra@codesourcery.com>
431
432 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
433 are used when extracting signed fields and converting them to
434 potentially 64-bit types.
435
f24ff6e9
SM		 4362018-09-21 Simon Marchi <simon.marchi@ericsson.com>
437
438 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
439 * Makefile.in: Re-generate.
440 * aclocal.m4: Re-generate.
441 * configure: Re-generate.
442 * configure.ac: Remove check for -Wno-missing-field-initializers.
443 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
444 (csky_v2_opcodes): Likewise.
445
53b6d6f5
MR		 4462018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
447
448 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
449
fbaf61ad
NC		 4502018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
451
452 * nds32-asm.c (operand_fields): Remove the unused fields.
453 (nds32_opcodes): Remove the unused instructions.
454 * nds32-dis.c (nds32_ex9_info): Removed.
455 (nds32_parse_opcode): Updated.
456 (print_insn_nds32): Likewise.
457 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
458 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
459 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
460 build_opcode_hash_table): New functions.
461 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
462 nds32_opcode_table): New.
463 (hw_ktabs): Declare it to a pointer rather than an array.
464 (build_hash_table): Removed.
465 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
466 SYN_ROPT and upadte HW_GPR and HW_INT.
467 * nds32-dis.c (keywords): Remove const.
468 (match_field): New function.
469 (nds32_parse_opcode): Updated.
470 * disassemble.c (disassemble_init_for_target):
471 Add disassemble_init_nds32.
472 * nds32-dis.c (eum map_type): New.
473 (nds32_private_data): Likewise.
474 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
475 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
476 (print_insn_nds32): Updated.
477 * nds32-asm.c (parse_aext_reg): Add new parameter.
478 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
479 are allowed to use.
480 All callers changed.
481 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
482 (operand_fields): Add new fields.
483 (nds32_opcodes): Add new instructions.
484 (keyword_aridxi_mx): New keyword.
485 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
486 and NASM_ATTR_ZOL.
487 (ALU2_1, ALU2_2, ALU2_3): New macros.
488 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
489
4e2b1898
JW		 4902018-09-17 Kito Cheng <kito@andestech.com>
491
492 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
493
04e2a182
L		 4942018-09-17 H.J. Lu <hongjiu.lu@intel.com>
495
496 PR gas/23670
497 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
498 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
499 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
500 (EVEX_LEN_0F7E_P_1): Likewise.
501 (EVEX_LEN_0F7E_P_2): Likewise.
502 (EVEX_LEN_0FD6_P_2): Likewise.
503 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
504 (EVEX_LEN_TABLE): Likewise.
505 (EVEX_LEN_0F6E_P_2): New enum.
506 (EVEX_LEN_0F7E_P_1): Likewise.
507 (EVEX_LEN_0F7E_P_2): Likewise.
508 (EVEX_LEN_0FD6_P_2): Likewise.
509 (evex_len_table): New.
510 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
511 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
512 * i386-tbl.h: Regenerated.
513
d5f787c2
L		 5142018-09-17 H.J. Lu <hongjiu.lu@intel.com>
515
516 PR gas/23665
517 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
518 VEX_LEN_0F7E_P_2 entries.
519 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
520 * i386-tbl.h: Regenerated.
521
ec6f095a
L		 5222018-09-17 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-dis.c (VZERO_Fixup): Removed.
525 (VZERO): Likewise.
526 (VEX_LEN_0F10_P_1): Likewise.
527 (VEX_LEN_0F10_P_3): Likewise.
528 (VEX_LEN_0F11_P_1): Likewise.
529 (VEX_LEN_0F11_P_3): Likewise.
530 (VEX_LEN_0F2E_P_0): Likewise.
531 (VEX_LEN_0F2E_P_2): Likewise.
532 (VEX_LEN_0F2F_P_0): Likewise.
533 (VEX_LEN_0F2F_P_2): Likewise.
534 (VEX_LEN_0F51_P_1): Likewise.
535 (VEX_LEN_0F51_P_3): Likewise.
536 (VEX_LEN_0F52_P_1): Likewise.
537 (VEX_LEN_0F53_P_1): Likewise.
538 (VEX_LEN_0F58_P_1): Likewise.
539 (VEX_LEN_0F58_P_3): Likewise.
540 (VEX_LEN_0F59_P_1): Likewise.
541 (VEX_LEN_0F59_P_3): Likewise.
542 (VEX_LEN_0F5A_P_1): Likewise.
543 (VEX_LEN_0F5A_P_3): Likewise.
544 (VEX_LEN_0F5C_P_1): Likewise.
545 (VEX_LEN_0F5C_P_3): Likewise.
546 (VEX_LEN_0F5D_P_1): Likewise.
547 (VEX_LEN_0F5D_P_3): Likewise.
548 (VEX_LEN_0F5E_P_1): Likewise.
549 (VEX_LEN_0F5E_P_3): Likewise.
550 (VEX_LEN_0F5F_P_1): Likewise.
551 (VEX_LEN_0F5F_P_3): Likewise.
552 (VEX_LEN_0FC2_P_1): Likewise.
553 (VEX_LEN_0FC2_P_3): Likewise.
554 (VEX_LEN_0F3A0A_P_2): Likewise.
555 (VEX_LEN_0F3A0B_P_2): Likewise.
556 (VEX_W_0F10_P_0): Likewise.
557 (VEX_W_0F10_P_1): Likewise.
558 (VEX_W_0F10_P_2): Likewise.
559 (VEX_W_0F10_P_3): Likewise.
560 (VEX_W_0F11_P_0): Likewise.
561 (VEX_W_0F11_P_1): Likewise.
562 (VEX_W_0F11_P_2): Likewise.
563 (VEX_W_0F11_P_3): Likewise.
564 (VEX_W_0F12_P_0_M_0): Likewise.
565 (VEX_W_0F12_P_0_M_1): Likewise.
566 (VEX_W_0F12_P_1): Likewise.
567 (VEX_W_0F12_P_2): Likewise.
568 (VEX_W_0F12_P_3): Likewise.
569 (VEX_W_0F13_M_0): Likewise.
570 (VEX_W_0F14): Likewise.
571 (VEX_W_0F15): Likewise.
572 (VEX_W_0F16_P_0_M_0): Likewise.
573 (VEX_W_0F16_P_0_M_1): Likewise.
574 (VEX_W_0F16_P_1): Likewise.
575 (VEX_W_0F16_P_2): Likewise.
576 (VEX_W_0F17_M_0): Likewise.
577 (VEX_W_0F28): Likewise.
578 (VEX_W_0F29): Likewise.
579 (VEX_W_0F2B_M_0): Likewise.
580 (VEX_W_0F2E_P_0): Likewise.
581 (VEX_W_0F2E_P_2): Likewise.
582 (VEX_W_0F2F_P_0): Likewise.
583 (VEX_W_0F2F_P_2): Likewise.
584 (VEX_W_0F50_M_0): Likewise.
585 (VEX_W_0F51_P_0): Likewise.
586 (VEX_W_0F51_P_1): Likewise.
587 (VEX_W_0F51_P_2): Likewise.
588 (VEX_W_0F51_P_3): Likewise.
589 (VEX_W_0F52_P_0): Likewise.
590 (VEX_W_0F52_P_1): Likewise.
591 (VEX_W_0F53_P_0): Likewise.
592 (VEX_W_0F53_P_1): Likewise.
593 (VEX_W_0F58_P_0): Likewise.
594 (VEX_W_0F58_P_1): Likewise.
595 (VEX_W_0F58_P_2): Likewise.
596 (VEX_W_0F58_P_3): Likewise.
597 (VEX_W_0F59_P_0): Likewise.
598 (VEX_W_0F59_P_1): Likewise.
599 (VEX_W_0F59_P_2): Likewise.
600 (VEX_W_0F59_P_3): Likewise.
601 (VEX_W_0F5A_P_0): Likewise.
602 (VEX_W_0F5A_P_1): Likewise.
603 (VEX_W_0F5A_P_3): Likewise.
604 (VEX_W_0F5B_P_0): Likewise.
605 (VEX_W_0F5B_P_1): Likewise.
606 (VEX_W_0F5B_P_2): Likewise.
607 (VEX_W_0F5C_P_0): Likewise.
608 (VEX_W_0F5C_P_1): Likewise.
609 (VEX_W_0F5C_P_2): Likewise.
610 (VEX_W_0F5C_P_3): Likewise.
611 (VEX_W_0F5D_P_0): Likewise.
612 (VEX_W_0F5D_P_1): Likewise.
613 (VEX_W_0F5D_P_2): Likewise.
614 (VEX_W_0F5D_P_3): Likewise.
615 (VEX_W_0F5E_P_0): Likewise.
616 (VEX_W_0F5E_P_1): Likewise.
617 (VEX_W_0F5E_P_2): Likewise.
618 (VEX_W_0F5E_P_3): Likewise.
619 (VEX_W_0F5F_P_0): Likewise.
620 (VEX_W_0F5F_P_1): Likewise.
621 (VEX_W_0F5F_P_2): Likewise.
622 (VEX_W_0F5F_P_3): Likewise.
623 (VEX_W_0F60_P_2): Likewise.
624 (VEX_W_0F61_P_2): Likewise.
625 (VEX_W_0F62_P_2): Likewise.
626 (VEX_W_0F63_P_2): Likewise.
627 (VEX_W_0F64_P_2): Likewise.
628 (VEX_W_0F65_P_2): Likewise.
629 (VEX_W_0F66_P_2): Likewise.
630 (VEX_W_0F67_P_2): Likewise.
631 (VEX_W_0F68_P_2): Likewise.
632 (VEX_W_0F69_P_2): Likewise.
633 (VEX_W_0F6A_P_2): Likewise.
634 (VEX_W_0F6B_P_2): Likewise.
635 (VEX_W_0F6C_P_2): Likewise.
636 (VEX_W_0F6D_P_2): Likewise.
637 (VEX_W_0F6F_P_1): Likewise.
638 (VEX_W_0F6F_P_2): Likewise.
639 (VEX_W_0F70_P_1): Likewise.
640 (VEX_W_0F70_P_2): Likewise.
641 (VEX_W_0F70_P_3): Likewise.
642 (VEX_W_0F71_R_2_P_2): Likewise.
643 (VEX_W_0F71_R_4_P_2): Likewise.
644 (VEX_W_0F71_R_6_P_2): Likewise.
645 (VEX_W_0F72_R_2_P_2): Likewise.
646 (VEX_W_0F72_R_4_P_2): Likewise.
647 (VEX_W_0F72_R_6_P_2): Likewise.
648 (VEX_W_0F73_R_2_P_2): Likewise.
649 (VEX_W_0F73_R_3_P_2): Likewise.
650 (VEX_W_0F73_R_6_P_2): Likewise.
651 (VEX_W_0F73_R_7_P_2): Likewise.
652 (VEX_W_0F74_P_2): Likewise.
653 (VEX_W_0F75_P_2): Likewise.
654 (VEX_W_0F76_P_2): Likewise.
655 (VEX_W_0F77_P_0): Likewise.
656 (VEX_W_0F7C_P_2): Likewise.
657 (VEX_W_0F7C_P_3): Likewise.
658 (VEX_W_0F7D_P_2): Likewise.
659 (VEX_W_0F7D_P_3): Likewise.
660 (VEX_W_0F7E_P_1): Likewise.
661 (VEX_W_0F7F_P_1): Likewise.
662 (VEX_W_0F7F_P_2): Likewise.
663 (VEX_W_0FAE_R_2_M_0): Likewise.
664 (VEX_W_0FAE_R_3_M_0): Likewise.
665 (VEX_W_0FC2_P_0): Likewise.
666 (VEX_W_0FC2_P_1): Likewise.
667 (VEX_W_0FC2_P_2): Likewise.
668 (VEX_W_0FC2_P_3): Likewise.
669 (VEX_W_0FD0_P_2): Likewise.
670 (VEX_W_0FD0_P_3): Likewise.
671 (VEX_W_0FD1_P_2): Likewise.
672 (VEX_W_0FD2_P_2): Likewise.
673 (VEX_W_0FD3_P_2): Likewise.
674 (VEX_W_0FD4_P_2): Likewise.
675 (VEX_W_0FD5_P_2): Likewise.
676 (VEX_W_0FD6_P_2): Likewise.
677 (VEX_W_0FD7_P_2_M_1): Likewise.
678 (VEX_W_0FD8_P_2): Likewise.
679 (VEX_W_0FD9_P_2): Likewise.
680 (VEX_W_0FDA_P_2): Likewise.
681 (VEX_W_0FDB_P_2): Likewise.
682 (VEX_W_0FDC_P_2): Likewise.
683 (VEX_W_0FDD_P_2): Likewise.
684 (VEX_W_0FDE_P_2): Likewise.
685 (VEX_W_0FDF_P_2): Likewise.
686 (VEX_W_0FE0_P_2): Likewise.
687 (VEX_W_0FE1_P_2): Likewise.
688 (VEX_W_0FE2_P_2): Likewise.
689 (VEX_W_0FE3_P_2): Likewise.
690 (VEX_W_0FE4_P_2): Likewise.
691 (VEX_W_0FE5_P_2): Likewise.
692 (VEX_W_0FE6_P_1): Likewise.
693 (VEX_W_0FE6_P_2): Likewise.
694 (VEX_W_0FE6_P_3): Likewise.
695 (VEX_W_0FE7_P_2_M_0): Likewise.
696 (VEX_W_0FE8_P_2): Likewise.
697 (VEX_W_0FE9_P_2): Likewise.
698 (VEX_W_0FEA_P_2): Likewise.
699 (VEX_W_0FEB_P_2): Likewise.
700 (VEX_W_0FEC_P_2): Likewise.
701 (VEX_W_0FED_P_2): Likewise.
702 (VEX_W_0FEE_P_2): Likewise.
703 (VEX_W_0FEF_P_2): Likewise.
704 (VEX_W_0FF0_P_3_M_0): Likewise.
705 (VEX_W_0FF1_P_2): Likewise.
706 (VEX_W_0FF2_P_2): Likewise.
707 (VEX_W_0FF3_P_2): Likewise.
708 (VEX_W_0FF4_P_2): Likewise.
709 (VEX_W_0FF5_P_2): Likewise.
710 (VEX_W_0FF6_P_2): Likewise.
711 (VEX_W_0FF7_P_2): Likewise.
712 (VEX_W_0FF8_P_2): Likewise.
713 (VEX_W_0FF9_P_2): Likewise.
714 (VEX_W_0FFA_P_2): Likewise.
715 (VEX_W_0FFB_P_2): Likewise.
716 (VEX_W_0FFC_P_2): Likewise.
717 (VEX_W_0FFD_P_2): Likewise.
718 (VEX_W_0FFE_P_2): Likewise.
719 (VEX_W_0F3800_P_2): Likewise.
720 (VEX_W_0F3801_P_2): Likewise.
721 (VEX_W_0F3802_P_2): Likewise.
722 (VEX_W_0F3803_P_2): Likewise.
723 (VEX_W_0F3804_P_2): Likewise.
724 (VEX_W_0F3805_P_2): Likewise.
725 (VEX_W_0F3806_P_2): Likewise.
726 (VEX_W_0F3807_P_2): Likewise.
727 (VEX_W_0F3808_P_2): Likewise.
728 (VEX_W_0F3809_P_2): Likewise.
729 (VEX_W_0F380A_P_2): Likewise.
730 (VEX_W_0F380B_P_2): Likewise.
731 (VEX_W_0F3817_P_2): Likewise.
732 (VEX_W_0F381C_P_2): Likewise.
733 (VEX_W_0F381D_P_2): Likewise.
734 (VEX_W_0F381E_P_2): Likewise.
735 (VEX_W_0F3820_P_2): Likewise.
736 (VEX_W_0F3821_P_2): Likewise.
737 (VEX_W_0F3822_P_2): Likewise.
738 (VEX_W_0F3823_P_2): Likewise.
739 (VEX_W_0F3824_P_2): Likewise.
740 (VEX_W_0F3825_P_2): Likewise.
741 (VEX_W_0F3828_P_2): Likewise.
742 (VEX_W_0F3829_P_2): Likewise.
743 (VEX_W_0F382A_P_2_M_0): Likewise.
744 (VEX_W_0F382B_P_2): Likewise.
745 (VEX_W_0F3830_P_2): Likewise.
746 (VEX_W_0F3831_P_2): Likewise.
747 (VEX_W_0F3832_P_2): Likewise.
748 (VEX_W_0F3833_P_2): Likewise.
749 (VEX_W_0F3834_P_2): Likewise.
750 (VEX_W_0F3835_P_2): Likewise.
751 (VEX_W_0F3837_P_2): Likewise.
752 (VEX_W_0F3838_P_2): Likewise.
753 (VEX_W_0F3839_P_2): Likewise.
754 (VEX_W_0F383A_P_2): Likewise.
755 (VEX_W_0F383B_P_2): Likewise.
756 (VEX_W_0F383C_P_2): Likewise.
757 (VEX_W_0F383D_P_2): Likewise.
758 (VEX_W_0F383E_P_2): Likewise.
759 (VEX_W_0F383F_P_2): Likewise.
760 (VEX_W_0F3840_P_2): Likewise.
761 (VEX_W_0F3841_P_2): Likewise.
762 (VEX_W_0F38DB_P_2): Likewise.
763 (VEX_W_0F3A08_P_2): Likewise.
764 (VEX_W_0F3A09_P_2): Likewise.
765 (VEX_W_0F3A0A_P_2): Likewise.
766 (VEX_W_0F3A0B_P_2): Likewise.
767 (VEX_W_0F3A0C_P_2): Likewise.
768 (VEX_W_0F3A0D_P_2): Likewise.
769 (VEX_W_0F3A0E_P_2): Likewise.
770 (VEX_W_0F3A0F_P_2): Likewise.
771 (VEX_W_0F3A21_P_2): Likewise.
772 (VEX_W_0F3A40_P_2): Likewise.
773 (VEX_W_0F3A41_P_2): Likewise.
774 (VEX_W_0F3A42_P_2): Likewise.
775 (VEX_W_0F3A62_P_2): Likewise.
776 (VEX_W_0F3A63_P_2): Likewise.
777 (VEX_W_0F3ADF_P_2): Likewise.
778 (VEX_LEN_0F77_P_0): New.
779 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
780 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
781 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
782 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
783 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
784 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
785 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
786 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
787 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
788 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
789 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
790 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
791 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
792 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
793 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
794 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
795 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
796 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
797 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
798 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
799 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
800 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
801 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
802 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
803 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
804 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
805 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
806 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
807 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
808 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
809 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
810 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
811 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
812 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
813 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
814 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
815 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
816 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
817 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
818 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
819 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
820 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
821 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
822 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
823 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
824 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
825 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
826 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
827 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
828 (vex_table): Update VEX 0F28 and 0F29 entries.
829 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
830 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
831 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
832 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
833 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
834 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
835 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
836 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
837 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
838 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
839 VEX_LEN_0F3A0B_P_2 entries.
840 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
841 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
842 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
843 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
844 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
845 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
846 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
847 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
848 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
849 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
850 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
851 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
852 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
853 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
854 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
855 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
856 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
857 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
858 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
859 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
860 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
861 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
862 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
863 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
864 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
865 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
866 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
867 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
868 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
869 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
870 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
871 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
872 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
873 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
874 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
875 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
876 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
877 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
878 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
879 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
880 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
881 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
882 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
883 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
884 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
885 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
886 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
887 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
888 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
889 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
890 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
891 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
892 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
893 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
894 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
895 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
896 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
897 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
898 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
899 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
900 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
901 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
902 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
903 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
904 VEX_W_0F3ADF_P_2 entries.
905 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
906 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
907 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
908
6fa52824
L		 9092018-09-17 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-opc.tbl (VexWIG): New.
912 Replace VexW=3 with VexWIG.
913
db4cc665
L		 9142018-09-15 H.J. Lu <hongjiu.lu@intel.com>
915
916 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
917 * i386-tbl.h: Regenerated.
918
3c374143
L		 9192018-09-15 H.J. Lu <hongjiu.lu@intel.com>
920
921 PR gas/23665
922 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
923 VEX_LEN_0FD6_P_2 entries.
924 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
925 * i386-tbl.h: Regenerated.
926
6865c043
L		 9272018-09-14 H.J. Lu <hongjiu.lu@intel.com>
928
929 PR gas/23642
930 * i386-opc.h (VEXWIG): New.
931 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
932 * i386-tbl.h: Regenerated.
933
70df6fc9
L		 9342018-09-14 H.J. Lu <hongjiu.lu@intel.com>
935
936 PR binutils/23655
937 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
938 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
939 * i386-dis.c (EXxEVexR64): New.
940 (evex_rounding_64_mode): Likewise.
941 (OP_Rounding): Handle evex_rounding_64_mode.
942
d20dee9e
L		 9432018-09-14 H.J. Lu <hongjiu.lu@intel.com>
944
945 PR binutils/23655
946 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
947 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
948 * i386-dis.c (Edqa): New.
949 (dqa_mode): Likewise.
950 (intel_operand_size): Handle dqa_mode as m_mode.
951 (OP_E_register): Handle dqa_mode as dq_mode.
952 (OP_E_memory): Set shift for dqa_mode based on address_mode.
953
5074ad8a
L		 9542018-09-14 H.J. Lu <hongjiu.lu@intel.com>
955
956 * i386-dis.c (OP_E_memory): Reformat.
957
556059dd
JB		 9582018-09-14 Jan Beulich <jbeulich@suse.com>
959
960 * i386-opc.tbl (crc32): Fold byte and word forms.
961 * i386-tbl.h: Re-generate.
962
41d1ab6a
L		 9632018-09-13 H.J. Lu <hongjiu.lu@intel.com>
964
965 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
966 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
967 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
968 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
969 * i386-tbl.h: Regenerated.
970
57f6375e
JB		 9712018-09-13 Jan Beulich <jbeulich@suse.com>
972
973 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
974 meaningless.
975 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
976 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
977 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
978 * i386-tbl.h: Re-generate.
979
2589a7e5
JB		 9802018-09-13 Jan Beulich <jbeulich@suse.com>
981
982 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
983 AVX512_4VNNIW insns.
984 * i386-tbl.h: Re-generate.
985
a760eb41
JB		 9862018-09-13 Jan Beulich <jbeulich@suse.com>
987
988 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
989 meaningless.
990 * i386-tbl.h: Re-generate.
991
e9042658
JB		 9922018-09-13 Jan Beulich <jbeulich@suse.com>
993
994 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
995 meaningless.
996 * i386-tbl.h: Re-generate.
997
9caa306f
JB		 9982018-09-13 Jan Beulich <jbeulich@suse.com>
999
1000 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
1001 meaningless.
1002 * i386-tbl.h: Re-generate.
1003
fb6ce599
JB		 10042018-09-13 Jan Beulich <jbeulich@suse.com>
1005
1006 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
1007 meaningless.
1008 * i386-tbl.h: Re-generate.
1009
6a8da886
JB		 10102018-09-13 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
1013 meaningless.
1014 * i386-tbl.h: Re-generate.
1015
c7f27919
JB		 10162018-09-13 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
1019 * i386-tbl.h: Re-generate.
1020
0f407ee9
JB		 10212018-09-13 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
1024 * i386-tbl.h: Re-generate.
1025
2fbbbee5
JB		 10262018-09-13 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1029 meaningless.
1030 * i386-tbl.h: Re-generate.
1031
2b02b9a2
JB		 10322018-09-13 Jan Beulich <jbeulich@suse.com>
1033
1034 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1035 meaningless.
1036 * i386-tbl.h: Re-generate.
1037
963c68aa
JB		 10382018-09-13 Jan Beulich <jbeulich@suse.com>
1039
1040 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1041 * i386-tbl.h: Re-generate.
1042
64e025c3
JB		 10432018-09-13 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1046 * i386-tbl.h: Re-generate.
1047
47603f88
JB		 10482018-09-13 Jan Beulich <jbeulich@suse.com>
1049
1050 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1051 * i386-tbl.h: Re-generate.
1052
0001cfd0
JB		 10532018-09-13 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1056 meaningless.
1057 * i386-tbl.h: Re-generate.
1058
be4b452e
JB		 10592018-09-13 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1062 meaningless.
1063 * i386-tbl.h: Re-generate.
1064
d09a1394
JB		 10652018-09-13 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1068 meaningless.
1069 * i386-tbl.h: Re-generate.
1070
07599e13
JB		 10712018-09-13 Jan Beulich <jbeulich@suse.com>
1072
1073 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1074 * i386-tbl.h: Re-generate.
1075
1ee3e487
JB		 10762018-09-13 Jan Beulich <jbeulich@suse.com>
1077
1078 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1079 * i386-tbl.h: Re-generate.
1080
a5f580e5
JB		 10812018-09-13 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1084 * i386-tbl.h: Re-generate.
1085
49d5d12d
JB		 10862018-09-13 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1089 (vpbroadcastw, rdpid): Drop NoRex64.
1090 * i386-tbl.h: Re-generate.
1091
f5eb1d70
JB		 10922018-09-13 Jan Beulich <jbeulich@suse.com>
1093
1094 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1095 store templates, adding D.
1096 * i386-tbl.h: Re-generate.
1097
dbbc8b7e
JB		 10982018-09-13 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1101 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1102 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1103 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1104 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1105 Fold load and store templates where possible, adding D. Drop
1106 IgnoreSize where it was pointlessly present. Drop redundant
1107 *word.
1108 * i386-tbl.h: Re-generate.
1109
d276ec69
JB		 11102018-09-13 Jan Beulich <jbeulich@suse.com>
1111
1112 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1113 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1114 (intel_operand_size): Handle v_bndmk_mode.
1115 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1116
9da4dfd6
JD		 11172018-09-08 John Darrington <john@darrington.wattle.id.au>
1118
1119 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1120
be192bc2
JW		 11212018-08-31 Kito Cheng <kito@andestech.com>
1122
1123 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1124 compressed floating point instructions.
1125
43135d3b
JW		 11262018-08-30 Kito Cheng <kito@andestech.com>
1127
1128 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1129 riscv_opcode.xlen_requirement.
1130 * riscv-opc.c (riscv_opcodes): Update for struct change.
1131
df28970f
MA		 11322018-08-29 Martin Aberg <maberg@gaisler.com>
1133
1134 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1135 psr (PWRPSR) instruction.
1136
9108bc33
CX		 11372018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1138
1139 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1140
bd782c07
CX		 11412018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1142
1143 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1144
ac8cb70f
CX		 11452018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1146
1147 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1148 loongson3a as an alias of gs464 for compatibility.
1149 * mips-opc.c (mips_opcodes): Change Comments.
1150
a693765e
CX		 11512018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1152
1153 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1154 option.
1155 (print_mips_disassembler_options): Document -M loongson-ext.
1156 * mips-opc.c (LEXT2): New macro.
1157 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1158
bdc6c06e
CX		 11592018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1160
1161 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1162 descriptors.
1163 (parse_mips_ase_option): Handle -M loongson-ext option.
1164 (print_mips_disassembler_options): Document -M loongson-ext.
1165 * mips-opc.c (IL3A): Delete.
1166 * mips-opc.c (LEXT): New macro.
1167 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1168 instructions.
1169
716c08de
CX		 11702018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1171
1172 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1173 descriptors.
1174 (parse_mips_ase_option): Handle -M loongson-cam option.
1175 (print_mips_disassembler_options): Document -M loongson-cam.
1176 * mips-opc.c (LCAM): New macro.
1177 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1178 instructions.
1179
9cf7e568
AM		 11802018-08-21 Alan Modra <amodra@gmail.com>
1181
1182 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1183 (skip_optional_operands): Count optional operands, and update
1184 ppc_optional_operand_value call.
1185 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1186 (extract_vlensi): Likewise.
1187 (extract_fxm): Return default value for missing optional operand.
1188 (extract_ls, extract_raq, extract_tbr): Likewise.
1189 (insert_sxl, extract_sxl): New functions.
1190 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1191 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1192 flag and extra entry.
1193 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1194 extract_sxl.
1195
d203b41a 11962018-08-20 Alan Modra <amodra@gmail.com>
f4107842 1197
d203b41a 1198 * sh-opc.h (MASK): Simplify.
f4107842 1199
08a8fe2f 12002018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 1201
d203b41a
AM		 1202 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1203 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 1204 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 1205
08a8fe2f 12062018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 1207
1208 * s12z.h: Delete.
7ba3ba91 1209
1bc60e56
L		 12102018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1211
1212 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1213 address with the addr32 prefix and without base nor index
1214 registers.
1215
d871f3f4
L		 12162018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1217
1218 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1219 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1220 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1221 (cpu_flags): Add CpuCMOV and CpuFXSR.
1222 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1223 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1224 * i386-init.h: Regenerated.
1225 * i386-tbl.h: Likewise.
1226
b6523c37 12272018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1228
1229 * arc-regs.h: Update auxiliary registers.
1230
e968fc9b
JB		 12312018-08-06 Jan Beulich <jbeulich@suse.com>
1232
1233 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1234 (RegIP, RegIZ): Define.
1235 * i386-reg.tbl: Adjust comments.
1236 (rip): Use Qword instead of BaseIndex. Use RegIP.
1237 (eip): Use Dword instead of BaseIndex. Use RegIP.
1238 (riz): Add Qword. Use RegIZ.
1239 (eiz): Add Dword. Use RegIZ.
1240 * i386-tbl.h: Re-generate.
1241
dbf8be89
JB		 12422018-08-03 Jan Beulich <jbeulich@suse.com>
1243
1244 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1245 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1246 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1247 * i386-tbl.h: Re-generate.
1248
c48dadc9
JB		 12492018-08-03 Jan Beulich <jbeulich@suse.com>
1250
1251 * i386-gen.c (operand_types): Remove Mem field.
1252 * i386-opc.h (union i386_operand_type): Remove mem field.
1253 * i386-init.h, i386-tbl.h: Re-generate.
1254
cb86a42a
AM		 12552018-08-01 Alan Modra <amodra@gmail.com>
1256
1257 * po/POTFILES.in: Regenerate.
1258
07cc0450
NC		 12592018-07-31 Nick Clifton <nickc@redhat.com>
1260
1261 * po/sv.po: Updated Swedish translation.
1262
1424ad86
JB		 12632018-07-31 Jan Beulich <jbeulich@suse.com>
1264
1265 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1266 * i386-init.h, i386-tbl.h: Re-generate.
1267
ae2387fe
JB		 12682018-07-31 Jan Beulich <jbeulich@suse.com>
1269
1270 * i386-opc.h (ZEROING_MASKING) Rename to ...
1271 (DYNAMIC_MASKING): ... this. Adjust comment.
1272 * i386-opc.tbl (MaskingMorZ): Define.
1273 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1274 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1275 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1276 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1277 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1278 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1279 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1280 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1281 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1282
6ff00b5e
JB		 12832018-07-31 Jan Beulich <jbeulich@suse.com>
1284
1285 * i386-opc.tbl: Use element rather than vector size for AVX512*
1286 scatter/gather insns.
1287 * i386-tbl.h: Re-generate.
1288
e951d5ca
JB		 12892018-07-31 Jan Beulich <jbeulich@suse.com>
1290
1291 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1292 (cpu_flags): Drop CpuVREX.
1293 * i386-opc.h (CpuVREX): Delete.
1294 (union i386_cpu_flags): Remove cpuvrex.
1295 * i386-init.h, i386-tbl.h: Re-generate.
1296
eb41b248
JW		 12972018-07-30 Jim Wilson <jimw@sifive.com>
1298
1299 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1300 fields.
1301 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1302
b8891f8d
AJ		 13032018-07-30 Andrew Jenner <andrew@codesourcery.com>
1304
1305 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1306 * Makefile.in: Regenerated.
1307 * configure.ac: Add C-SKY.
1308 * configure: Regenerated.
1309 * csky-dis.c: New file.
1310 * csky-opc.h: New file.
1311 * disassemble.c (ARCH_csky): Define.
1312 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1313 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1314
16065af1
AM		 13152018-07-27 Alan Modra <amodra@gmail.com>
1316
1317 * ppc-opc.c (insert_sprbat): Correct function parameter and
1318 return type.
1319 (extract_sprbat): Likewise, variable too.
1320
fa758a70
AC		 13212018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1322 Alan Modra <amodra@gmail.com>
1323
1324 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1325 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1326 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1327 support disjointed BAT.
1328 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1329 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1330 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1331
4a1b91ea
L		 13322018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1333 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1334
1335 * i386-gen.c (adjust_broadcast_modifier): New function.
1336 (process_i386_opcode_modifier): Add an argument for operands.
1337 Adjust the Broadcast value based on operands.
1338 (output_i386_opcode): Pass operand_types to
1339 process_i386_opcode_modifier.
1340 (process_i386_opcodes): Pass NULL as operands to
1341 process_i386_opcode_modifier.
1342 * i386-opc.h (BYTE_BROADCAST): New.
1343 (WORD_BROADCAST): Likewise.
1344 (DWORD_BROADCAST): Likewise.
1345 (QWORD_BROADCAST): Likewise.
1346 (i386_opcode_modifier): Expand broadcast to 3 bits.
1347 * i386-tbl.h: Regenerated.
1348
67ce483b
AM		 13492018-07-24 Alan Modra <amodra@gmail.com>
1350
1351 PR 23430
1352 * or1k-desc.h: Regenerate.
1353
4174bfff
JB		 13542018-07-24 Jan Beulich <jbeulich@suse.com>
1355
1356 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1357 vcvtusi2ss, and vcvtusi2sd.
1358 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1359 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1360 * i386-tbl.h: Re-generate.
1361
04e65276
CZ		 13622018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1363
1364 * arc-opc.c (extract_w6): Fix extending the sign.
1365
47e6f81c
CZ		 13662018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1367
1368 * arc-tbl.h (vewt): Allow it for ARC EM family.
1369
bb71536f
AM		 13702018-07-23 Alan Modra <amodra@gmail.com>
1371
1372 PR 23419
1373 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1374 opcode variants for mtspr/mfspr encodings.
1375
8095d2f7
CX		 13762018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1377 Maciej W. Rozycki <macro@mips.com>
1378
1379 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1380 loongson3a descriptors.
1381 (parse_mips_ase_option): Handle -M loongson-mmi option.
1382 (print_mips_disassembler_options): Document -M loongson-mmi.
1383 * mips-opc.c (LMMI): New macro.
1384 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1385 instructions.
1386
5f32791e
JB		 13872018-07-19 Jan Beulich <jbeulich@suse.com>
1388
1389 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1390 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1391 IgnoreSize and [XYZ]MMword where applicable.
1392 * i386-tbl.h: Re-generate.
1393
625cbd7a
JB		 13942018-07-19 Jan Beulich <jbeulich@suse.com>
1395
1396 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1397 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1398 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1399 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1400 * i386-tbl.h: Re-generate.
1401
86b15c32
JB		 14022018-07-19 Jan Beulich <jbeulich@suse.com>
1403
1404 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1405 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1406 VPCLMULQDQ templates into their respective AVX512VL counterparts
1407 where possible, using Disp8ShiftVL and CheckRegSize instead of
1408 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1409 * i386-tbl.h: Re-generate.
1410
cf769ed5
JB		 14112018-07-19 Jan Beulich <jbeulich@suse.com>
1412
1413 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1414 AVX512VL counterparts where possible, using Disp8ShiftVL and
1415 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1416 IgnoreSize) as appropriate.
1417 * i386-tbl.h: Re-generate.
1418
8282b7ad
JB		 14192018-07-19 Jan Beulich <jbeulich@suse.com>
1420
1421 * i386-opc.tbl: Fold AVX512BW templates into their respective
1422 AVX512VL counterparts where possible, using Disp8ShiftVL and
1423 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1424 IgnoreSize) as appropriate.
1425 * i386-tbl.h: Re-generate.
1426
755908cc
JB		 14272018-07-19 Jan Beulich <jbeulich@suse.com>
1428
1429 * i386-opc.tbl: Fold AVX512CD templates into their respective
1430 AVX512VL counterparts where possible, using Disp8ShiftVL and
1431 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1432 IgnoreSize) as appropriate.
1433 * i386-tbl.h: Re-generate.
1434
7091c612
JB		 14352018-07-19 Jan Beulich <jbeulich@suse.com>
1436
1437 * i386-opc.h (DISP8_SHIFT_VL): New.
1438 * i386-opc.tbl (Disp8ShiftVL): Define.
1439 (various): Fold AVX512VL templates into their respective
1440 AVX512F counterparts where possible, using Disp8ShiftVL and
1441 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1442 IgnoreSize) as appropriate.
1443 * i386-tbl.h: Re-generate.
1444
c30be56e
JB		 14452018-07-19 Jan Beulich <jbeulich@suse.com>
1446
1447 * Makefile.am: Change dependencies and rule for
1448 $(srcdir)/i386-init.h.
1449 * Makefile.in: Re-generate.
1450 * i386-gen.c (process_i386_opcodes): New local variable
1451 "marker". Drop opening of input file. Recognize marker and line
1452 number directives.
1453 * i386-opc.tbl (OPCODE_I386_H): Define.
1454 (i386-opc.h): Include it.
1455 (None): Undefine.
1456
11a322db
L		 14572018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1458
1459 PR gas/23418
1460 * i386-opc.h (Byte): Update comments.
1461 (Word): Likewise.
1462 (Dword): Likewise.
1463 (Fword): Likewise.
1464 (Qword): Likewise.
1465 (Tbyte): Likewise.
1466 (Xmmword): Likewise.
1467 (Ymmword): Likewise.
1468 (Zmmword): Likewise.
1469 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1470 vcvttps2uqq.
1471 * i386-tbl.h: Regenerated.
1472
cde3679e
NC		 14732018-07-12 Sudakshina Das <sudi.das@arm.com>
1474
1475 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1476 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1477 * aarch64-asm-2.c: Regenerate.
1478 * aarch64-dis-2.c: Regenerate.
1479 * aarch64-opc-2.c: Regenerate.
1480
45a28947
TC		 14812018-07-12 Tamar Christina <tamar.christina@arm.com>
1482
1483 PR binutils/23192
1484 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1485 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1486 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1487 sqdmulh, sqrdmulh): Use Em16.
1488
c597cc3d
SD		 14892018-07-11 Sudakshina Das <sudi.das@arm.com>
1490
1491 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1492 csdb together with them.
1493 (thumb32_opcodes): Likewise.
1494
a79eaed6
JB		 14952018-07-11 Jan Beulich <jbeulich@suse.com>
1496
1497 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1498 requiring 32-bit registers as operands 2 and 3. Improve
1499 comments.
1500 (mwait, mwaitx): Fold templates. Improve comments.
1501 OPERAND_TYPE_INOUTPORTREG.
1502 * i386-tbl.h: Re-generate.
1503
2fb5be8d
JB		 15042018-07-11 Jan Beulich <jbeulich@suse.com>
1505
1506 * i386-gen.c (operand_type_init): Remove
1507 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1508 OPERAND_TYPE_INOUTPORTREG.
1509 * i386-init.h: Re-generate.
1510
7f5cad30
JB		 15112018-07-11 Jan Beulich <jbeulich@suse.com>
1512
1513 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1514 (wrssq, wrussq): Add Qword.
1515 * i386-tbl.h: Re-generate.
1516
f0a85b07
JB		 15172018-07-11 Jan Beulich <jbeulich@suse.com>
1518
1519 * i386-opc.h: Rename OTMax to OTNum.
1520 (OTNumOfUints): Adjust calculation.
1521 (OTUnused): Directly alias to OTNum.
1522
9dcb0ba4
MR		 15232018-07-09 Maciej W. Rozycki <macro@mips.com>
1524
1525 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1526 `reg_xys'.
1527 (lea_reg_xys): Likewise.
1528 (print_insn_loop_primitive): Rename `reg' local variable to
1529 `reg_dxy'.
1530
f311ba7e
TC		 15312018-07-06 Tamar Christina <tamar.christina@arm.com>
1532
1533 PR binutils/23242
1534 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1535
cba05feb
TC		 15362018-07-06 Tamar Christina <tamar.christina@arm.com>
1537
1538 PR binutils/23369
1539 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1540 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1541
471b9d15
MR		 15422018-07-02 Maciej W. Rozycki <macro@mips.com>
1543
1544 PR tdep/8282
1545 * mips-dis.c (mips_option_arg_t): New enumeration.
1546 (mips_options): New variable.
1547 (disassembler_options_mips): New function.
1548 (print_mips_disassembler_options): Reimplement in terms of
1549 `disassembler_options_mips'.
1550 * arm-dis.c (disassembler_options_arm): Adapt to using the
1551 `disasm_options_and_args_t' structure.
1552 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1553 * s390-dis.c (disassembler_options_s390): Likewise.
1554
c0c468d5
TP		 15552018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1556
1557 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1558 expected result.
1559 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1560 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1561 * testsuite/ld-arm/tls-longplt.d: Likewise.
1562
369c9167
TC		 15632018-06-29 Tamar Christina <tamar.christina@arm.com>
1564
1565 PR binutils/23192
1566 * aarch64-asm-2.c: Regenerate.
1567 * aarch64-dis-2.c: Likewise.
1568 * aarch64-opc-2.c: Likewise.
1569 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1570 * aarch64-opc.c (operand_general_constraint_met_p,
1571 aarch64_print_operand): Likewise.
1572 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1573 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1574 fmlal2, fmlsl2.
1575 (AARCH64_OPERANDS): Add Em2.
1576
30aa1306
NC		 15772018-06-26 Nick Clifton <nickc@redhat.com>
1578
1579 * po/uk.po: Updated Ukranian translation.
1580 * po/de.po: Updated German translation.
1581 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1582
eca4b721
NC		 15832018-06-26 Nick Clifton <nickc@redhat.com>
1584
1585 * nfp-dis.c: Fix spelling mistake.
1586
71300e2c
NC		 15872018-06-24 Nick Clifton <nickc@redhat.com>
1588
1589 * configure: Regenerate.
1590 * po/opcodes.pot: Regenerate.
1591
719d8288
NC		 15922018-06-24 Nick Clifton <nickc@redhat.com>
1593
1594 2.31 branch created.
1595
514cd3a0
TC		 15962018-06-19 Tamar Christina <tamar.christina@arm.com>
1597
1598 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1599 * aarch64-asm-2.c: Regenerate.
1600 * aarch64-dis-2.c: Likewise.
1601
385e4d0f
MR		 16022018-06-21 Maciej W. Rozycki <macro@mips.com>
1603
1604 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1605 `-M ginv' option description.
1606
160d1b3d
SH		 16072018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1608
1609 PR gas/23305
1610 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1611 la and lla.
1612
d0ac1c44
SM		 16132018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1614
1615 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1616 * configure.ac: Remove AC_PREREQ.
1617 * Makefile.in: Re-generate.
1618 * aclocal.m4: Re-generate.
1619 * configure: Re-generate.
1620
6f20c942
FS		 16212018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1622
1623 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1624 mips64r6 descriptors.
1625 (parse_mips_ase_option): Handle -Mginv option.
1626 (print_mips_disassembler_options): Document -Mginv.
1627 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1628 (GINV): New macro.
1629 (mips_opcodes): Define ginvi and ginvt.
1630
730c3174
SE		 16312018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1632 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1633
1634 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1635 * mips-opc.c (CRC, CRC64): New macros.
1636 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1637 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1638 crc32cd for CRC64.
1639
cb366992
EB		 16402018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1641
1642 PR 20319
1643 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1644 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1645
ce72cd46
AM		 16462018-06-06 Alan Modra <amodra@gmail.com>
1647
1648 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1649 setjmp. Move init for some other vars later too.
1650
4b8e28c7
MF		 16512018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1652
1653 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1654 (dis_private): Add new fields for property section tracking.
1655 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1656 (xtensa_instruction_fits): New functions.
1657 (fetch_data): Bump minimal fetch size to 4.
1658 (print_insn_xtensa): Make struct dis_private static.
1659 Load and prepare property table on section change.
1660 Don't disassemble literals. Don't disassemble instructions that
1661 cross property table boundaries.
1662
55e99962
L		 16632018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1664
1665 * configure: Regenerated.
1666
733bd0ab
JB		 16672018-06-01 Jan Beulich <jbeulich@suse.com>
1668
1669 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1670 * i386-tbl.h: Re-generate.
1671
dfd27d41
JB		 16722018-06-01 Jan Beulich <jbeulich@suse.com>
1673
1674 * i386-opc.tbl (sldt, str): Add NoRex64.
1675 * i386-tbl.h: Re-generate.
1676
64795710
JB		 16772018-06-01 Jan Beulich <jbeulich@suse.com>
1678
1679 * i386-opc.tbl (invpcid): Add Oword.
1680 * i386-tbl.h: Re-generate.
1681
030157d8
AM		 16822018-06-01 Alan Modra <amodra@gmail.com>
1683
1684 * sysdep.h (_bfd_error_handler): Don't declare.
1685 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1686 * rl78-decode.opc: Likewise.
1687 * msp430-decode.c: Regenerate.
1688 * rl78-decode.c: Regenerate.
1689
a9660a6f
AP		 16902018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1691
1692 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1693 * i386-init.h : Regenerated.
1694
277eb7f6
AM		 16952018-05-25 Alan Modra <amodra@gmail.com>
1696
1697 * Makefile.in: Regenerate.
1698 * po/POTFILES.in: Regenerate.
1699
98553ad3
PB		 17002018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1701
1702 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1703 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1704 (insert_bab, extract_bab, insert_btab, extract_btab,
1705 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1706 (BAT, BBA VBA RBS XB6S): Delete macros.
1707 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1708 (BB, BD, RBX, XC6): Update for new macros.
1709 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1710 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1711 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1712 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1713
7b4ae824
JD		 17142018-05-18 John Darrington <john@darrington.wattle.id.au>
1715
1716 * Makefile.am: Add support for s12z architecture.
1717 * configure.ac: Likewise.
1718 * disassemble.c: Likewise.
1719 * disassemble.h: Likewise.
1720 * Makefile.in: Regenerate.
1721 * configure: Regenerate.
1722 * s12z-dis.c: New file.
1723 * s12z.h: New file.
1724
29e0f0a1
AM		 17252018-05-18 Alan Modra <amodra@gmail.com>
1726
1727 * nfp-dis.c: Don't #include libbfd.h.
1728 (init_nfp3200_priv): Use bfd_get_section_contents.
1729 (nit_nfp6000_mecsr_sec): Likewise.
1730
809276d2
NC		 17312018-05-17 Nick Clifton <nickc@redhat.com>
1732
1733 * po/zh_CN.po: Updated simplified Chinese translation.
1734
ff329288
TC		 17352018-05-16 Tamar Christina <tamar.christina@arm.com>
1736
1737 PR binutils/23109
1738 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1739 * aarch64-dis-2.c: Regenerate.
1740
f9830ec1
TC		 17412018-05-15 Tamar Christina <tamar.christina@arm.com>
1742
1743 PR binutils/21446
1744 * aarch64-asm.c (opintl.h): Include.
1745 (aarch64_ins_sysreg): Enforce read/write constraints.
1746 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1747 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1748 (F_REG_READ, F_REG_WRITE): New.
1749 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1750 AARCH64_OPND_SYSREG.
1751 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1752 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1753 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1754 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1755 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1756 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1757 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1758 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1759 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1760 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1761 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1762 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1763 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1764 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1765 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1766 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1767 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1768
7d02540a
TC		 17692018-05-15 Tamar Christina <tamar.christina@arm.com>
1770
1771 PR binutils/21446
1772 * aarch64-dis.c (no_notes: New.
1773 (parse_aarch64_dis_option): Support notes.
1774 (aarch64_decode_insn, print_operands): Likewise.
1775 (print_aarch64_disassembler_options): Document notes.
1776 * aarch64-opc.c (aarch64_print_operand): Support notes.
1777
561a72d4
TC		 17782018-05-15 Tamar Christina <tamar.christina@arm.com>
1779
1780 PR binutils/21446
1781 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1782 and take error struct.
1783 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1784 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1785 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1786 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1787 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1788 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1789 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1790 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1791 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1792 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1793 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1794 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1795 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1796 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1797 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1798 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1799 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1800 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1801 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1802 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1803 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1804 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1805 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1806 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1807 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1808 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1809 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1810 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1811 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1812 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1813 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1814 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1815 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1816 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1817 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1818 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1819 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1820 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1821 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1822 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1823 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1824 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1825 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1826 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1827 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1828 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1829 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1830 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1831 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1832 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1833 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1834 (determine_disassembling_preference, aarch64_decode_insn,
1835 print_insn_aarch64_word, print_insn_data): Take errors struct.
1836 (print_insn_aarch64): Use errors.
1837 * aarch64-asm-2.c: Regenerate.
1838 * aarch64-dis-2.c: Regenerate.
1839 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1840 boolean in aarch64_insert_operan.
1841 (print_operand_extractor): Likewise.
1842 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1843
1678bd35
FT		 18442018-05-15 Francois H. Theron <francois.theron@netronome.com>
1845
1846 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1847
06cfb1c8
L		 18482018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1849
1850 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1851
84f9f8c3
AM		 18522018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1853
1854 * cr16-opc.c (cr16_instruction): Comment typo fix.
1855 * hppa-dis.c (print_insn_hppa): Likewise.
1856
e6f372ba
JW		 18572018-05-08 Jim Wilson <jimw@sifive.com>
1858
1859 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1860 (match_c_slli64, match_srxi_as_c_srxi): New.
1861 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1862 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1863 <c.slli, c.srli, c.srai>: Use match_s_slli.
1864 <c.slli64, c.srli64, c.srai64>: New.
1865
f413a913
AM		 18662018-05-08 Alan Modra <amodra@gmail.com>
1867
1868 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1869 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1870 partition opcode space for index lookup.
1871
a87a6478
PB		 18722018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1873
1874 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1875 <insn_length>: ...with this. Update usage.
1876 Remove duplicate call to *info->memory_error_func.
1877
c0a30a9f
L		 18782018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1879 H.J. Lu <hongjiu.lu@intel.com>
1880
1881 * i386-dis.c (Gva): New.
1882 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1883 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1884 (prefix_table): New instructions (see prefix above).
1885 (mod_table): New instructions (see prefix above).
1886 (OP_G): Handle va_mode.
1887 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1888 CPU_MOVDIR64B_FLAGS.
1889 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1890 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1891 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1892 * i386-opc.tbl: Add movidir{i,64b}.
1893 * i386-init.h: Regenerated.
1894 * i386-tbl.h: Likewise.
1895
75c0a438
L		 18962018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1897
1898 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1899 AddrPrefixOpReg.
1900 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1901 (AddrPrefixOpReg): This.
1902 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1903 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1904
2ceb7719
PB		 19052018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1906
1907 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1908 (vle_num_opcodes): Likewise.
1909 (spe2_num_opcodes): Likewise.
1910 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1911 initialization loop.
1912 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1913 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1914 only once.
1915
b3ac5c6c
TC		 19162018-05-01 Tamar Christina <tamar.christina@arm.com>
1917
1918 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1919
fe944acf
FT		 19202018-04-30 Francois H. Theron <francois.theron@netronome.com>
1921
1922 Makefile.am: Added nfp-dis.c.
1923 configure.ac: Added bfd_nfp_arch.
1924 disassemble.h: Added print_insn_nfp prototype.
1925 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1926 nfp-dis.c: New, for NFP support.
1927 po/POTFILES.in: Added nfp-dis.c to the list.
1928 Makefile.in: Regenerate.
1929 configure: Regenerate.
1930
e2195274
JB		 19312018-04-26 Jan Beulich <jbeulich@suse.com>
1932
1933 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1934 templates into their base ones.
1935 * i386-tlb.h: Re-generate.
1936
59ef5df4
JB		 19372018-04-26 Jan Beulich <jbeulich@suse.com>
1938
1939 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1940 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1941 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1942 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1943 * i386-init.h: Re-generate.
1944
6e041cf4
JB		 19452018-04-26 Jan Beulich <jbeulich@suse.com>
1946
1947 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1948 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1949 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1950 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1951 comment.
1952 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1953 and CpuRegMask.
1954 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1955 CpuRegMask: Delete.
1956 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1957 cpuregzmm, and cpuregmask.
1958 * i386-init.h: Re-generate.
1959 * i386-tbl.h: Re-generate.
1960
0e0eea78
JB		 19612018-04-26 Jan Beulich <jbeulich@suse.com>
1962
1963 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1964 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1965 * i386-init.h: Re-generate.
1966
2f1bada2
JB		 19672018-04-26 Jan Beulich <jbeulich@suse.com>
1968
1969 * i386-gen.c (VexImmExt): Delete.
1970 * i386-opc.h (VexImmExt, veximmext): Delete.
1971 * i386-opc.tbl: Drop all VexImmExt uses.
1972 * i386-tlb.h: Re-generate.
1973
bacd1457
JB		 19742018-04-25 Jan Beulich <jbeulich@suse.com>
1975
1976 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1977 register-only forms.
1978 * i386-tlb.h: Re-generate.
1979
10bba94b
TC		 19802018-04-25 Tamar Christina <tamar.christina@arm.com>
1981
1982 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1983
c48935d7
IT		 19842018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1985
1986 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1987 PREFIX_0F1C.
1988 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1989 (cpu_flags): Add CpuCLDEMOTE.
1990 * i386-init.h: Regenerate.
1991 * i386-opc.h (enum): Add CpuCLDEMOTE,
1992 (i386_cpu_flags): Add cpucldemote.
1993 * i386-opc.tbl: Add cldemote.
1994 * i386-tbl.h: Regenerate.
1995
211dc24b
AM		 19962018-04-16 Alan Modra <amodra@gmail.com>
1997
1998 * Makefile.am: Remove sh5 and sh64 support.
1999 * configure.ac: Likewise.
2000 * disassemble.c: Likewise.
2001 * disassemble.h: Likewise.
2002 * sh-dis.c: Likewise.
2003 * sh64-dis.c: Delete.
2004 * sh64-opc.c: Delete.
2005 * sh64-opc.h: Delete.
2006 * Makefile.in: Regenerate.
2007 * configure: Regenerate.
2008 * po/POTFILES.in: Regenerate.
2009
a9a4b302
AM		 20102018-04-16 Alan Modra <amodra@gmail.com>
2011
2012 * Makefile.am: Remove w65 support.
2013 * configure.ac: Likewise.
2014 * disassemble.c: Likewise.
2015 * disassemble.h: Likewise.
2016 * w65-dis.c: Delete.
2017 * w65-opc.h: Delete.
2018 * Makefile.in: Regenerate.
2019 * configure: Regenerate.
2020 * po/POTFILES.in: Regenerate.
2021
04cb01fd
AM		 20222018-04-16 Alan Modra <amodra@gmail.com>
2023
2024 * configure.ac: Remove we32k support.
2025 * configure: Regenerate.
2026
c2bf1eec
AM		 20272018-04-16 Alan Modra <amodra@gmail.com>
2028
2029 * Makefile.am: Remove m88k support.
2030 * configure.ac: Likewise.
2031 * disassemble.c: Likewise.
2032 * disassemble.h: Likewise.
2033 * m88k-dis.c: Delete.
2034 * Makefile.in: Regenerate.
2035 * configure: Regenerate.
2036 * po/POTFILES.in: Regenerate.
2037
6793974d
AM		 20382018-04-16 Alan Modra <amodra@gmail.com>
2039
2040 * Makefile.am: Remove i370 support.
2041 * configure.ac: Likewise.
2042 * disassemble.c: Likewise.
2043 * disassemble.h: Likewise.
2044 * i370-dis.c: Delete.
2045 * i370-opc.c: Delete.
2046 * Makefile.in: Regenerate.
2047 * configure: Regenerate.
2048 * po/POTFILES.in: Regenerate.
2049
e82aa794
AM		 20502018-04-16 Alan Modra <amodra@gmail.com>
2051
2052 * Makefile.am: Remove h8500 support.
2053 * configure.ac: Likewise.
2054 * disassemble.c: Likewise.
2055 * disassemble.h: Likewise.
2056 * h8500-dis.c: Delete.
2057 * h8500-opc.h: Delete.
2058 * Makefile.in: Regenerate.
2059 * configure: Regenerate.
2060 * po/POTFILES.in: Regenerate.
2061
fceadf09
AM		 20622018-04-16 Alan Modra <amodra@gmail.com>
2063
2064 * configure.ac: Remove tahoe support.
2065 * configure: Regenerate.
2066
ae1d3843
L		 20672018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2068
2069 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2070 umwait.
2071 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2072 64-bit mode.
2073 * i386-tbl.h: Regenerated.
2074
de89d0a3
IT		 20752018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2076
2077 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2078 PREFIX_MOD_1_0FAE_REG_6.
2079 (va_mode): New.
2080 (OP_E_register): Use va_mode.
2081 * i386-dis-evex.h (prefix_table):
2082 New instructions (see prefixes above).
2083 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2084 (cpu_flags): Likewise.
2085 * i386-opc.h (enum): Likewise.
2086 (i386_cpu_flags): Likewise.
2087 * i386-opc.tbl: Add umonitor, umwait, tpause.
2088 * i386-init.h: Regenerate.
2089 * i386-tbl.h: Likewise.
2090
a8eb42a8
AM		 20912018-04-11 Alan Modra <amodra@gmail.com>
2092
2093 * opcodes/i860-dis.c: Delete.
2094 * opcodes/i960-dis.c: Delete.
2095 * Makefile.am: Remove i860 and i960 support.
2096 * configure.ac: Likewise.
2097 * disassemble.c: Likewise.
2098 * disassemble.h: Likewise.
2099 * Makefile.in: Regenerate.
2100 * configure: Regenerate.
2101 * po/POTFILES.in: Regenerate.
2102
caf0678c
L		 21032018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2104
2105 PR binutils/23025
2106 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2107 to 0.
2108 (print_insn): Clear vex instead of vex.evex.
2109
4fb0d2b9
NC		 21102018-04-04 Nick Clifton <nickc@redhat.com>
2111
2112 * po/es.po: Updated Spanish translation.
2113
c39e5b26
JB		 21142018-03-28 Jan Beulich <jbeulich@suse.com>
2115
2116 * i386-gen.c (opcode_modifiers): Delete VecESize.
2117 * i386-opc.h (VecESize): Delete.
2118 (struct i386_opcode_modifier): Delete vecesize.
2119 * i386-opc.tbl: Drop VecESize.
2120 * i386-tlb.h: Re-generate.
2121
8e6e0792
JB		 21222018-03-28 Jan Beulich <jbeulich@suse.com>
2123
2124 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2125 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2126 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2127 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2128 * i386-tlb.h: Re-generate.
2129
9f123b91
JB		 21302018-03-28 Jan Beulich <jbeulich@suse.com>
2131
2132 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2133 Fold AVX512 forms
2134 * i386-tlb.h: Re-generate.
2135
9646c87b
JB		 21362018-03-28 Jan Beulich <jbeulich@suse.com>
2137
2138 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2139 (vex_len_table): Drop Y for vcvt*2si.
2140 (putop): Replace plain 'Y' handling by abort().
2141
c8d59609
NC		 21422018-03-28 Nick Clifton <nickc@redhat.com>
2143
2144 PR 22988
2145 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2146 instructions with only a base address register.
2147 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2148 handle AARHC64_OPND_SVE_ADDR_R.
2149 (aarch64_print_operand): Likewise.
2150 * aarch64-asm-2.c: Regenerate.
2151 * aarch64_dis-2.c: Regenerate.
2152 * aarch64-opc-2.c: Regenerate.
2153
b8c169f3
JB		 21542018-03-22 Jan Beulich <jbeulich@suse.com>
2155
2156 * i386-opc.tbl: Drop VecESize from register only insn forms and
2157 memory forms not allowing broadcast.
2158 * i386-tlb.h: Re-generate.
2159
96bc132a
JB		 21602018-03-22 Jan Beulich <jbeulich@suse.com>
2161
2162 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2163 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2164 sha256*): Drop Disp<N>.
2165
9f79e886
JB		 21662018-03-22 Jan Beulich <jbeulich@suse.com>
2167
2168 * i386-dis.c (EbndS, bnd_swap_mode): New.
2169 (prefix_table): Use EbndS.
2170 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2171 * i386-opc.tbl (bndmov): Move misplaced Load.
2172 * i386-tlb.h: Re-generate.
2173
d6793fa1
JB		 21742018-03-22 Jan Beulich <jbeulich@suse.com>
2175
2176 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2177 templates allowing memory operands and folded ones for register
2178 only flavors.
2179 * i386-tlb.h: Re-generate.
2180
f7768225
JB		 21812018-03-22 Jan Beulich <jbeulich@suse.com>
2182
2183 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2184 256-bit templates. Drop redundant leftover Disp<N>.
2185 * i386-tlb.h: Re-generate.
2186
0e35537d
JW		 21872018-03-14 Kito Cheng <kito.cheng@gmail.com>
2188
2189 * riscv-opc.c (riscv_insn_types): New.
2190
b4a3689a
NC		 21912018-03-13 Nick Clifton <nickc@redhat.com>
2192
2193 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2194
d3d50934
L		 21952018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2196
2197 * i386-opc.tbl: Add Optimize to clr.
2198 * i386-tbl.h: Regenerated.
2199
bd5dea88
L		 22002018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2201
2202 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2203 * i386-opc.h (OldGcc): Removed.
2204 (i386_opcode_modifier): Remove oldgcc.
2205 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2206 instructions for old (<= 2.8.1) versions of gcc.
2207 * i386-tbl.h: Regenerated.
2208
e771e7c9
JB		 22092018-03-08 Jan Beulich <jbeulich@suse.com>
2210
2211 * i386-opc.h (EVEXDYN): New.
2212 * i386-opc.tbl: Fold various AVX512VL templates.
2213 * i386-tlb.h: Re-generate.
2214
ed438a93
JB		 22152018-03-08 Jan Beulich <jbeulich@suse.com>
2216
2217 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2218 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2219 vpexpandd, vpexpandq): Fold AFX512VF templates.
2220 * i386-tlb.h: Re-generate.
2221
454172a9
JB		 22222018-03-08 Jan Beulich <jbeulich@suse.com>
2223
2224 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2225 Fold 128- and 256-bit VEX-encoded templates.
2226 * i386-tlb.h: Re-generate.
2227
36824150
JB		 22282018-03-08 Jan Beulich <jbeulich@suse.com>
2229
2230 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2231 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2232 vpexpandd, vpexpandq): Fold AVX512F templates.
2233 * i386-tlb.h: Re-generate.
2234
e7f5c0a9
JB		 22352018-03-08 Jan Beulich <jbeulich@suse.com>
2236
2237 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2238 64-bit templates. Drop Disp<N>.
2239 * i386-tlb.h: Re-generate.
2240
25a4277f
JB		 22412018-03-08 Jan Beulich <jbeulich@suse.com>
2242
2243 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2244 and 256-bit templates.
2245 * i386-tlb.h: Re-generate.
2246
d2224064
JB		 22472018-03-08 Jan Beulich <jbeulich@suse.com>
2248
2249 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2250 * i386-tlb.h: Re-generate.
2251
1b193f0b
JB		 22522018-03-08 Jan Beulich <jbeulich@suse.com>
2253
2254 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2255 Drop NoAVX.
2256 * i386-tlb.h: Re-generate.
2257
f2f6a710
JB		 22582018-03-08 Jan Beulich <jbeulich@suse.com>
2259
2260 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2261 * i386-tlb.h: Re-generate.
2262
38e314eb
JB		 22632018-03-08 Jan Beulich <jbeulich@suse.com>
2264
2265 * i386-gen.c (opcode_modifiers): Delete FloatD.
2266 * i386-opc.h (FloatD): Delete.
2267 (struct i386_opcode_modifier): Delete floatd.
2268 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2269 FloatD by D.
2270 * i386-tlb.h: Re-generate.
2271
d53e6b98
JB		 22722018-03-08 Jan Beulich <jbeulich@suse.com>
2273
2274 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2275
2907c2f5
JB		 22762018-03-08 Jan Beulich <jbeulich@suse.com>
2277
2278 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2279 * i386-tlb.h: Re-generate.
2280
73053c1f
JB		 22812018-03-08 Jan Beulich <jbeulich@suse.com>
2282
2283 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2284 forms.
2285 * i386-tlb.h: Re-generate.
2286
52fe4420
AM		 22872018-03-07 Alan Modra <amodra@gmail.com>
2288
2289 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2290 bfd_arch_rs6000.
2291 * disassemble.h (print_insn_rs6000): Delete.
2292 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2293 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2294 (print_insn_rs6000): Delete.
2295
a6743a54
AM		 22962018-03-03 Alan Modra <amodra@gmail.com>
2297
2298 * sysdep.h (opcodes_error_handler): Define.
2299 (_bfd_error_handler): Declare.
2300 * Makefile.am: Remove stray #.
2301 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2302 EDIT" comment.
2303 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2304 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2305 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2306 opcodes_error_handler to print errors. Standardize error messages.
2307 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2308 and include opintl.h.
2309 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2310 * i386-gen.c: Standardize error messages.
2311 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2312 * Makefile.in: Regenerate.
2313 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2314 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2315 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2316 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2317 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2318 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2319 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2320 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2321 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2322 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2323 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2324 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2325 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2326
8305403a
L		 23272018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2328
2329 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2330 vpsub[bwdq] instructions.
2331 * i386-tbl.h: Regenerated.
2332
e184813f
AM		 23332018-03-01 Alan Modra <amodra@gmail.com>
2334
2335 * configure.ac (ALL_LINGUAS): Sort.
2336 * configure: Regenerate.
2337
5b616bef
TP		 23382018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2339
2340 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2341 macro by assignements.
2342
b6f8c7c4
L		 23432018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2344
2345 PR gas/22871
2346 * i386-gen.c (opcode_modifiers): Add Optimize.
2347 * i386-opc.h (Optimize): New enum.
2348 (i386_opcode_modifier): Add optimize.
2349 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2350 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2351 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2352 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2353 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2354 vpxord and vpxorq.
2355 * i386-tbl.h: Regenerated.
2356
e95b887f
AM		 23572018-02-26 Alan Modra <amodra@gmail.com>
2358
2359 * crx-dis.c (getregliststring): Allocate a large enough buffer
2360 to silence false positive gcc8 warning.
2361
0bccfb29
JW		 23622018-02-22 Shea Levy <shea@shealevy.com>
2363
2364 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2365
6b6b6807
L		 23662018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2367
2368 * i386-opc.tbl: Add {rex},
2369 * i386-tbl.h: Regenerated.
2370
75f31665
MR		 23712018-02-20 Maciej W. Rozycki <macro@mips.com>
2372
2373 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2374 (mips16_opcodes): Replace `M' with `m' for "restore".
2375
e207bc53
TP		 23762018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2377
2378 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2379
87993319
MR		 23802018-02-13 Maciej W. Rozycki <macro@mips.com>
2381
2382 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2383 variable to `function_index'.
2384
68d20676
NC		 23852018-02-13 Nick Clifton <nickc@redhat.com>
2386
2387 PR 22823
2388 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2389 about truncation of printing.
2390
d2159fdc
HW		 23912018-02-12 Henry Wong <henry@stuffedcow.net>
2392
2393 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2394
f174ef9f
NC		 23952018-02-05 Nick Clifton <nickc@redhat.com>
2396
2397 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2398
be3a8dca
IT		 23992018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2400
2401 * i386-dis.c (enum): Add pconfig.
2402 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2403 (cpu_flags): Add CpuPCONFIG.
2404 * i386-opc.h (enum): Add CpuPCONFIG.
2405 (i386_cpu_flags): Add cpupconfig.
2406 * i386-opc.tbl: Add PCONFIG instruction.
2407 * i386-init.h: Regenerate.
2408 * i386-tbl.h: Likewise.
2409
3233d7d0
IT		 24102018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2411
2412 * i386-dis.c (enum): Add PREFIX_0F09.
2413 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2414 (cpu_flags): Add CpuWBNOINVD.
2415 * i386-opc.h (enum): Add CpuWBNOINVD.
2416 (i386_cpu_flags): Add cpuwbnoinvd.
2417 * i386-opc.tbl: Add WBNOINVD instruction.
2418 * i386-init.h: Regenerate.
2419 * i386-tbl.h: Likewise.
2420
e925c834
JW		 24212018-01-17 Jim Wilson <jimw@sifive.com>
2422
2423 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2424
d777820b
IT		 24252018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2426
2427 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2428 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2429 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2430 (cpu_flags): Add CpuIBT, CpuSHSTK.
2431 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2432 (i386_cpu_flags): Add cpuibt, cpushstk.
2433 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2434 * i386-init.h: Regenerate.
2435 * i386-tbl.h: Likewise.
2436
f6efed01
NC		 24372018-01-16 Nick Clifton <nickc@redhat.com>
2438
2439 * po/pt_BR.po: Updated Brazilian Portugese translation.
2440 * po/de.po: Updated German translation.
2441
2721d702
JW		 24422018-01-15 Jim Wilson <jimw@sifive.com>
2443
2444 * riscv-opc.c (match_c_nop): New.
2445 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2446
616dcb87
NC		 24472018-01-15 Nick Clifton <nickc@redhat.com>
2448
2449 * po/uk.po: Updated Ukranian translation.
2450
3957a496
NC		 24512018-01-13 Nick Clifton <nickc@redhat.com>
2452
2453 * po/opcodes.pot: Regenerated.
2454
769c7ea5
NC		 24552018-01-13 Nick Clifton <nickc@redhat.com>
2456
2457 * configure: Regenerate.
2458
faf766e3
NC		 24592018-01-13 Nick Clifton <nickc@redhat.com>
2460
2461 2.30 branch created.
2462
888a89da
IT		 24632018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2464
2465 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2466 * i386-tbl.h: Regenerate.
2467
cbda583a
JB		 24682018-01-10 Jan Beulich <jbeulich@suse.com>
2469
2470 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2471 * i386-tbl.h: Re-generate.
2472
c9e92278
JB		 24732018-01-10 Jan Beulich <jbeulich@suse.com>
2474
2475 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2476 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2477 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2478 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2479 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2480 Disp8MemShift of AVX512VL forms.
2481 * i386-tbl.h: Re-generate.
2482
35fd2b2b
JW		 24832018-01-09 Jim Wilson <jimw@sifive.com>
2484
2485 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2486 then the hi_addr value is zero.
2487
91d8b670
JG		 24882018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2489
2490 * arm-dis.c (arm_opcodes): Add csdb.
2491 (thumb32_opcodes): Add csdb.
2492
be2e7d95
JG		 24932018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2494
2495 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2496 * aarch64-asm-2.c: Regenerate.
2497 * aarch64-dis-2.c: Regenerate.
2498 * aarch64-opc-2.c: Regenerate.
2499
704a705d
L		 25002018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2501
2502 PR gas/22681
2503 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2504 Remove AVX512 vmovd with 64-bit operands.
2505 * i386-tbl.h: Regenerated.
2506
35eeb78f
JW		 25072018-01-05 Jim Wilson <jimw@sifive.com>
2508
2509 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2510 jalr.
2511
219d1afa
AM		 25122018-01-03 Alan Modra <amodra@gmail.com>
2513
2514 Update year range in copyright notice of all files.
2515
1508bbf5
JB		 25162018-01-02 Jan Beulich <jbeulich@suse.com>
2517
2518 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2519 and OPERAND_TYPE_REGZMM entries.
2520
1e563868 2521For older changes see ChangeLog-2017
3499769a 2522\f
1e563868 2523Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2524
2525Copying and distribution of this file, with or without modification,
2526are permitted in any medium without royalty provided the copyright
2527notice and this notice are preserved.
2528
2529Local Variables:
2530mode: change-log
2531left-margin: 8
2532fill-column: 74
2533version-control: never
2534End:
GDB Binutils - Deliverables
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