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ubsan: wasm: shift is too large for 64-bit type 'bfd_vma'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
27c1c427
AM		 12019-12-23 Alan Modra <amodra@gmail.com>
2
3 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
4 Catch value overflow. Sign extend only on terminating byte.
5
cda8d785
AM		 62019-12-20 Alan Modra <amodra@gmail.com>
7
8 PR 25281
9 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
10 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
11 printed. Print .word in more cases.
12
bcd9f578
AM		 132019-12-20 Alan Modra <amodra@gmail.com>
14
15 * or1k-ibld.c: Regenerate.
16
15d2859f
AM		 172019-12-20 Alan Modra <amodra@gmail.com>
18
19 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
20 unsigned variables.
21
000fe1a7
AM		 222019-12-20 Alan Modra <amodra@gmail.com>
23
24 * m68hc11-dis.c (read_memory): Delete forward decls.
25 (print_indexed_operand, print_insn): Likewise.
26 (print_indexed_operand): Formatting. Don't rely on short being
27 exactly 16 bits, make sign extension explicit.
28 (print_insn): Likewise. Avoid signed overflow.
29
f0090188
AM		 302019-12-19 Alan Modra <amodra@gmail.com>
31
32 * vax-dis.c (print_insn_mode): Stop index mode recursion.
33
1d29ab86
DF		 342019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
35
36 PR 25277
37 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
38 fdiv with "mbi_".
39 * microblaze-opc.h (opcodes): Adjust to suit.
40
2480b6fa
AM		 412019-12-18 Alan Modra <amodra@gmail.com>
42
43 * alpha-opc.c (OP): Avoid signed overflow.
44 * arm-dis.c (print_insn): Likewise.
45 * mcore-dis.c (print_insn_mcore): Likewise.
46 * pj-dis.c (get_int): Likewise.
47 * ppc-opc.c (EBD15, EBD15BI): Likewise.
48 * score7-dis.c (s7_print_insn): Likewise.
49 * tic30-dis.c (print_insn_tic30): Likewise.
50 * v850-opc.c (insert_SELID): Likewise.
51 * vax-dis.c (print_insn_vax): Likewise.
52 * arc-ext.c (create_map): Likewise.
53 (struct ExtAuxRegister): Make "address" field unsigned int.
54 (arcExtMap_auxRegName): Pass unsigned address.
55 (dump_ARC_extmap): Adjust.
56 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
57
eb7b5046
AM		 582019-12-17 Alan Modra <amodra@gmail.com>
59
60 * visium-dis.c (print_insn_visium): Avoid signed overflow.
61
29298bf6
AM		 622019-12-17 Alan Modra <amodra@gmail.com>
63
64 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
65 (value_fit_unsigned_field_p): Likewise.
66 (aarch64_wide_constant_p): Likewise.
67 (operand_general_constraint_met_p): Likewise.
68 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
69
e46d79a7
AM		 702019-12-17 Alan Modra <amodra@gmail.com>
71
72 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
73 (print_insn_nds32): Use uint64_t for "given" and "given1".
74
5b660084
AM		 752019-12-17 Alan Modra <amodra@gmail.com>
76
77 * tic80-dis.c: Delete file.
78 * tic80-opc.c: Delete file.
79 * disassemble.c: Remove tic80 support.
80 * disassemble.h: Likewise.
81 * Makefile.am: Likewise.
82 * configure.ac: Likewise.
83 * Makefile.in: Regenerate.
84 * configure: Regenerate.
85 * po/POTFILES.in: Regenerate.
86
62e65990
AM		 872019-12-17 Alan Modra <amodra@gmail.com>
88
89 * bpf-ibld.c: Regenerate.
90
f81e7e2d
AM		 912019-12-16 Alan Modra <amodra@gmail.com>
92
93 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
94 conditional.
95 (aarch64_ext_imm): Avoid signed overflow.
96
488d02fe
AM		 972019-12-16 Alan Modra <amodra@gmail.com>
98
99 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
100
8a92faab
AM		 1012019-12-16 Alan Modra <amodra@gmail.com>
102
103 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
104
e6ced26a
AM		 1052019-12-16 Alan Modra <amodra@gmail.com>
106
107 * xstormy16-ibld.c: Regenerate.
108
84e098cd
AM		 1092019-12-16 Alan Modra <amodra@gmail.com>
110
111 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
112 value adjustment so that it doesn't affect reg field too.
113
36bd8ea7
AM		 1142019-12-16 Alan Modra <amodra@gmail.com>
115
116 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
117 (get_number_of_operands, getargtype, getbits, getregname),
118 (getcopregname, getprocregname, gettrapstring, getcinvstring),
119 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
120 (powerof2, match_opcode, make_instruction, print_arguments),
121 (print_arg): Delete forward declarations, moving static to..
122 (getregname, getcopregname, getregliststring): ..these definitions.
123 (build_mask): Return unsigned int mask.
124 (match_opcode): Use unsigned int vars.
125
cedfc774
AM		 1262019-12-16 Alan Modra <amodra@gmail.com>
127
128 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
129
4bdb25fe
AM		 1302019-12-16 Alan Modra <amodra@gmail.com>
131
132 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
133 (struct objdump_disasm_info): Delete.
134 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
135 N32_IMMS to unsigned before shifting left.
136
cf950fd4
AM		 1372019-12-16 Alan Modra <amodra@gmail.com>
138
139 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
140 (print_insn_moxie): Remove unnecessary cast.
141
967354c3
AM		 1422019-12-12 Alan Modra <amodra@gmail.com>
143
144 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
145 mask.
146
1d61b032
AM		 1472019-12-11 Alan Modra <amodra@gmail.com>
148
149 * arc-dis.c (BITS): Don't truncate high bits with shifts.
150 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
151 * tic54x-dis.c (print_instruction): Likewise.
152 * tilegx-opc.c (parse_insn_tilegx): Likewise.
153 * tilepro-opc.c (parse_insn_tilepro): Likewise.
154 * visium-dis.c (disassem_class0): Likewise.
155 * pdp11-dis.c (sign_extend): Likewise.
156 (SIGN_BITS): Delete.
157 * epiphany-ibld.c: Regenerate.
158 * lm32-ibld.c: Regenerate.
159 * m32c-ibld.c: Regenerate.
160
5afa80e9
AM		 1612019-12-11 Alan Modra <amodra@gmail.com>
162
163 * ns32k-dis.c (sign_extend): Correct last patch.
164
5c05618a
AM		 1652019-12-11 Alan Modra <amodra@gmail.com>
166
167 * vax-dis.c (NEXTLONG): Avoid signed overflow.
168
2a81ccbb
AM		 1692019-12-11 Alan Modra <amodra@gmail.com>
170
171 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
172 sign extend using shifts.
173
b84f6152
AM		 1742019-12-11 Alan Modra <amodra@gmail.com>
175
176 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
177
66152f16
AM		 1782019-12-11 Alan Modra <amodra@gmail.com>
179
180 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
181 on NULL registertable entry.
182 (tic4x_hash_opcode): Use unsigned arithmetic.
183
205c426a
AM		 1842019-12-11 Alan Modra <amodra@gmail.com>
185
186 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
187
fb4cb4e2
AM		 1882019-12-11 Alan Modra <amodra@gmail.com>
189
190 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
191 (bit_extract_simple, sign_extend): Likewise.
192
96f1f604
AM		 1932019-12-11 Alan Modra <amodra@gmail.com>
194
195 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
196
8c9b4171
AM		 1972019-12-11 Alan Modra <amodra@gmail.com>
198
199 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
200
334175b6
AM		 2012019-12-11 Alan Modra <amodra@gmail.com>
202
203 * m68k-dis.c (COERCE32): Cast value first.
204 (NEXTLONG, NEXTULONG): Avoid signed overflow.
205
f8a87c78
AM		 2062019-12-11 Alan Modra <amodra@gmail.com>
207
208 * h8300-dis.c (extract_immediate): Avoid signed overflow.
209 (bfd_h8_disassemble): Likewise.
210
159653d8
AM		 2112019-12-11 Alan Modra <amodra@gmail.com>
212
213 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
214 past end of operands array.
215
d93bba9e
AM		 2162019-12-11 Alan Modra <amodra@gmail.com>
217
218 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
219 overflow when collecting bytes of a number.
220
c202f69e
AM		 2212019-12-11 Alan Modra <amodra@gmail.com>
222
223 * cris-dis.c (print_with_operands): Avoid signed integer
224 overflow when collecting bytes of a 32-bit integer.
225
0ef562a4
AM		 2262019-12-11 Alan Modra <amodra@gmail.com>
227
228 * cr16-dis.c (EXTRACT, SBM): Rewrite.
229 (cr16_match_opcode): Delete duplicate bcond test.
230
2fd2b153
AM		 2312019-12-11 Alan Modra <amodra@gmail.com>
232
233 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
234 (SIGNBIT): New.
235 (MASKBITS, SIGNEXTEND): Rewrite.
236 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
237 unsigned arithmetic, instead assign result of SIGNEXTEND back
238 to x.
239 (fmtconst_val): Use 1u in shift expression.
240
a11db3e9
AM		 2412019-12-11 Alan Modra <amodra@gmail.com>
242
243 * arc-dis.c (find_format_from_table): Use ull constant when
244 shifting by up to 32.
245
9d48687b
AM		 2462019-12-11 Alan Modra <amodra@gmail.com>
247
248 PR 25270
249 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
250 false when field is zero for sve_size_tsz_bhs.
251
b8e61daa
AM		 2522019-12-11 Alan Modra <amodra@gmail.com>
253
254 * epiphany-ibld.c: Regenerate.
255
20135676
AM		 2562019-12-10 Alan Modra <amodra@gmail.com>
257
258 PR 24960
259 * disassemble.c (disassemble_free_target): New function.
260
103ebbc3
AM		 2612019-12-10 Alan Modra <amodra@gmail.com>
262
263 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
264 * disassemble.c (disassemble_init_for_target): Likewise.
265 * bpf-dis.c: Regenerate.
266 * epiphany-dis.c: Regenerate.
267 * fr30-dis.c: Regenerate.
268 * frv-dis.c: Regenerate.
269 * ip2k-dis.c: Regenerate.
270 * iq2000-dis.c: Regenerate.
271 * lm32-dis.c: Regenerate.
272 * m32c-dis.c: Regenerate.
273 * m32r-dis.c: Regenerate.
274 * mep-dis.c: Regenerate.
275 * mt-dis.c: Regenerate.
276 * or1k-dis.c: Regenerate.
277 * xc16x-dis.c: Regenerate.
278 * xstormy16-dis.c: Regenerate.
279
6f0e0752
AM		 2802019-12-10 Alan Modra <amodra@gmail.com>
281
282 * ppc-dis.c (private): Delete variable.
283 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
284 (powerpc_init_dialect): Don't use global private.
285
e7c22a69
AM		 2862019-12-10 Alan Modra <amodra@gmail.com>
287
288 * s12z-opc.c: Formatting.
289
0a6aef6b
AM		 2902019-12-08 Alan Modra <amodra@gmail.com>
291
292 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
293 registers.
294
2dc4b12f
JB		 2952019-12-05 Jan Beulich <jbeulich@suse.com>
296
297 * aarch64-tbl.h (aarch64_feature_crypto,
298 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
299 CRYPTO_V8_2_INSN): Delete.
300
378fd436
AM		 3012019-12-05 Alan Modra <amodra@gmail.com>
302
303 PR 25249
304 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
305 (struct string_buf): New.
306 (strbuf): New function.
307 (get_field): Use strbuf rather than strdup of local temp.
308 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
309 (get_field_rfsl, get_field_imm15): Likewise.
310 (get_field_rd, get_field_r1, get_field_r2): Update macros.
311 (get_field_special): Likewise. Don't strcpy spr. Formatting.
312 (print_insn_microblaze): Formatting. Init and pass string_buf to
313 get_field functions.
314
0ba59a29
JB		 3152019-12-04 Jan Beulich <jbeulich@suse.com>
316
317 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
318 * i386-tbl.h: Re-generate.
319
77ad8092
JB		 3202019-12-04 Jan Beulich <jbeulich@suse.com>
321
322 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
323
3036c899
JB		 3242019-12-04 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
327 forms.
328 (xbegin): Drop DefaultSize.
329 * i386-tbl.h: Re-generate.
330
8b301fbb
MI		 3312019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
332
333 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
334 Change the coproc CRC conditions to use the extension
335 feature set, second word, base on ARM_EXT2_CRC.
336
6aa385b9
JB		 3372019-11-14 Jan Beulich <jbeulich@suse.com>
338
339 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
340 * i386-tbl.h: Re-generate.
341
0cfa3eb3
JB		 3422019-11-14 Jan Beulich <jbeulich@suse.com>
343
344 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
345 JumpInterSegment, and JumpAbsolute entries.
346 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
347 JUMP_ABSOLUTE): Define.
348 (struct i386_opcode_modifier): Extend jump field to 3 bits.
349 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
350 fields.
351 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
352 JumpInterSegment): Define.
353 * i386-tbl.h: Re-generate.
354
6f2f06be
JB		 3552019-11-14 Jan Beulich <jbeulich@suse.com>
356
357 * i386-gen.c (operand_type_init): Remove
358 OPERAND_TYPE_JUMPABSOLUTE entry.
359 (opcode_modifiers): Add JumpAbsolute entry.
360 (operand_types): Remove JumpAbsolute entry.
361 * i386-opc.h (JumpAbsolute): Move between enums.
362 (struct i386_opcode_modifier): Add jumpabsolute field.
363 (union i386_operand_type): Remove jumpabsolute field.
364 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
365 * i386-init.h, i386-tbl.h: Re-generate.
366
601e8564
JB		 3672019-11-14 Jan Beulich <jbeulich@suse.com>
368
369 * i386-gen.c (opcode_modifiers): Add AnySize entry.
370 (operand_types): Remove AnySize entry.
371 * i386-opc.h (AnySize): Move between enums.
372 (struct i386_opcode_modifier): Add anysize field.
373 (OTUnused): Un-comment.
374 (union i386_operand_type): Remove anysize field.
375 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
376 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
377 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
378 AnySize.
379 * i386-tbl.h: Re-generate.
380
7722d40a
JW		 3812019-11-12 Nelson Chu <nelson.chu@sifive.com>
382
383 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
384 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
385 use the floating point register (FPR).
386
ce760a76
MI		 3872019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
388
389 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
390 cmode 1101.
391 (is_mve_encoding_conflict): Update cmode conflict checks for
392 MVE_VMVN_IMM.
393
51c8edf6
JB		 3942019-11-12 Jan Beulich <jbeulich@suse.com>
395
396 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
397 entry.
398 (operand_types): Remove EsSeg entry.
399 (main): Replace stale use of OTMax.
400 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
401 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
402 (EsSeg): Delete.
403 (OTUnused): Comment out.
404 (union i386_operand_type): Remove esseg field.
405 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
406 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
407 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
408 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
409 * i386-init.h, i386-tbl.h: Re-generate.
410
474da251
JB		 4112019-11-12 Jan Beulich <jbeulich@suse.com>
412
413 * i386-gen.c (operand_instances): Add RegB entry.
414 * i386-opc.h (enum operand_instance): Add RegB.
415 * i386-opc.tbl (RegC, RegD, RegB): Define.
416 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
417 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
418 monitorx, mwaitx): Drop ImmExt and convert encodings
419 accordingly.
420 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
421 (edx, rdx): Add Instance=RegD.
422 (ebx, rbx): Add Instance=RegB.
423 * i386-tbl.h: Re-generate.
424
75e5731b
JB		 4252019-11-12 Jan Beulich <jbeulich@suse.com>
426
427 * i386-gen.c (operand_type_init): Adjust
428 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
429 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
430 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
431 (operand_instances): New.
432 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
433 (output_operand_type): New parameter "instance". Process it.
434 (process_i386_operand_type): New local variable "instance".
435 (main): Adjust static assertions.
436 * i386-opc.h (INSTANCE_WIDTH): Define.
437 (enum operand_instance): New.
438 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
439 (union i386_operand_type): Replace acc, inoutportreg, and
440 shiftcount by instance.
441 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
442 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
443 Add Instance=.
444 * i386-init.h, i386-tbl.h: Re-generate.
445
91802f3c
JB		 4462019-11-11 Jan Beulich <jbeulich@suse.com>
447
448 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
449 smaxp/sminp entries' "tied_operand" field to 2.
450
4f5fc85d
JB		 4512019-11-11 Jan Beulich <jbeulich@suse.com>
452
453 * aarch64-opc.c (operand_general_constraint_met_p): Replace
454 "index" local variable by that of the already existing "num".
455
dc2be329
L		 4562019-11-08 H.J. Lu <hongjiu.lu@intel.com>
457
458 PR gas/25167
459 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
460 * i386-tbl.h: Regenerated.
461
f74a6307
JB		 4622019-11-08 Jan Beulich <jbeulich@suse.com>
463
464 * i386-gen.c (operand_type_init): Add Class= to
465 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
466 OPERAND_TYPE_REGBND entry.
467 (operand_classes): Add RegMask and RegBND entries.
468 (operand_types): Drop RegMask and RegBND entry.
469 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
470 (RegMask, RegBND): Delete.
471 (union i386_operand_type): Remove regmask and regbnd fields.
472 * i386-opc.tbl (RegMask, RegBND): Define.
473 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
474 Class=RegBND.
475 * i386-init.h, i386-tbl.h: Re-generate.
476
3528c362
JB		 4772019-11-08 Jan Beulich <jbeulich@suse.com>
478
479 * i386-gen.c (operand_type_init): Add Class= to
480 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
481 OPERAND_TYPE_REGZMM entries.
482 (operand_classes): Add RegMMX and RegSIMD entries.
483 (operand_types): Drop RegMMX and RegSIMD entries.
484 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
485 (RegMMX, RegSIMD): Delete.
486 (union i386_operand_type): Remove regmmx and regsimd fields.
487 * i386-opc.tbl (RegMMX): Define.
488 (RegXMM, RegYMM, RegZMM): Add Class=.
489 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
490 Class=RegSIMD.
491 * i386-init.h, i386-tbl.h: Re-generate.
492
4a5c67ed
JB		 4932019-11-08 Jan Beulich <jbeulich@suse.com>
494
495 * i386-gen.c (operand_type_init): Add Class= to
496 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
497 entries.
498 (operand_classes): Add RegCR, RegDR, and RegTR entries.
499 (operand_types): Drop Control, Debug, and Test entries.
500 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
501 (Control, Debug, Test): Delete.
502 (union i386_operand_type): Remove control, debug, and test
503 fields.
504 * i386-opc.tbl (Control, Debug, Test): Define.
505 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
506 Class=RegDR, and Test by Class=RegTR.
507 * i386-init.h, i386-tbl.h: Re-generate.
508
00cee14f
JB		 5092019-11-08 Jan Beulich <jbeulich@suse.com>
510
511 * i386-gen.c (operand_type_init): Add Class= to
512 OPERAND_TYPE_SREG entry.
513 (operand_classes): Add SReg entry.
514 (operand_types): Drop SReg entry.
515 * i386-opc.h (enum operand_class): Add SReg.
516 (SReg): Delete.
517 (union i386_operand_type): Remove sreg field.
518 * i386-opc.tbl (SReg): Define.
519 * i386-reg.tbl: Replace SReg by Class=SReg.
520 * i386-init.h, i386-tbl.h: Re-generate.
521
bab6aec1
JB		 5222019-11-08 Jan Beulich <jbeulich@suse.com>
523
524 * i386-gen.c (operand_type_init): Add Class=. New
525 OPERAND_TYPE_ANYIMM entry.
526 (operand_classes): New.
527 (operand_types): Drop Reg entry.
528 (output_operand_type): New parameter "class". Process it.
529 (process_i386_operand_type): New local variable "class".
530 (main): Adjust static assertions.
531 * i386-opc.h (CLASS_WIDTH): Define.
532 (enum operand_class): New.
533 (Reg): Replace by Class. Adjust comment.
534 (union i386_operand_type): Replace reg by class.
535 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
536 Class=.
537 * i386-reg.tbl: Replace Reg by Class=Reg.
538 * i386-init.h: Re-generate.
539
1f4cd317
MM		 5402019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
541
542 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
543 (aarch64_opcode_table): Add data gathering hint mnemonic.
544 * opcodes/aarch64-dis-2.c: Account for new instruction.
545
616ce08e
MM		 5462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
547
548 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
549
550
8382113f
MM		 5512019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
552
553 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
554 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
555 aarch64_feature_f64mm): New feature sets.
556 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
557 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
558 instructions.
559 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
560 macros.
561 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
562 (OP_SVE_QQQ): New qualifier.
563 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
564 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
565 the movprfx constraint.
566 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
567 (aarch64_opcode_table): Define new instructions smmla,
568 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
569 uzip{1/2}, trn{1/2}.
570 * aarch64-opc.c (operand_general_constraint_met_p): Handle
571 AARCH64_OPND_SVE_ADDR_RI_S4x32.
572 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
573 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
574 Account for new instructions.
575 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
576 S4x32 operand.
577 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
578
aab2c27d
MM		 5792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5802019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
581
582 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
583 Armv8.6-A.
584 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
585 (neon_opcodes): Add bfloat SIMD instructions.
586 (print_insn_coprocessor): Add new control character %b to print
587 condition code without checking cp_num.
588 (print_insn_neon): Account for BFloat16 instructions that have no
589 special top-byte handling.
590
33593eaf
MM		 5912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5922019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
593
594 * arm-dis.c (print_insn_coprocessor,
595 print_insn_generic_coprocessor): Create wrapper functions around
596 the implementation of the print_insn_coprocessor control codes.
597 (print_insn_coprocessor_1): Original print_insn_coprocessor
598 function that now takes which array to look at as an argument.
599 (print_insn_arm): Use both print_insn_coprocessor and
600 print_insn_generic_coprocessor.
601 (print_insn_thumb32): As above.
602
df678013
MM		 6032019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6042019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
605
606 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
607 in reglane special case.
608 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
609 aarch64_find_next_opcode): Account for new instructions.
610 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
611 in reglane special case.
612 * aarch64-opc.c (struct operand_qualifier_data): Add data for
613 new AARCH64_OPND_QLF_S_2H qualifier.
614 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
615 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
616 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
617 sets.
618 (BFLOAT_SVE, BFLOAT): New feature set macros.
619 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
620 instructions.
621 (aarch64_opcode_table): Define new instructions bfdot,
622 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
623 bfcvtn2, bfcvt.
624
8ae2d3d9
MM		 6252019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6262019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
627
628 * aarch64-tbl.h (ARMV8_6): New macro.
629
142861df
JB		 6302019-11-07 Jan Beulich <jbeulich@suse.com>
631
632 * i386-dis.c (prefix_table): Add mcommit.
633 (rm_table): Add rdpru.
634 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
635 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
636 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
637 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
638 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
639 * i386-opc.tbl (mcommit, rdpru): New.
640 * i386-init.h, i386-tbl.h: Re-generate.
641
081e283f
JB		 6422019-11-07 Jan Beulich <jbeulich@suse.com>
643
644 * i386-dis.c (OP_Mwait): Drop local variable "names", use
645 "names32" instead.
646 (OP_Monitor): Drop local variable "op1_names", re-purpose
647 "names" for it instead, and replace former "names" uses by
648 "names32" ones.
649
c050c89a
JB		 6502019-11-07 Jan Beulich <jbeulich@suse.com>
651
652 PR/gas 25167
653 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
654 operand-less forms.
655 * opcodes/i386-tbl.h: Re-generate.
656
7abb8d81
JB		 6572019-11-05 Jan Beulich <jbeulich@suse.com>
658
659 * i386-dis.c (OP_Mwaitx): Delete.
660 (prefix_table): Use OP_Mwait for mwaitx entry.
661 (OP_Mwait): Also handle mwaitx.
662
267b8516
JB		 6632019-11-05 Jan Beulich <jbeulich@suse.com>
664
665 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
666 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
667 (prefix_table): Add respective entries.
668 (rm_table): Link to those entries.
669
f8687e93
JB		 6702019-11-05 Jan Beulich <jbeulich@suse.com>
671
672 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
673 (REG_0F1C_P_0_MOD_0): ... this.
674 (REG_0F1E_MOD_3): Rename to ...
675 (REG_0F1E_P_1_MOD_3): ... this.
676 (RM_0F01_REG_5): Rename to ...
677 (RM_0F01_REG_5_MOD_3): ... this.
678 (RM_0F01_REG_7): Rename to ...
679 (RM_0F01_REG_7_MOD_3): ... this.
680 (RM_0F1E_MOD_3_REG_7): Rename to ...
681 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
682 (RM_0FAE_REG_6): Rename to ...
683 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
684 (RM_0FAE_REG_7): Rename to ...
685 (RM_0FAE_REG_7_MOD_3): ... this.
686 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
687 (PREFIX_0F01_REG_5_MOD_0): ... this.
688 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
689 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
690 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
691 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
692 (PREFIX_0FAE_REG_0): Rename to ...
693 (PREFIX_0FAE_REG_0_MOD_3): ... this.
694 (PREFIX_0FAE_REG_1): Rename to ...
695 (PREFIX_0FAE_REG_1_MOD_3): ... this.
696 (PREFIX_0FAE_REG_2): Rename to ...
697 (PREFIX_0FAE_REG_2_MOD_3): ... this.
698 (PREFIX_0FAE_REG_3): Rename to ...
699 (PREFIX_0FAE_REG_3_MOD_3): ... this.
700 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
701 (PREFIX_0FAE_REG_4_MOD_0): ... this.
702 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
703 (PREFIX_0FAE_REG_4_MOD_3): ... this.
704 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
705 (PREFIX_0FAE_REG_5_MOD_0): ... this.
706 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
707 (PREFIX_0FAE_REG_5_MOD_3): ... this.
708 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
709 (PREFIX_0FAE_REG_6_MOD_0): ... this.
710 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
711 (PREFIX_0FAE_REG_6_MOD_3): ... this.
712 (PREFIX_0FAE_REG_7): Rename to ...
713 (PREFIX_0FAE_REG_7_MOD_0): ... this.
714 (PREFIX_MOD_0_0FC3): Rename to ...
715 (PREFIX_0FC3_MOD_0): ... this.
716 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
717 (PREFIX_0FC7_REG_6_MOD_0): ... this.
718 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
719 (PREFIX_0FC7_REG_6_MOD_3): ... this.
720 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
721 (PREFIX_0FC7_REG_7_MOD_3): ... this.
722 (reg_table, prefix_table, mod_table, rm_table): Adjust
723 accordingly.
724
5103274f
NC		 7252019-11-04 Nick Clifton <nickc@redhat.com>
726
727 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
728 of a v850 system register. Move the v850_sreg_names array into
729 this function.
730 (get_v850_reg_name): Likewise for ordinary register names.
731 (get_v850_vreg_name): Likewise for vector register names.
732 (get_v850_cc_name): Likewise for condition codes.
733 * get_v850_float_cc_name): Likewise for floating point condition
734 codes.
735 (get_v850_cacheop_name): Likewise for cache-ops.
736 (get_v850_prefop_name): Likewise for pref-ops.
737 (disassemble): Use the new accessor functions.
738
1820262b
DB		 7392019-10-30 Delia Burduv <delia.burduv@arm.com>
740
741 * aarch64-opc.c (print_immediate_offset_address): Don't print the
742 immediate for the writeback form of ldraa/ldrab if it is 0.
743 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
744 * aarch64-opc-2.c: Regenerated.
745
3cc17af5
JB		 7462019-10-30 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (operand_type_shorthands): Delete.
749 (operand_type_init): Expand previous shorthands.
750 (set_bitfield_from_shorthand): Rename back to ...
751 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
752 of operand_type_init[].
753 (set_bitfield): Adjust call to the above function.
754 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
755 RegXMM, RegYMM, RegZMM): Define.
756 * i386-reg.tbl: Expand prior shorthands.
757
a2cebd03
JB		 7582019-10-30 Jan Beulich <jbeulich@suse.com>
759
760 * i386-gen.c (output_i386_opcode): Change order of fields
761 emitted to output.
762 * i386-opc.h (struct insn_template): Move operands field.
763 Convert extension_opcode field to unsigned short.
764 * i386-tbl.h: Re-generate.
765
507916b8
JB		 7662019-10-30 Jan Beulich <jbeulich@suse.com>
767
768 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
769 of W.
770 * i386-opc.h (W): Extend comment.
771 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
772 general purpose variants not allowing for byte operands.
773 * i386-tbl.h: Re-generate.
774
efea62b4
NC		 7752019-10-29 Nick Clifton <nickc@redhat.com>
776
777 * tic30-dis.c (print_branch): Correct size of operand array.
778
9adb2591
NC		 7792019-10-29 Nick Clifton <nickc@redhat.com>
780
781 * d30v-dis.c (print_insn): Check that operand index is valid
782 before attempting to access the operands array.
783
993a00a9
NC		 7842019-10-29 Nick Clifton <nickc@redhat.com>
785
786 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
787 locating the bit to be tested.
788
66a66a17
NC		 7892019-10-29 Nick Clifton <nickc@redhat.com>
790
791 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
792 values.
793 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
794 (print_insn_s12z): Check for illegal size values.
795
1ee3542c
NC		 7962019-10-28 Nick Clifton <nickc@redhat.com>
797
798 * csky-dis.c (csky_chars_to_number): Check for a negative
799 count. Use an unsigned integer to construct the return value.
800
bbf9a0b5
NC		 8012019-10-28 Nick Clifton <nickc@redhat.com>
802
803 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
804 operand buffer. Set value to 15 not 13.
805 (get_register_operand): Use OPERAND_BUFFER_LEN.
806 (get_indirect_operand): Likewise.
807 (print_two_operand): Likewise.
808 (print_three_operand): Likewise.
809 (print_oar_insn): Likewise.
810
d1e304bc
NC		 8112019-10-28 Nick Clifton <nickc@redhat.com>
812
813 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
814 (bit_extract_simple): Likewise.
815 (bit_copy): Likewise.
816 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
817 index_offset array are not accessed.
818
dee33451
NC		 8192019-10-28 Nick Clifton <nickc@redhat.com>
820
821 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
822 operand.
823
27cee81d
NC		 8242019-10-25 Nick Clifton <nickc@redhat.com>
825
826 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
827 access to opcodes.op array element.
828
de6d8dc2
NC		 8292019-10-23 Nick Clifton <nickc@redhat.com>
830
831 * rx-dis.c (get_register_name): Fix spelling typo in error
832 message.
833 (get_condition_name, get_flag_name, get_double_register_name)
834 (get_double_register_high_name, get_double_register_low_name)
835 (get_double_control_register_name, get_double_condition_name)
836 (get_opsize_name, get_size_name): Likewise.
837
6207ed28
NC		 8382019-10-22 Nick Clifton <nickc@redhat.com>
839
840 * rx-dis.c (get_size_name): New function. Provides safe
841 access to name array.
842 (get_opsize_name): Likewise.
843 (print_insn_rx): Use the accessor functions.
844
12234dfd
NC		 8452019-10-16 Nick Clifton <nickc@redhat.com>
846
847 * rx-dis.c (get_register_name): New function. Provides safe
848 access to name array.
849 (get_condition_name, get_flag_name, get_double_register_name)
850 (get_double_register_high_name, get_double_register_low_name)
851 (get_double_control_register_name, get_double_condition_name):
852 Likewise.
853 (print_insn_rx): Use the accessor functions.
854
1d378749
NC		 8552019-10-09 Nick Clifton <nickc@redhat.com>
856
857 PR 25041
858 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
859 instructions.
860
d241b910
JB		 8612019-10-07 Jan Beulich <jbeulich@suse.com>
862
863 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
864 (cmpsd): Likewise. Move EsSeg to other operand.
865 * opcodes/i386-tbl.h: Re-generate.
866
f5c5b7c1
AM		 8672019-09-23 Alan Modra <amodra@gmail.com>
868
869 * m68k-dis.c: Include cpu-m68k.h
870
7beeaeb8
AM		 8712019-09-23 Alan Modra <amodra@gmail.com>
872
873 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
874 "elf/mips.h" earlier.
875
3f9aad11
JB		 8762018-09-20 Jan Beulich <jbeulich@suse.com>
877
878 PR gas/25012
879 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
880 with SReg operand.
881 * i386-tbl.h: Re-generate.
882
fd361982
AM		 8832019-09-18 Alan Modra <amodra@gmail.com>
884
885 * arc-ext.c: Update throughout for bfd section macro changes.
886
e0b2a78c
SM		 8872019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
888
889 * Makefile.in: Re-generate.
890 * configure: Re-generate.
891
7e9ad3a3
JW		 8922019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
893
894 * riscv-opc.c (riscv_opcodes): Change subset field
895 to insn_class field for all instructions.
896 (riscv_insn_types): Likewise.
897
bb695960
PB		 8982019-09-16 Phil Blundell <pb@pbcl.net>
899
900 * configure: Regenerated.
901
8063ab7e
MV		 9022019-09-10 Miod Vallat <miod@online.fr>
903
904 PR 24982
905 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
906
60391a25
PB		 9072019-09-09 Phil Blundell <pb@pbcl.net>
908
909 binutils 2.33 branch created.
910
f44b758d
NC		 9112019-09-03 Nick Clifton <nickc@redhat.com>
912
913 PR 24961
914 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
915 greater than zero before indexing via (bufcnt -1).
916
1e4b5e7d
NC		 9172019-09-03 Nick Clifton <nickc@redhat.com>
918
919 PR 24958
920 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
921 (MAX_SPEC_REG_NAME_LEN): Define.
922 (struct mmix_dis_info): Use defined constants for array lengths.
923 (get_reg_name): New function.
924 (get_sprec_reg_name): New function.
925 (print_insn_mmix): Use new functions.
926
c4a23bf8
SP		 9272019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
928
929 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
930 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
931 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
932
a051e2f3
KT		 9332019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
934
935 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
936 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
937 (aarch64_sys_reg_supported_p): Update checks for the above.
938
08132bdd
SP		 9392019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
940
941 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
942 cases MVE_SQRSHRL and MVE_UQRSHLL.
943 (print_insn_mve): Add case for specifier 'k' to check
944 specific bit of the instruction.
945
d88bdcb4
PA		 9462019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
947
948 PR 24854
949 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
950 encountering an unknown machine type.
951 (print_insn_arc): Handle arc_insn_length returning 0. In error
952 cases return -1 rather than calling abort.
953
bc750500
JB		 9542019-08-07 Jan Beulich <jbeulich@suse.com>
955
956 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
957 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
958 IgnoreSize.
959 * i386-tbl.h: Re-generate.
960
23d188c7
BW		 9612019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
962
963 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
964 instructions.
965
c0d6f62f
JW		 9662019-07-30 Mel Chen <mel.chen@sifive.com>
967
968 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
969 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
970
971 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
972 fscsr.
973
0f3f7167
CZ		 9742019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
975
976 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
977 and MPY class instructions.
978 (parse_option): Add nps400 option.
979 (print_arc_disassembler_options): Add nps400 info.
980
7e126ba3
CZ		 9812019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
982
983 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
984 (bspop): Likewise.
985 (modapp): Likewise.
986 * arc-opc.c (RAD_CHK): Add.
987 * arc-tbl.h: Regenerate.
988
a028026d
KT		 9892019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
990
991 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
992 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
993
ac79ff9e
NC		 9942019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
995
996 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
997 instructions as UNPREDICTABLE.
998
231097b0
JM		 9992019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1000
1001 * bpf-desc.c: Regenerated.
1002
1d942ae9
JB		 10032019-07-17 Jan Beulich <jbeulich@suse.com>
1004
1005 * i386-gen.c (static_assert): Define.
1006 (main): Use it.
1007 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1008 (Opcode_Modifier_Num): ... this.
1009 (Mem): Delete.
1010
dfd69174
JB		 10112019-07-16 Jan Beulich <jbeulich@suse.com>
1012
1013 * i386-gen.c (operand_types): Move RegMem ...
1014 (opcode_modifiers): ... here.
1015 * i386-opc.h (RegMem): Move to opcode modifer enum.
1016 (union i386_operand_type): Move regmem field ...
1017 (struct i386_opcode_modifier): ... here.
1018 * i386-opc.tbl (RegMem): Define.
1019 (mov, movq): Move RegMem on segment, control, debug, and test
1020 register flavors.
1021 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1022 to non-SSE2AVX flavor.
1023 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1024 Move RegMem on register only flavors. Drop IgnoreSize from
1025 legacy encoding flavors.
1026 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1027 flavors.
1028 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1029 register only flavors.
1030 (vmovd): Move RegMem and drop IgnoreSize on register only
1031 flavor. Change opcode and operand order to store form.
1032 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1033
21df382b
JB		 10342019-07-16 Jan Beulich <jbeulich@suse.com>
1035
1036 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1037 entries.
1038 * i386-opc.h (SReg2, SReg3): Replace by ...
1039 (SReg): ... this.
1040 (union i386_operand_type): Replace sreg fields.
1041 * i386-opc.tbl (mov, ): Use SReg.
1042 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1043 register flavors.
1044 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1045 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1046
3719fd55
JM		 10472019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1048
1049 * bpf-desc.c: Regenerate.
1050 * bpf-opc.c: Likewise.
1051 * bpf-opc.h: Likewise.
1052
92434a14
JM		 10532019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1054
1055 * bpf-desc.c: Regenerate.
1056 * bpf-opc.c: Likewise.
1057
43dd7626
HPN		 10582019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1059
1060 * arm-dis.c (print_insn_coprocessor): Rename index to
1061 index_operand.
1062
98602811
JW		 10632019-07-05 Kito Cheng <kito.cheng@sifive.com>
1064
1065 * riscv-opc.c (riscv_insn_types): Add r4 type.
1066
1067 * riscv-opc.c (riscv_insn_types): Add b and j type.
1068
1069 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1070 format for sb type and correct s type.
1071
01c1ee4a
RS		 10722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1073
1074 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1075 SVE FMOV alias of FCPY.
1076
83adff69
RS		 10772019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1078
1079 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1080 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1081
89418844
RS		 10822019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1083
1084 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1085 registers in an instruction prefixed by MOVPRFX.
1086
41be57ca
MM		 10872019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1088
1089 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1090 sve_size_13 icode to account for variant behaviour of
1091 pmull{t,b}.
1092 * aarch64-dis-2.c: Regenerate.
1093 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1094 sve_size_13 icode to account for variant behaviour of
1095 pmull{t,b}.
1096 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1097 (OP_SVE_VVV_Q_D): Add new qualifier.
1098 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1099 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1100 AES and those not.
1101
9d3bf266
JB		 11022019-07-01 Jan Beulich <jbeulich@suse.com>
1103
1104 * opcodes/i386-gen.c (operand_type_init): Remove
1105 OPERAND_TYPE_VEC_IMM4 entry.
1106 (operand_types): Remove Vec_Imm4.
1107 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1108 (union i386_operand_type): Remove vec_imm4.
1109 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1110 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1111
c3949f43
JB		 11122019-07-01 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1115 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1116 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1117 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1118 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1119 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1120 * i386-tbl.h: Re-generate.
1121
5641ec01
JB		 11222019-07-01 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1125 register operands.
1126 * i386-tbl.h: Re-generate.
1127
79dec6b7
JB		 11282019-07-01 Jan Beulich <jbeulich@suse.com>
1129
1130 * i386-opc.tbl (C): New.
1131 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1132 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1133 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1134 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1135 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1136 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1137 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1138 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1139 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1140 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1141 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1142 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1143 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1144 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1145 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1146 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1147 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1148 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1149 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1150 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1151 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1152 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1153 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1154 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1155 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1156 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1157 flavors.
1158 * i386-tbl.h: Re-generate.
1159
a0a1771e
JB		 11602019-07-01 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1163 register operands.
1164 * i386-tbl.h: Re-generate.
1165
cd546e7b
JB		 11662019-07-01 Jan Beulich <jbeulich@suse.com>
1167
1168 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1169 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1170 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1171 * i386-tbl.h: Re-generate.
1172
e3bba3fc
JB		 11732019-07-01 Jan Beulich <jbeulich@suse.com>
1174
1175 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1176 Disp8MemShift from register only templates.
1177 * i386-tbl.h: Re-generate.
1178
36cc073e
JB		 11792019-07-01 Jan Beulich <jbeulich@suse.com>
1180
1181 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1182 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1183 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1184 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1185 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1186 EVEX_W_0F11_P_3_M_1): Delete.
1187 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1188 EVEX_W_0F11_P_3): New.
1189 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1190 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1191 MOD_EVEX_0F11_PREFIX_3 table entries.
1192 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1193 PREFIX_EVEX_0F11 table entries.
1194 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1195 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1196 EVEX_W_0F11_P_3_M_{0,1} table entries.
1197
219920a7
JB		 11982019-07-01 Jan Beulich <jbeulich@suse.com>
1199
1200 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1201 Delete.
1202
e395f487
L		 12032019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1204
1205 PR binutils/24719
1206 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1207 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1208 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1209 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1210 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1211 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1212 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1213 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1214 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1215 PREFIX_EVEX_0F38C6_REG_6 entries.
1216 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1217 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1218 EVEX_W_0F38C7_R_6_P_2 entries.
1219 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1220 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1221 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1222 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1223 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1224 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1225 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1226
2b7bcc87
JB		 12272019-06-27 Jan Beulich <jbeulich@suse.com>
1228
1229 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1230 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1231 VEX_LEN_0F2D_P_3): Delete.
1232 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1233 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1234 (prefix_table): ... here.
1235
c1dc7af5
JB		 12362019-06-27 Jan Beulich <jbeulich@suse.com>
1237
1238 * i386-dis.c (Iq): Delete.
1239 (Id): New.
1240 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1241 TBM insns.
1242 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1243 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1244 (OP_E_memory): Also honor needindex when deciding whether an
1245 address size prefix needs printing.
1246 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1247
d7560e2d
JW		 12482019-06-26 Jim Wilson <jimw@sifive.com>
1249
1250 PR binutils/24739
1251 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1252 Set info->display_endian to info->endian_code.
1253
2c703856
JB		 12542019-06-25 Jan Beulich <jbeulich@suse.com>
1255
1256 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1257 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1258 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1259 OPERAND_TYPE_ACC64 entries.
1260 * i386-init.h: Re-generate.
1261
54fbadc0
JB		 12622019-06-25 Jan Beulich <jbeulich@suse.com>
1263
1264 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1265 Delete.
1266 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1267 of dqa_mode.
1268 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1269 entries here.
1270 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1271 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1272
a280ab8e
JB		 12732019-06-25 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1276 variables.
1277
e1a1babd
JB		 12782019-06-25 Jan Beulich <jbeulich@suse.com>
1279
1280 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1281 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1282 movnti.
d7560e2d 1283 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1284 * i386-tbl.h: Re-generate.
1285
b8364fa7
JB		 12862019-06-25 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1289 * i386-tbl.h: Re-generate.
1290
ad692897
L		 12912019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1292
1293 * i386-dis-evex.h: Break into ...
1294 * i386-dis-evex-len.h: New file.
1295 * i386-dis-evex-mod.h: Likewise.
1296 * i386-dis-evex-prefix.h: Likewise.
1297 * i386-dis-evex-reg.h: Likewise.
1298 * i386-dis-evex-w.h: Likewise.
1299 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1300 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1301 i386-dis-evex-mod.h.
1302
f0a6222e
L		 13032019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1304
1305 PR binutils/24700
1306 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1307 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1308 EVEX_W_0F385B_P_2.
1309 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1310 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1311 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1312 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1313 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1314 EVEX_LEN_0F385B_P_2_W_1.
1315 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1316 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1317 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1318 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1319 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1320 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1321 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1322 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1323 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1324 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1325
6e1c90b7
L		 13262019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1327
1328 PR binutils/24691
1329 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1330 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1331 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1332 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1333 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1334 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1335 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1336 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1337 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1338 EVEX_LEN_0F3A43_P_2_W_1.
1339 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1340 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1341 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1342 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1343 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1344 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1345 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1346 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1347 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1348 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1349 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1350 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1351
bcc5a6eb
NC		 13522019-06-14 Nick Clifton <nickc@redhat.com>
1353
1354 * po/fr.po; Updated French translation.
1355
e4c4ac46
SH		 13562019-06-13 Stafford Horne <shorne@gmail.com>
1357
1358 * or1k-asm.c: Regenerated.
1359 * or1k-desc.c: Regenerated.
1360 * or1k-desc.h: Regenerated.
1361 * or1k-dis.c: Regenerated.
1362 * or1k-ibld.c: Regenerated.
1363 * or1k-opc.c: Regenerated.
1364 * or1k-opc.h: Regenerated.
1365 * or1k-opinst.c: Regenerated.
1366
a0e44ef5
PB		 13672019-06-12 Peter Bergner <bergner@linux.ibm.com>
1368
1369 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1370
12efd68d
L		 13712019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1372
1373 PR binutils/24633
1374 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1375 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1376 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1377 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1378 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1379 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1380 EVEX_LEN_0F3A1B_P_2_W_1.
1381 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1382 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1383 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1384 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1385 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1386 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1387 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1388 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1389
63c6fc6c
L		 13902019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1391
1392 PR binutils/24626
1393 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1394 EVEX.vvvv when disassembling VEX and EVEX instructions.
1395 (OP_VEX): Set vex.register_specifier to 0 after readding
1396 vex.register_specifier.
1397 (OP_Vex_2src_1): Likewise.
1398 (OP_Vex_2src_2): Likewise.
1399 (OP_LWP_E): Likewise.
1400 (OP_EX_Vex): Don't check vex.register_specifier.
1401 (OP_XMM_Vex): Likewise.
1402
9186c494
L		 14032019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1404 Lili Cui <lili.cui@intel.com>
1405
1406 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1407 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1408 instructions.
1409 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1410 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1411 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1412 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1413 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1414 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1415 * i386-init.h: Regenerated.
1416 * i386-tbl.h: Likewise.
1417
5d79adc4
L		 14182019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1419 Lili Cui <lili.cui@intel.com>
1420
1421 * doc/c-i386.texi: Document enqcmd.
1422 * testsuite/gas/i386/enqcmd-intel.d: New file.
1423 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1424 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1425 * testsuite/gas/i386/enqcmd.d: Likewise.
1426 * testsuite/gas/i386/enqcmd.s: Likewise.
1427 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1428 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1429 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1430 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1431 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1432 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1433 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1434 and x86-64-enqcmd.
1435
a9d96ab9
AH		 14362019-06-04 Alan Hayward <alan.hayward@arm.com>
1437
1438 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1439
4f6d070a
AM		 14402019-06-03 Alan Modra <amodra@gmail.com>
1441
1442 * ppc-dis.c (prefix_opcd_indices): Correct size.
1443
a2f4b66c
L		 14442019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1445
1446 PR gas/24625
1447 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1448 Disp8ShiftVL.
1449 * i386-tbl.h: Regenerated.
1450
405b5bd8
AM		 14512019-05-24 Alan Modra <amodra@gmail.com>
1452
1453 * po/POTFILES.in: Regenerate.
1454
8acf1435
PB		 14552019-05-24 Peter Bergner <bergner@linux.ibm.com>
1456 Alan Modra <amodra@gmail.com>
1457
1458 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1459 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1460 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1461 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1462 XTOP>): Define and add entries.
1463 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1464 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1465 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1466 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1467
dd7efa79
PB		 14682019-05-24 Peter Bergner <bergner@linux.ibm.com>
1469 Alan Modra <amodra@gmail.com>
1470
1471 * ppc-dis.c (ppc_opts): Add "future" entry.
1472 (PREFIX_OPCD_SEGS): Define.
1473 (prefix_opcd_indices): New array.
1474 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1475 (lookup_prefix): New function.
1476 (print_insn_powerpc): Handle 64-bit prefix instructions.
1477 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1478 (PMRR, POWERXX): Define.
1479 (prefix_opcodes): New instruction table.
1480 (prefix_num_opcodes): New constant.
1481
79472b45
JM		 14822019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1483
1484 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1485 * configure: Regenerated.
1486 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1487 and cpu/bpf.opc.
1488 (HFILES): Add bpf-desc.h and bpf-opc.h.
1489 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1490 bpf-ibld.c and bpf-opc.c.
1491 (BPF_DEPS): Define.
1492 * Makefile.in: Regenerated.
1493 * disassemble.c (ARCH_bpf): Define.
1494 (disassembler): Add case for bfd_arch_bpf.
1495 (disassemble_init_for_target): Likewise.
1496 (enum epbf_isa_attr): Define.
1497 * disassemble.h: extern print_insn_bpf.
1498 * bpf-asm.c: Generated.
1499 * bpf-opc.h: Likewise.
1500 * bpf-opc.c: Likewise.
1501 * bpf-ibld.c: Likewise.
1502 * bpf-dis.c: Likewise.
1503 * bpf-desc.h: Likewise.
1504 * bpf-desc.c: Likewise.
1505
ba6cd17f
SD		 15062019-05-21 Sudakshina Das <sudi.das@arm.com>
1507
1508 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1509 and VMSR with the new operands.
1510
e39c1607
SD		 15112019-05-21 Sudakshina Das <sudi.das@arm.com>
1512
1513 * arm-dis.c (enum mve_instructions): New enum
1514 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1515 and cneg.
1516 (mve_opcodes): New instructions as above.
1517 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1518 csneg and csel.
1519 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1520
23d00a41
SD		 15212019-05-21 Sudakshina Das <sudi.das@arm.com>
1522
1523 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1524 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1525 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1526 uqshl, urshrl and urshr.
1527 (is_mve_okay_in_it): Add new instructions to TRUE list.
1528 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1529 (print_insn_mve): Updated to accept new %j,
1530 %<bitfield>m and %<bitfield>n patterns.
1531
cd4797ee
FS		 15322019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1533
1534 * mips-opc.c (mips_builtin_opcodes): Change source register
1535 constraint for DAUI.
1536
999b073b
NC		 15372019-05-20 Nick Clifton <nickc@redhat.com>
1538
1539 * po/fr.po: Updated French translation.
1540
14b456f2
AV		 15412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1542 Michael Collison <michael.collison@arm.com>
1543
1544 * arm-dis.c (thumb32_opcodes): Add new instructions.
1545 (enum mve_instructions): Likewise.
1546 (enum mve_undefined): Add new reasons.
1547 (is_mve_encoding_conflict): Handle new instructions.
1548 (is_mve_undefined): Likewise.
1549 (is_mve_unpredictable): Likewise.
1550 (print_mve_undefined): Likewise.
1551 (print_mve_size): Likewise.
1552
f49bb598
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (thumb32_opcodes): Add new instructions.
1557 (enum mve_instructions): Likewise.
1558 (is_mve_encoding_conflict): Handle new instructions.
1559 (is_mve_undefined): Likewise.
1560 (is_mve_unpredictable): Likewise.
1561 (print_mve_size): Likewise.
1562
56858bea
AV		 15632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1564 Michael Collison <michael.collison@arm.com>
1565
1566 * arm-dis.c (thumb32_opcodes): Add new instructions.
1567 (enum mve_instructions): Likewise.
1568 (is_mve_encoding_conflict): Likewise.
1569 (is_mve_unpredictable): Likewise.
1570 (print_mve_size): Likewise.
1571
e523f101
AV		 15722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1573 Michael Collison <michael.collison@arm.com>
1574
1575 * arm-dis.c (thumb32_opcodes): Add new instructions.
1576 (enum mve_instructions): Likewise.
1577 (is_mve_encoding_conflict): Handle new instructions.
1578 (is_mve_undefined): Likewise.
1579 (is_mve_unpredictable): Likewise.
1580 (print_mve_size): Likewise.
1581
66dcaa5d
AV		 15822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1583 Michael Collison <michael.collison@arm.com>
1584
1585 * arm-dis.c (thumb32_opcodes): Add new instructions.
1586 (enum mve_instructions): Likewise.
1587 (is_mve_encoding_conflict): Handle new instructions.
1588 (is_mve_undefined): Likewise.
1589 (is_mve_unpredictable): Likewise.
1590 (print_mve_size): Likewise.
1591 (print_insn_mve): Likewise.
1592
d052b9b7
AV		 15932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1594 Michael Collison <michael.collison@arm.com>
1595
1596 * arm-dis.c (thumb32_opcodes): Add new instructions.
1597 (print_insn_thumb32): Handle new instructions.
1598
ed63aa17
AV		 15992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1600 Michael Collison <michael.collison@arm.com>
1601
1602 * arm-dis.c (enum mve_instructions): Add new instructions.
1603 (enum mve_undefined): Add new reasons.
1604 (is_mve_encoding_conflict): Handle new instructions.
1605 (is_mve_undefined): Likewise.
1606 (is_mve_unpredictable): Likewise.
1607 (print_mve_undefined): Likewise.
1608 (print_mve_size): Likewise.
1609 (print_mve_shift_n): Likewise.
1610 (print_insn_mve): Likewise.
1611
897b9bbc
AV		 16122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1613 Michael Collison <michael.collison@arm.com>
1614
1615 * arm-dis.c (enum mve_instructions): Add new instructions.
1616 (is_mve_encoding_conflict): Handle new instructions.
1617 (is_mve_unpredictable): Likewise.
1618 (print_mve_rotate): Likewise.
1619 (print_mve_size): Likewise.
1620 (print_insn_mve): Likewise.
1621
1c8f2df8
AV		 16222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1623 Michael Collison <michael.collison@arm.com>
1624
1625 * arm-dis.c (enum mve_instructions): Add new instructions.
1626 (is_mve_encoding_conflict): Handle new instructions.
1627 (is_mve_unpredictable): Likewise.
1628 (print_mve_size): Likewise.
1629 (print_insn_mve): Likewise.
1630
d3b63143
AV		 16312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1632 Michael Collison <michael.collison@arm.com>
1633
1634 * arm-dis.c (enum mve_instructions): Add new instructions.
1635 (enum mve_undefined): Add new reasons.
1636 (is_mve_encoding_conflict): Handle new instructions.
1637 (is_mve_undefined): Likewise.
1638 (is_mve_unpredictable): Likewise.
1639 (print_mve_undefined): Likewise.
1640 (print_mve_size): Likewise.
1641 (print_insn_mve): Likewise.
1642
14925797
AV		 16432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1644 Michael Collison <michael.collison@arm.com>
1645
1646 * arm-dis.c (enum mve_instructions): Add new instructions.
1647 (is_mve_encoding_conflict): Handle new instructions.
1648 (is_mve_undefined): Likewise.
1649 (is_mve_unpredictable): Likewise.
1650 (print_mve_size): Likewise.
1651 (print_insn_mve): Likewise.
1652
c507f10b
AV		 16532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1654 Michael Collison <michael.collison@arm.com>
1655
1656 * arm-dis.c (enum mve_instructions): Add new instructions.
1657 (enum mve_unpredictable): Add new reasons.
1658 (enum mve_undefined): Likewise.
1659 (is_mve_okay_in_it): Handle new isntructions.
1660 (is_mve_encoding_conflict): Likewise.
1661 (is_mve_undefined): Likewise.
1662 (is_mve_unpredictable): Likewise.
1663 (print_mve_vmov_index): Likewise.
1664 (print_simd_imm8): Likewise.
1665 (print_mve_undefined): Likewise.
1666 (print_mve_unpredictable): Likewise.
1667 (print_mve_size): Likewise.
1668 (print_insn_mve): Likewise.
1669
bf0b396d
AV		 16702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1671 Michael Collison <michael.collison@arm.com>
1672
1673 * arm-dis.c (enum mve_instructions): Add new instructions.
1674 (enum mve_unpredictable): Add new reasons.
1675 (enum mve_undefined): Likewise.
1676 (is_mve_encoding_conflict): Handle new instructions.
1677 (is_mve_undefined): Likewise.
1678 (is_mve_unpredictable): Likewise.
1679 (print_mve_undefined): Likewise.
1680 (print_mve_unpredictable): Likewise.
1681 (print_mve_rounding_mode): Likewise.
1682 (print_mve_vcvt_size): Likewise.
1683 (print_mve_size): Likewise.
1684 (print_insn_mve): Likewise.
1685
ef1576a1
AV		 16862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1687 Michael Collison <michael.collison@arm.com>
1688
1689 * arm-dis.c (enum mve_instructions): Add new instructions.
1690 (enum mve_unpredictable): Add new reasons.
1691 (enum mve_undefined): Likewise.
1692 (is_mve_undefined): Handle new instructions.
1693 (is_mve_unpredictable): Likewise.
1694 (print_mve_undefined): Likewise.
1695 (print_mve_unpredictable): Likewise.
1696 (print_mve_size): Likewise.
1697 (print_insn_mve): Likewise.
1698
aef6d006
AV		 16992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1700 Michael Collison <michael.collison@arm.com>
1701
1702 * arm-dis.c (enum mve_instructions): Add new instructions.
1703 (enum mve_undefined): Add new reasons.
1704 (insns): Add new instructions.
1705 (is_mve_encoding_conflict):
1706 (print_mve_vld_str_addr): New print function.
1707 (is_mve_undefined): Handle new instructions.
1708 (is_mve_unpredictable): Likewise.
1709 (print_mve_undefined): Likewise.
1710 (print_mve_size): Likewise.
1711 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1712 (print_insn_mve): Handle new operands.
1713
04d54ace
AV		 17142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1715 Michael Collison <michael.collison@arm.com>
1716
1717 * arm-dis.c (enum mve_instructions): Add new instructions.
1718 (enum mve_unpredictable): Add new reasons.
1719 (is_mve_encoding_conflict): Handle new instructions.
1720 (is_mve_unpredictable): Likewise.
1721 (mve_opcodes): Add new instructions.
1722 (print_mve_unpredictable): Handle new reasons.
1723 (print_mve_register_blocks): New print function.
1724 (print_mve_size): Handle new instructions.
1725 (print_insn_mve): Likewise.
1726
9743db03
AV		 17272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1728 Michael Collison <michael.collison@arm.com>
1729
1730 * arm-dis.c (enum mve_instructions): Add new instructions.
1731 (enum mve_unpredictable): Add new reasons.
1732 (enum mve_undefined): Likewise.
1733 (is_mve_encoding_conflict): Handle new instructions.
1734 (is_mve_undefined): Likewise.
1735 (is_mve_unpredictable): Likewise.
1736 (coprocessor_opcodes): Move NEON VDUP from here...
1737 (neon_opcodes): ... to here.
1738 (mve_opcodes): Add new instructions.
1739 (print_mve_undefined): Handle new reasons.
1740 (print_mve_unpredictable): Likewise.
1741 (print_mve_size): Handle new instructions.
1742 (print_insn_neon): Handle vdup.
1743 (print_insn_mve): Handle new operands.
1744
143275ea
AV		 17452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1746 Michael Collison <michael.collison@arm.com>
1747
1748 * arm-dis.c (enum mve_instructions): Add new instructions.
1749 (enum mve_unpredictable): Add new values.
1750 (mve_opcodes): Add new instructions.
1751 (vec_condnames): New array with vector conditions.
1752 (mve_predicatenames): New array with predicate suffixes.
1753 (mve_vec_sizename): New array with vector sizes.
1754 (enum vpt_pred_state): New enum with vector predication states.
1755 (struct vpt_block): New struct type for vpt blocks.
1756 (vpt_block_state): Global struct to keep track of state.
1757 (mve_extract_pred_mask): New helper function.
1758 (num_instructions_vpt_block): Likewise.
1759 (mark_outside_vpt_block): Likewise.
1760 (mark_inside_vpt_block): Likewise.
1761 (invert_next_predicate_state): Likewise.
1762 (update_next_predicate_state): Likewise.
1763 (update_vpt_block_state): Likewise.
1764 (is_vpt_instruction): Likewise.
1765 (is_mve_encoding_conflict): Add entries for new instructions.
1766 (is_mve_unpredictable): Likewise.
1767 (print_mve_unpredictable): Handle new cases.
1768 (print_instruction_predicate): Likewise.
1769 (print_mve_size): New function.
1770 (print_vec_condition): New function.
1771 (print_insn_mve): Handle vpt blocks and new print operands.
1772
f08d8ce3
AV		 17732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1774
1775 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1776 8, 14 and 15 for Armv8.1-M Mainline.
1777
73cd51e5
AV		 17782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1779 Michael Collison <michael.collison@arm.com>
1780
1781 * arm-dis.c (enum mve_instructions): New enum.
1782 (enum mve_unpredictable): Likewise.
1783 (enum mve_undefined): Likewise.
1784 (struct mopcode32): New struct.
1785 (is_mve_okay_in_it): New function.
1786 (is_mve_architecture): Likewise.
1787 (arm_decode_field): Likewise.
1788 (arm_decode_field_multiple): Likewise.
1789 (is_mve_encoding_conflict): Likewise.
1790 (is_mve_undefined): Likewise.
1791 (is_mve_unpredictable): Likewise.
1792 (print_mve_undefined): Likewise.
1793 (print_mve_unpredictable): Likewise.
1794 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1795 (print_insn_mve): New function.
1796 (print_insn_thumb32): Handle MVE architecture.
1797 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1798
3076e594
NC		 17992019-05-10 Nick Clifton <nickc@redhat.com>
1800
1801 PR 24538
1802 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1803 end of the table prematurely.
1804
387e7624
FS		 18052019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1806
1807 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1808 macros for R6.
1809
0067be51
AM		 18102019-05-11 Alan Modra <amodra@gmail.com>
1811
1812 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1813 when -Mraw is in effect.
1814
42e6288f
MM		 18152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1816
1817 * aarch64-dis-2.c: Regenerate.
1818 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1819 (OP_SVE_BBB): New variant set.
1820 (OP_SVE_DDDD): New variant set.
1821 (OP_SVE_HHH): New variant set.
1822 (OP_SVE_HHHU): New variant set.
1823 (OP_SVE_SSS): New variant set.
1824 (OP_SVE_SSSU): New variant set.
1825 (OP_SVE_SHH): New variant set.
1826 (OP_SVE_SBBU): New variant set.
1827 (OP_SVE_DSS): New variant set.
1828 (OP_SVE_DHHU): New variant set.
1829 (OP_SVE_VMV_HSD_BHS): New variant set.
1830 (OP_SVE_VVU_HSD_BHS): New variant set.
1831 (OP_SVE_VVVU_SD_BH): New variant set.
1832 (OP_SVE_VVVU_BHSD): New variant set.
1833 (OP_SVE_VVV_QHD_DBS): New variant set.
1834 (OP_SVE_VVV_HSD_BHS): New variant set.
1835 (OP_SVE_VVV_HSD_BHS2): New variant set.
1836 (OP_SVE_VVV_BHS_HSD): New variant set.
1837 (OP_SVE_VV_BHS_HSD): New variant set.
1838 (OP_SVE_VVV_SD): New variant set.
1839 (OP_SVE_VVU_BHS_HSD): New variant set.
1840 (OP_SVE_VZVV_SD): New variant set.
1841 (OP_SVE_VZVV_BH): New variant set.
1842 (OP_SVE_VZV_SD): New variant set.
1843 (aarch64_opcode_table): Add sve2 instructions.
1844
28ed815a
MM		 18452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1846
1847 * aarch64-asm-2.c: Regenerated.
1848 * aarch64-dis-2.c: Regenerated.
1849 * aarch64-opc-2.c: Regenerated.
1850 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1851 for SVE_SHLIMM_UNPRED_22.
1852 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1853 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1854 operand.
1855
fd1dc4a0
MM		 18562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1857
1858 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1859 sve_size_tsz_bhs iclass encode.
1860 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1861 sve_size_tsz_bhs iclass decode.
1862
31e36ab3
MM		 18632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1864
1865 * aarch64-asm-2.c: Regenerated.
1866 * aarch64-dis-2.c: Regenerated.
1867 * aarch64-opc-2.c: Regenerated.
1868 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1869 for SVE_Zm4_11_INDEX.
1870 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1871 (fields): Handle SVE_i2h field.
1872 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1873 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1874
1be5f94f
MM		 18752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1876
1877 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1878 sve_shift_tsz_bhsd iclass encode.
1879 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1880 sve_shift_tsz_bhsd iclass decode.
1881
3c17238b
MM		 18822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1883
1884 * aarch64-asm-2.c: Regenerated.
1885 * aarch64-dis-2.c: Regenerated.
1886 * aarch64-opc-2.c: Regenerated.
1887 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1888 (aarch64_encode_variant_using_iclass): Handle
1889 sve_shift_tsz_hsd iclass encode.
1890 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1891 sve_shift_tsz_hsd iclass decode.
1892 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1893 for SVE_SHRIMM_UNPRED_22.
1894 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1895 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1896 operand.
1897
cd50a87a
MM		 18982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1899
1900 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1901 sve_size_013 iclass encode.
1902 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1903 sve_size_013 iclass decode.
1904
3c705960
MM		 19052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1906
1907 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1908 sve_size_bh iclass encode.
1909 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1910 sve_size_bh iclass decode.
1911
0a57e14f
MM		 19122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1913
1914 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1915 sve_size_sd2 iclass encode.
1916 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1917 sve_size_sd2 iclass decode.
1918 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1919 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1920
c469c864
MM		 19212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1922
1923 * aarch64-asm-2.c: Regenerated.
1924 * aarch64-dis-2.c: Regenerated.
1925 * aarch64-opc-2.c: Regenerated.
1926 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1927 for SVE_ADDR_ZX.
1928 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1929 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1930
116adc27
MM		 19312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1932
1933 * aarch64-asm-2.c: Regenerated.
1934 * aarch64-dis-2.c: Regenerated.
1935 * aarch64-opc-2.c: Regenerated.
1936 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1937 for SVE_Zm3_11_INDEX.
1938 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1939 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1940 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1941 fields.
1942 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1943
3bd82c86
MM		 19442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1945
1946 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1947 sve_size_hsd2 iclass encode.
1948 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1949 sve_size_hsd2 iclass decode.
1950 * aarch64-opc.c (fields): Handle SVE_size field.
1951 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1952
adccc507
MM		 19532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1954
1955 * aarch64-asm-2.c: Regenerated.
1956 * aarch64-dis-2.c: Regenerated.
1957 * aarch64-opc-2.c: Regenerated.
1958 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1959 for SVE_IMM_ROT3.
1960 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1961 (fields): Handle SVE_rot3 field.
1962 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1963 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1964
5cd99750
MM		 19652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1966
1967 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1968 instructions.
1969
7ce2460a
MM		 19702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1971
1972 * aarch64-tbl.h
1973 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1974 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1975 aarch64_feature_sve2bitperm): New feature sets.
1976 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1977 for feature set addresses.
1978 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1979 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1980
41cee089
FS		 19812019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1982 Faraz Shahbazker <fshahbazker@wavecomp.com>
1983
1984 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1985 argument and set ASE_EVA_R6 appropriately.
1986 (set_default_mips_dis_options): Pass ISA to above.
1987 (parse_mips_dis_option): Likewise.
1988 * mips-opc.c (EVAR6): New macro.
1989 (mips_builtin_opcodes): Add llwpe, scwpe.
1990
b83b4b13
SD		 19912019-05-01 Sudakshina Das <sudi.das@arm.com>
1992
1993 * aarch64-asm-2.c: Regenerated.
1994 * aarch64-dis-2.c: Regenerated.
1995 * aarch64-opc-2.c: Regenerated.
1996 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1997 AARCH64_OPND_TME_UIMM16.
1998 (aarch64_print_operand): Likewise.
1999 * aarch64-tbl.h (QL_IMM_NIL): New.
2000 (TME): New.
2001 (_TME_INSN): New.
2002 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2003
4a90ce95
JD		 20042019-04-29 John Darrington <john@darrington.wattle.id.au>
2005
2006 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2007
a45328b9
AB		 20082019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2009 Faraz Shahbazker <fshahbazker@wavecomp.com>
2010
2011 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2012
d10be0cb
JD		 20132019-04-24 John Darrington <john@darrington.wattle.id.au>
2014
2015 * s12z-opc.h: Add extern "C" bracketing to help
2016 users who wish to use this interface in c++ code.
2017
a679f24e
JD		 20182019-04-24 John Darrington <john@darrington.wattle.id.au>
2019
2020 * s12z-opc.c (bm_decode): Handle bit map operations with the
2021 "reserved0" mode.
2022
32c36c3c
AV		 20232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2024
2025 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2026 specifier. Add entries for VLDR and VSTR of system registers.
2027 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2028 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2029 of %J and %K format specifier.
2030
efd6b359
AV		 20312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2032
2033 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2034 Add new entries for VSCCLRM instruction.
2035 (print_insn_coprocessor): Handle new %C format control code.
2036
6b0dd094
AV		 20372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2038
2039 * arm-dis.c (enum isa): New enum.
2040 (struct sopcode32): New structure.
2041 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2042 set isa field of all current entries to ANY.
2043 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2044 Only match an entry if its isa field allows the current mode.
2045
4b5a202f
AV		 20462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2047
2048 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2049 CLRM.
2050 (print_insn_thumb32): Add logic to print %n CLRM register list.
2051
60f993ce
AV		 20522019-04-15 Sudakshina Das <sudi.das@arm.com>
2053
2054 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2055 and %Q patterns.
2056
f6b2b12d
AV		 20572019-04-15 Sudakshina Das <sudi.das@arm.com>
2058
2059 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2060 (print_insn_thumb32): Edit the switch case for %Z.
2061
1889da70
AV		 20622019-04-15 Sudakshina Das <sudi.das@arm.com>
2063
2064 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2065
65d1bc05
AV		 20662019-04-15 Sudakshina Das <sudi.das@arm.com>
2067
2068 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2069
1caf72a5
AV		 20702019-04-15 Sudakshina Das <sudi.das@arm.com>
2071
2072 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2073
f1c7f421
AV		 20742019-04-15 Sudakshina Das <sudi.das@arm.com>
2075
2076 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2077 Arm register with r13 and r15 unpredictable.
2078 (thumb32_opcodes): New instructions for bfx and bflx.
2079
4389b29a
AV		 20802019-04-15 Sudakshina Das <sudi.das@arm.com>
2081
2082 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2083
e5d6e09e
AV		 20842019-04-15 Sudakshina Das <sudi.das@arm.com>
2085
2086 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2087
e12437dc
AV		 20882019-04-15 Sudakshina Das <sudi.das@arm.com>
2089
2090 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2091
031254f2
AV		 20922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2093
2094 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2095
e5a557ac
JD		 20962019-04-12 John Darrington <john@darrington.wattle.id.au>
2097
2098 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2099 "optr". ("operator" is a reserved word in c++).
2100
bd7ceb8d
SD		 21012019-04-11 Sudakshina Das <sudi.das@arm.com>
2102
2103 * aarch64-opc.c (aarch64_print_operand): Add case for
2104 AARCH64_OPND_Rt_SP.
2105 (verify_constraints): Likewise.
2106 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2107 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2108 to accept Rt|SP as first operand.
2109 (AARCH64_OPERANDS): Add new Rt_SP.
2110 * aarch64-asm-2.c: Regenerated.
2111 * aarch64-dis-2.c: Regenerated.
2112 * aarch64-opc-2.c: Regenerated.
2113
e54010f1
SD		 21142019-04-11 Sudakshina Das <sudi.das@arm.com>
2115
2116 * aarch64-asm-2.c: Regenerated.
2117 * aarch64-dis-2.c: Likewise.
2118 * aarch64-opc-2.c: Likewise.
2119 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2120
7e96e219
RS		 21212019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2122
2123 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2124
6f2791d5
L		 21252019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2126
2127 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2128 * i386-init.h: Regenerated.
2129
e392bad3
AM		 21302019-04-07 Alan Modra <amodra@gmail.com>
2131
2132 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2133 op_separator to control printing of spaces, comma and parens
2134 rather than need_comma, need_paren and spaces vars.
2135
dffaa15c
AM		 21362019-04-07 Alan Modra <amodra@gmail.com>
2137
2138 PR 24421
2139 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2140 (print_insn_neon, print_insn_arm): Likewise.
2141
d6aab7a1
XG		 21422019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2143
2144 * i386-dis-evex.h (evex_table): Updated to support BF16
2145 instructions.
2146 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2147 and EVEX_W_0F3872_P_3.
2148 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2149 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2150 * i386-opc.h (enum): Add CpuAVX512_BF16.
2151 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2152 * i386-opc.tbl: Add AVX512 BF16 instructions.
2153 * i386-init.h: Regenerated.
2154 * i386-tbl.h: Likewise.
2155
66e85460
AM		 21562019-04-05 Alan Modra <amodra@gmail.com>
2157
2158 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2159 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2160 to favour printing of "-" branch hint when using the "y" bit.
2161 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2162
c2b1c275
AM		 21632019-04-05 Alan Modra <amodra@gmail.com>
2164
2165 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2166 opcode until first operand is output.
2167
aae9718e
PB		 21682019-04-04 Peter Bergner <bergner@linux.ibm.com>
2169
2170 PR gas/24349
2171 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2172 (valid_bo_post_v2): Add support for 'at' branch hints.
2173 (insert_bo): Only error on branch on ctr.
2174 (get_bo_hint_mask): New function.
2175 (insert_boe): Add new 'branch_taken' formal argument. Add support
2176 for inserting 'at' branch hints.
2177 (extract_boe): Add new 'branch_taken' formal argument. Add support
2178 for extracting 'at' branch hints.
2179 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2180 (BOE): Delete operand.
2181 (BOM, BOP): New operands.
2182 (RM): Update value.
2183 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2184 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2185 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2186 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2187 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2188 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2189 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2190 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2191 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2192 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2193 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2194 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2195 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2196 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2197 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2198 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2199 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2200 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2201 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2202 bttarl+>: New extended mnemonics.
2203
96a86c01
AM		 22042019-03-28 Alan Modra <amodra@gmail.com>
2205
2206 PR 24390
2207 * ppc-opc.c (BTF): Define.
2208 (powerpc_opcodes): Use for mtfsb*.
2209 * ppc-dis.c (print_insn_powerpc): Print fields with both
2210 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2211
796d6298
TC		 22122019-03-25 Tamar Christina <tamar.christina@arm.com>
2213
2214 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2215 (mapping_symbol_for_insn): Implement new algorithm.
2216 (print_insn): Remove duplicate code.
2217
60df3720
TC		 22182019-03-25 Tamar Christina <tamar.christina@arm.com>
2219
2220 * aarch64-dis.c (print_insn_aarch64):
2221 Implement override.
2222
51457761
TC		 22232019-03-25 Tamar Christina <tamar.christina@arm.com>
2224
2225 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2226 order.
2227
53b2f36b
TC		 22282019-03-25 Tamar Christina <tamar.christina@arm.com>
2229
2230 * aarch64-dis.c (last_stop_offset): New.
2231 (print_insn_aarch64): Use stop_offset.
2232
89199bb5
L		 22332019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2234
2235 PR gas/24359
2236 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2237 CPU_ANY_AVX2_FLAGS.
2238 * i386-init.h: Regenerated.
2239
97ed31ae
L		 22402019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2241
2242 PR gas/24348
2243 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2244 vmovdqu16, vmovdqu32 and vmovdqu64.
2245 * i386-tbl.h: Regenerated.
2246
0919bfe9
AK		 22472019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2248
2249 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2250 from vstrszb, vstrszh, and vstrszf.
2251
22522019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2253
2254 * s390-opc.txt: Add instruction descriptions.
2255
21820ebe
JW		 22562019-02-08 Jim Wilson <jimw@sifive.com>
2257
2258 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2259 <bne>: Likewise.
2260
f7dd2fb2
TC		 22612019-02-07 Tamar Christina <tamar.christina@arm.com>
2262
2263 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2264
6456d318
TC		 22652019-02-07 Tamar Christina <tamar.christina@arm.com>
2266
2267 PR binutils/23212
2268 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2269 * aarch64-opc.c (verify_elem_sd): New.
2270 (fields): Add FLD_sz entr.
2271 * aarch64-tbl.h (_SIMD_INSN): New.
2272 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2273 fmulx scalar and vector by element isns.
2274
4a83b610
NC		 22752019-02-07 Nick Clifton <nickc@redhat.com>
2276
2277 * po/sv.po: Updated Swedish translation.
2278
fc60b8c8
AK		 22792019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2280
2281 * s390-mkopc.c (main): Accept arch13 as cpu string.
2282 * s390-opc.c: Add new instruction formats and instruction opcode
2283 masks.
2284 * s390-opc.txt: Add new arch13 instructions.
2285
e10620d3
TC		 22862019-01-25 Sudakshina Das <sudi.das@arm.com>
2287
2288 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2289 (aarch64_opcode): Change encoding for stg, stzg
2290 st2g and st2zg.
2291 * aarch64-asm-2.c: Regenerated.
2292 * aarch64-dis-2.c: Regenerated.
2293 * aarch64-opc-2.c: Regenerated.
2294
20a4ca55
SD		 22952019-01-25 Sudakshina Das <sudi.das@arm.com>
2296
2297 * aarch64-asm-2.c: Regenerated.
2298 * aarch64-dis-2.c: Likewise.
2299 * aarch64-opc-2.c: Likewise.
2300 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2301
550fd7bf
SD		 23022019-01-25 Sudakshina Das <sudi.das@arm.com>
2303 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2304
2305 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2306 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2307 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2308 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2309 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2310 case for ldstgv_indexed.
2311 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2312 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2313 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2314 * aarch64-asm-2.c: Regenerated.
2315 * aarch64-dis-2.c: Regenerated.
2316 * aarch64-opc-2.c: Regenerated.
2317
d9938630
NC		 23182019-01-23 Nick Clifton <nickc@redhat.com>
2319
2320 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2321
375cd423
NC		 23222019-01-21 Nick Clifton <nickc@redhat.com>
2323
2324 * po/de.po: Updated German translation.
2325 * po/uk.po: Updated Ukranian translation.
2326
57299f48
CX		 23272019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2328 * mips-dis.c (mips_arch_choices): Fix typo in
2329 gs464, gs464e and gs264e descriptors.
2330
f48dfe41
NC		 23312019-01-19 Nick Clifton <nickc@redhat.com>
2332
2333 * configure: Regenerate.
2334 * po/opcodes.pot: Regenerate.
2335
f974f26c
NC		 23362018-06-24 Nick Clifton <nickc@redhat.com>
2337
2338 2.32 branch created.
2339
39f286cd
JD		 23402019-01-09 John Darrington <john@darrington.wattle.id.au>
2341
448b8ca8
JD		 2342 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2343 if it is null.
2344 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2345 zero.
2346
3107326d
AP		 23472019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2348
2349 * configure: Regenerate.
2350
7e9ca91e
AM		 23512019-01-07 Alan Modra <amodra@gmail.com>
2352
2353 * configure: Regenerate.
2354 * po/POTFILES.in: Regenerate.
2355
ef1ad42b
JD		 23562019-01-03 John Darrington <john@darrington.wattle.id.au>
2357
2358 * s12z-opc.c: New file.
2359 * s12z-opc.h: New file.
2360 * s12z-dis.c: Removed all code not directly related to display
2361 of instructions. Used the interface provided by the new files
2362 instead.
2363 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2364 * Makefile.in: Regenerate.
ef1ad42b 2365 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2366 * configure: Regenerate.
ef1ad42b 2367
82704155
AM		 23682019-01-01 Alan Modra <amodra@gmail.com>
2369
2370 Update year range in copyright notice of all files.
2371
d5c04e1b 2372For older changes see ChangeLog-2018
3499769a 2373\f
d5c04e1b 2374Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2375
2376Copying and distribution of this file, with or without modification,
2377are permitted in any medium without royalty provided the copyright
2378notice and this notice are preserved.
2379
2380Local Variables:
2381mode: change-log
2382left-margin: 8
2383fill-column: 74
2384version-control: never
2385End:
GDB Binutils - Deliverables
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