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x86: drop a few dead macros
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
219920a7
JB		 12019-07-01 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
4 Delete.
5
e395f487
L		 62019-06-27 H.J. Lu <hongjiu.lu@intel.com>
7
8 PR binutils/24719
9 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
10 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
11 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
12 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
13 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
14 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
15 EVEX_LEN_0F38C7_R_6_P_2_W_1.
16 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
17 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
18 PREFIX_EVEX_0F38C6_REG_6 entries.
19 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
20 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
21 EVEX_W_0F38C7_R_6_P_2 entries.
22 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
23 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
24 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
25 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
26 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
27 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
28 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
29
2b7bcc87
JB		 302019-06-27 Jan Beulich <jbeulich@suse.com>
31
32 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
33 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
34 VEX_LEN_0F2D_P_3): Delete.
35 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
36 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
37 (prefix_table): ... here.
38
c1dc7af5
JB		 392019-06-27 Jan Beulich <jbeulich@suse.com>
40
41 * i386-dis.c (Iq): Delete.
42 (Id): New.
43 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
44 TBM insns.
45 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
46 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
47 (OP_E_memory): Also honor needindex when deciding whether an
48 address size prefix needs printing.
49 (OP_I): Remove handling of q_mode. Add handling of d_mode.
50
d7560e2d
JW		 512019-06-26 Jim Wilson <jimw@sifive.com>
52
53 PR binutils/24739
54 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
55 Set info->display_endian to info->endian_code.
56
2c703856
JB		 572019-06-25 Jan Beulich <jbeulich@suse.com>
58
59 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
60 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
61 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
62 OPERAND_TYPE_ACC64 entries.
63 * i386-init.h: Re-generate.
64
54fbadc0
JB		 652019-06-25 Jan Beulich <jbeulich@suse.com>
66
67 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
68 Delete.
69 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
70 of dqa_mode.
71 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
72 entries here.
73 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
74 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
75
a280ab8e
JB		 762019-06-25 Jan Beulich <jbeulich@suse.com>
77
78 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
79 variables.
80
e1a1babd
JB		 812019-06-25 Jan Beulich <jbeulich@suse.com>
82
83 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
84 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
85 movnti.
d7560e2d 86 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 87 * i386-tbl.h: Re-generate.
88
b8364fa7
JB		 892019-06-25 Jan Beulich <jbeulich@suse.com>
90
91 * i386-opc.tbl (and): Mark Imm8S form for optimization.
92 * i386-tbl.h: Re-generate.
93
ad692897
L		 942019-06-21 H.J. Lu <hongjiu.lu@intel.com>
95
96 * i386-dis-evex.h: Break into ...
97 * i386-dis-evex-len.h: New file.
98 * i386-dis-evex-mod.h: Likewise.
99 * i386-dis-evex-prefix.h: Likewise.
100 * i386-dis-evex-reg.h: Likewise.
101 * i386-dis-evex-w.h: Likewise.
102 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
103 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
104 i386-dis-evex-mod.h.
105
f0a6222e
L		 1062019-06-19 H.J. Lu <hongjiu.lu@intel.com>
107
108 PR binutils/24700
109 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
110 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
111 EVEX_W_0F385B_P_2.
112 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
113 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
114 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
115 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
116 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
117 EVEX_LEN_0F385B_P_2_W_1.
118 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
119 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
120 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
121 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
122 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
123 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
124 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
125 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
126 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
127 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
128
6e1c90b7
L		 1292019-06-17 H.J. Lu <hongjiu.lu@intel.com>
130
131 PR binutils/24691
132 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
133 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
134 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
135 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
136 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
137 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
138 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
139 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
140 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
141 EVEX_LEN_0F3A43_P_2_W_1.
142 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
143 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
144 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
145 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
146 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
147 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
148 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
149 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
150 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
151 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
152 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
153 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
154
bcc5a6eb
NC		 1552019-06-14 Nick Clifton <nickc@redhat.com>
156
157 * po/fr.po; Updated French translation.
158
e4c4ac46
SH		 1592019-06-13 Stafford Horne <shorne@gmail.com>
160
161 * or1k-asm.c: Regenerated.
162 * or1k-desc.c: Regenerated.
163 * or1k-desc.h: Regenerated.
164 * or1k-dis.c: Regenerated.
165 * or1k-ibld.c: Regenerated.
166 * or1k-opc.c: Regenerated.
167 * or1k-opc.h: Regenerated.
168 * or1k-opinst.c: Regenerated.
169
a0e44ef5
PB		 1702019-06-12 Peter Bergner <bergner@linux.ibm.com>
171
172 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
173
12efd68d
L		 1742019-06-05 H.J. Lu <hongjiu.lu@intel.com>
175
176 PR binutils/24633
177 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
178 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
179 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
180 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
181 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
182 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
183 EVEX_LEN_0F3A1B_P_2_W_1.
184 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
185 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
186 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
187 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
188 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
189 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
190 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
191 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
192
63c6fc6c
L		 1932019-06-04 H.J. Lu <hongjiu.lu@intel.com>
194
195 PR binutils/24626
196 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
197 EVEX.vvvv when disassembling VEX and EVEX instructions.
198 (OP_VEX): Set vex.register_specifier to 0 after readding
199 vex.register_specifier.
200 (OP_Vex_2src_1): Likewise.
201 (OP_Vex_2src_2): Likewise.
202 (OP_LWP_E): Likewise.
203 (OP_EX_Vex): Don't check vex.register_specifier.
204 (OP_XMM_Vex): Likewise.
205
9186c494
L		 2062019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
207 Lili Cui <lili.cui@intel.com>
208
209 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
210 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
211 instructions.
212 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
213 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
214 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
215 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
216 (i386_cpu_flags): Add cpuavx512_vp2intersect.
217 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
218 * i386-init.h: Regenerated.
219 * i386-tbl.h: Likewise.
220
5d79adc4
L		 2212019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
222 Lili Cui <lili.cui@intel.com>
223
224 * doc/c-i386.texi: Document enqcmd.
225 * testsuite/gas/i386/enqcmd-intel.d: New file.
226 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
227 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
228 * testsuite/gas/i386/enqcmd.d: Likewise.
229 * testsuite/gas/i386/enqcmd.s: Likewise.
230 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
231 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
232 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
233 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
234 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
235 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
236 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
237 and x86-64-enqcmd.
238
a9d96ab9
AH		 2392019-06-04 Alan Hayward <alan.hayward@arm.com>
240
241 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
242
4f6d070a
AM		 2432019-06-03 Alan Modra <amodra@gmail.com>
244
245 * ppc-dis.c (prefix_opcd_indices): Correct size.
246
a2f4b66c
L		 2472019-05-28 H.J. Lu <hongjiu.lu@intel.com>
248
249 PR gas/24625
250 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
251 Disp8ShiftVL.
252 * i386-tbl.h: Regenerated.
253
405b5bd8
AM		 2542019-05-24 Alan Modra <amodra@gmail.com>
255
256 * po/POTFILES.in: Regenerate.
257
8acf1435
PB		 2582019-05-24 Peter Bergner <bergner@linux.ibm.com>
259 Alan Modra <amodra@gmail.com>
260
261 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
262 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
263 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
264 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
265 XTOP>): Define and add entries.
266 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
267 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
268 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
269 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
270
dd7efa79
PB		 2712019-05-24 Peter Bergner <bergner@linux.ibm.com>
272 Alan Modra <amodra@gmail.com>
273
274 * ppc-dis.c (ppc_opts): Add "future" entry.
275 (PREFIX_OPCD_SEGS): Define.
276 (prefix_opcd_indices): New array.
277 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
278 (lookup_prefix): New function.
279 (print_insn_powerpc): Handle 64-bit prefix instructions.
280 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
281 (PMRR, POWERXX): Define.
282 (prefix_opcodes): New instruction table.
283 (prefix_num_opcodes): New constant.
284
79472b45
JM		 2852019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
286
287 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
288 * configure: Regenerated.
289 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
290 and cpu/bpf.opc.
291 (HFILES): Add bpf-desc.h and bpf-opc.h.
292 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
293 bpf-ibld.c and bpf-opc.c.
294 (BPF_DEPS): Define.
295 * Makefile.in: Regenerated.
296 * disassemble.c (ARCH_bpf): Define.
297 (disassembler): Add case for bfd_arch_bpf.
298 (disassemble_init_for_target): Likewise.
299 (enum epbf_isa_attr): Define.
300 * disassemble.h: extern print_insn_bpf.
301 * bpf-asm.c: Generated.
302 * bpf-opc.h: Likewise.
303 * bpf-opc.c: Likewise.
304 * bpf-ibld.c: Likewise.
305 * bpf-dis.c: Likewise.
306 * bpf-desc.h: Likewise.
307 * bpf-desc.c: Likewise.
308
ba6cd17f
SD		 3092019-05-21 Sudakshina Das <sudi.das@arm.com>
310
311 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
312 and VMSR with the new operands.
313
e39c1607
SD		 3142019-05-21 Sudakshina Das <sudi.das@arm.com>
315
316 * arm-dis.c (enum mve_instructions): New enum
317 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
318 and cneg.
319 (mve_opcodes): New instructions as above.
320 (is_mve_encoding_conflict): Add cases for csinc, csinv,
321 csneg and csel.
322 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
323
23d00a41
SD		 3242019-05-21 Sudakshina Das <sudi.das@arm.com>
325
326 * arm-dis.c (emun mve_instructions): Updated for new instructions.
327 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
328 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
329 uqshl, urshrl and urshr.
330 (is_mve_okay_in_it): Add new instructions to TRUE list.
331 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
332 (print_insn_mve): Updated to accept new %j,
333 %<bitfield>m and %<bitfield>n patterns.
334
cd4797ee
FS		 3352019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
336
337 * mips-opc.c (mips_builtin_opcodes): Change source register
338 constraint for DAUI.
339
999b073b
NC		 3402019-05-20 Nick Clifton <nickc@redhat.com>
341
342 * po/fr.po: Updated French translation.
343
14b456f2
AV		 3442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
345 Michael Collison <michael.collison@arm.com>
346
347 * arm-dis.c (thumb32_opcodes): Add new instructions.
348 (enum mve_instructions): Likewise.
349 (enum mve_undefined): Add new reasons.
350 (is_mve_encoding_conflict): Handle new instructions.
351 (is_mve_undefined): Likewise.
352 (is_mve_unpredictable): Likewise.
353 (print_mve_undefined): Likewise.
354 (print_mve_size): Likewise.
355
f49bb598
AV		 3562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
357 Michael Collison <michael.collison@arm.com>
358
359 * arm-dis.c (thumb32_opcodes): Add new instructions.
360 (enum mve_instructions): Likewise.
361 (is_mve_encoding_conflict): Handle new instructions.
362 (is_mve_undefined): Likewise.
363 (is_mve_unpredictable): Likewise.
364 (print_mve_size): Likewise.
365
56858bea
AV		 3662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
367 Michael Collison <michael.collison@arm.com>
368
369 * arm-dis.c (thumb32_opcodes): Add new instructions.
370 (enum mve_instructions): Likewise.
371 (is_mve_encoding_conflict): Likewise.
372 (is_mve_unpredictable): Likewise.
373 (print_mve_size): Likewise.
374
e523f101
AV		 3752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
376 Michael Collison <michael.collison@arm.com>
377
378 * arm-dis.c (thumb32_opcodes): Add new instructions.
379 (enum mve_instructions): Likewise.
380 (is_mve_encoding_conflict): Handle new instructions.
381 (is_mve_undefined): Likewise.
382 (is_mve_unpredictable): Likewise.
383 (print_mve_size): Likewise.
384
66dcaa5d
AV		 3852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
386 Michael Collison <michael.collison@arm.com>
387
388 * arm-dis.c (thumb32_opcodes): Add new instructions.
389 (enum mve_instructions): Likewise.
390 (is_mve_encoding_conflict): Handle new instructions.
391 (is_mve_undefined): Likewise.
392 (is_mve_unpredictable): Likewise.
393 (print_mve_size): Likewise.
394 (print_insn_mve): Likewise.
395
d052b9b7
AV		 3962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
397 Michael Collison <michael.collison@arm.com>
398
399 * arm-dis.c (thumb32_opcodes): Add new instructions.
400 (print_insn_thumb32): Handle new instructions.
401
ed63aa17
AV		 4022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
403 Michael Collison <michael.collison@arm.com>
404
405 * arm-dis.c (enum mve_instructions): Add new instructions.
406 (enum mve_undefined): Add new reasons.
407 (is_mve_encoding_conflict): Handle new instructions.
408 (is_mve_undefined): Likewise.
409 (is_mve_unpredictable): Likewise.
410 (print_mve_undefined): Likewise.
411 (print_mve_size): Likewise.
412 (print_mve_shift_n): Likewise.
413 (print_insn_mve): Likewise.
414
897b9bbc
AV		 4152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
416 Michael Collison <michael.collison@arm.com>
417
418 * arm-dis.c (enum mve_instructions): Add new instructions.
419 (is_mve_encoding_conflict): Handle new instructions.
420 (is_mve_unpredictable): Likewise.
421 (print_mve_rotate): Likewise.
422 (print_mve_size): Likewise.
423 (print_insn_mve): Likewise.
424
1c8f2df8
AV		 4252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
426 Michael Collison <michael.collison@arm.com>
427
428 * arm-dis.c (enum mve_instructions): Add new instructions.
429 (is_mve_encoding_conflict): Handle new instructions.
430 (is_mve_unpredictable): Likewise.
431 (print_mve_size): Likewise.
432 (print_insn_mve): Likewise.
433
d3b63143
AV		 4342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
435 Michael Collison <michael.collison@arm.com>
436
437 * arm-dis.c (enum mve_instructions): Add new instructions.
438 (enum mve_undefined): Add new reasons.
439 (is_mve_encoding_conflict): Handle new instructions.
440 (is_mve_undefined): Likewise.
441 (is_mve_unpredictable): Likewise.
442 (print_mve_undefined): Likewise.
443 (print_mve_size): Likewise.
444 (print_insn_mve): Likewise.
445
14925797
AV		 4462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
447 Michael Collison <michael.collison@arm.com>
448
449 * arm-dis.c (enum mve_instructions): Add new instructions.
450 (is_mve_encoding_conflict): Handle new instructions.
451 (is_mve_undefined): Likewise.
452 (is_mve_unpredictable): Likewise.
453 (print_mve_size): Likewise.
454 (print_insn_mve): Likewise.
455
c507f10b
AV		 4562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
457 Michael Collison <michael.collison@arm.com>
458
459 * arm-dis.c (enum mve_instructions): Add new instructions.
460 (enum mve_unpredictable): Add new reasons.
461 (enum mve_undefined): Likewise.
462 (is_mve_okay_in_it): Handle new isntructions.
463 (is_mve_encoding_conflict): Likewise.
464 (is_mve_undefined): Likewise.
465 (is_mve_unpredictable): Likewise.
466 (print_mve_vmov_index): Likewise.
467 (print_simd_imm8): Likewise.
468 (print_mve_undefined): Likewise.
469 (print_mve_unpredictable): Likewise.
470 (print_mve_size): Likewise.
471 (print_insn_mve): Likewise.
472
bf0b396d
AV		 4732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
474 Michael Collison <michael.collison@arm.com>
475
476 * arm-dis.c (enum mve_instructions): Add new instructions.
477 (enum mve_unpredictable): Add new reasons.
478 (enum mve_undefined): Likewise.
479 (is_mve_encoding_conflict): Handle new instructions.
480 (is_mve_undefined): Likewise.
481 (is_mve_unpredictable): Likewise.
482 (print_mve_undefined): Likewise.
483 (print_mve_unpredictable): Likewise.
484 (print_mve_rounding_mode): Likewise.
485 (print_mve_vcvt_size): Likewise.
486 (print_mve_size): Likewise.
487 (print_insn_mve): Likewise.
488
ef1576a1
AV		 4892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
490 Michael Collison <michael.collison@arm.com>
491
492 * arm-dis.c (enum mve_instructions): Add new instructions.
493 (enum mve_unpredictable): Add new reasons.
494 (enum mve_undefined): Likewise.
495 (is_mve_undefined): Handle new instructions.
496 (is_mve_unpredictable): Likewise.
497 (print_mve_undefined): Likewise.
498 (print_mve_unpredictable): Likewise.
499 (print_mve_size): Likewise.
500 (print_insn_mve): Likewise.
501
aef6d006
AV		 5022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
503 Michael Collison <michael.collison@arm.com>
504
505 * arm-dis.c (enum mve_instructions): Add new instructions.
506 (enum mve_undefined): Add new reasons.
507 (insns): Add new instructions.
508 (is_mve_encoding_conflict):
509 (print_mve_vld_str_addr): New print function.
510 (is_mve_undefined): Handle new instructions.
511 (is_mve_unpredictable): Likewise.
512 (print_mve_undefined): Likewise.
513 (print_mve_size): Likewise.
514 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
515 (print_insn_mve): Handle new operands.
516
04d54ace
AV		 5172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
518 Michael Collison <michael.collison@arm.com>
519
520 * arm-dis.c (enum mve_instructions): Add new instructions.
521 (enum mve_unpredictable): Add new reasons.
522 (is_mve_encoding_conflict): Handle new instructions.
523 (is_mve_unpredictable): Likewise.
524 (mve_opcodes): Add new instructions.
525 (print_mve_unpredictable): Handle new reasons.
526 (print_mve_register_blocks): New print function.
527 (print_mve_size): Handle new instructions.
528 (print_insn_mve): Likewise.
529
9743db03
AV		 5302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
531 Michael Collison <michael.collison@arm.com>
532
533 * arm-dis.c (enum mve_instructions): Add new instructions.
534 (enum mve_unpredictable): Add new reasons.
535 (enum mve_undefined): Likewise.
536 (is_mve_encoding_conflict): Handle new instructions.
537 (is_mve_undefined): Likewise.
538 (is_mve_unpredictable): Likewise.
539 (coprocessor_opcodes): Move NEON VDUP from here...
540 (neon_opcodes): ... to here.
541 (mve_opcodes): Add new instructions.
542 (print_mve_undefined): Handle new reasons.
543 (print_mve_unpredictable): Likewise.
544 (print_mve_size): Handle new instructions.
545 (print_insn_neon): Handle vdup.
546 (print_insn_mve): Handle new operands.
547
143275ea
AV		 5482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
549 Michael Collison <michael.collison@arm.com>
550
551 * arm-dis.c (enum mve_instructions): Add new instructions.
552 (enum mve_unpredictable): Add new values.
553 (mve_opcodes): Add new instructions.
554 (vec_condnames): New array with vector conditions.
555 (mve_predicatenames): New array with predicate suffixes.
556 (mve_vec_sizename): New array with vector sizes.
557 (enum vpt_pred_state): New enum with vector predication states.
558 (struct vpt_block): New struct type for vpt blocks.
559 (vpt_block_state): Global struct to keep track of state.
560 (mve_extract_pred_mask): New helper function.
561 (num_instructions_vpt_block): Likewise.
562 (mark_outside_vpt_block): Likewise.
563 (mark_inside_vpt_block): Likewise.
564 (invert_next_predicate_state): Likewise.
565 (update_next_predicate_state): Likewise.
566 (update_vpt_block_state): Likewise.
567 (is_vpt_instruction): Likewise.
568 (is_mve_encoding_conflict): Add entries for new instructions.
569 (is_mve_unpredictable): Likewise.
570 (print_mve_unpredictable): Handle new cases.
571 (print_instruction_predicate): Likewise.
572 (print_mve_size): New function.
573 (print_vec_condition): New function.
574 (print_insn_mve): Handle vpt blocks and new print operands.
575
f08d8ce3
AV		 5762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
577
578 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
579 8, 14 and 15 for Armv8.1-M Mainline.
580
73cd51e5
AV		 5812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
582 Michael Collison <michael.collison@arm.com>
583
584 * arm-dis.c (enum mve_instructions): New enum.
585 (enum mve_unpredictable): Likewise.
586 (enum mve_undefined): Likewise.
587 (struct mopcode32): New struct.
588 (is_mve_okay_in_it): New function.
589 (is_mve_architecture): Likewise.
590 (arm_decode_field): Likewise.
591 (arm_decode_field_multiple): Likewise.
592 (is_mve_encoding_conflict): Likewise.
593 (is_mve_undefined): Likewise.
594 (is_mve_unpredictable): Likewise.
595 (print_mve_undefined): Likewise.
596 (print_mve_unpredictable): Likewise.
597 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
598 (print_insn_mve): New function.
599 (print_insn_thumb32): Handle MVE architecture.
600 (select_arm_features): Force thumb for Armv8.1-m Mainline.
601
3076e594
NC		 6022019-05-10 Nick Clifton <nickc@redhat.com>
603
604 PR 24538
605 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
606 end of the table prematurely.
607
387e7624
FS		 6082019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
609
610 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
611 macros for R6.
612
0067be51
AM		 6132019-05-11 Alan Modra <amodra@gmail.com>
614
615 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
616 when -Mraw is in effect.
617
42e6288f
MM		 6182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
619
620 * aarch64-dis-2.c: Regenerate.
621 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
622 (OP_SVE_BBB): New variant set.
623 (OP_SVE_DDDD): New variant set.
624 (OP_SVE_HHH): New variant set.
625 (OP_SVE_HHHU): New variant set.
626 (OP_SVE_SSS): New variant set.
627 (OP_SVE_SSSU): New variant set.
628 (OP_SVE_SHH): New variant set.
629 (OP_SVE_SBBU): New variant set.
630 (OP_SVE_DSS): New variant set.
631 (OP_SVE_DHHU): New variant set.
632 (OP_SVE_VMV_HSD_BHS): New variant set.
633 (OP_SVE_VVU_HSD_BHS): New variant set.
634 (OP_SVE_VVVU_SD_BH): New variant set.
635 (OP_SVE_VVVU_BHSD): New variant set.
636 (OP_SVE_VVV_QHD_DBS): New variant set.
637 (OP_SVE_VVV_HSD_BHS): New variant set.
638 (OP_SVE_VVV_HSD_BHS2): New variant set.
639 (OP_SVE_VVV_BHS_HSD): New variant set.
640 (OP_SVE_VV_BHS_HSD): New variant set.
641 (OP_SVE_VVV_SD): New variant set.
642 (OP_SVE_VVU_BHS_HSD): New variant set.
643 (OP_SVE_VZVV_SD): New variant set.
644 (OP_SVE_VZVV_BH): New variant set.
645 (OP_SVE_VZV_SD): New variant set.
646 (aarch64_opcode_table): Add sve2 instructions.
647
28ed815a
MM		 6482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
649
650 * aarch64-asm-2.c: Regenerated.
651 * aarch64-dis-2.c: Regenerated.
652 * aarch64-opc-2.c: Regenerated.
653 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
654 for SVE_SHLIMM_UNPRED_22.
655 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
656 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
657 operand.
658
fd1dc4a0
MM		 6592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
660
661 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
662 sve_size_tsz_bhs iclass encode.
663 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
664 sve_size_tsz_bhs iclass decode.
665
31e36ab3
MM		 6662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
667
668 * aarch64-asm-2.c: Regenerated.
669 * aarch64-dis-2.c: Regenerated.
670 * aarch64-opc-2.c: Regenerated.
671 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
672 for SVE_Zm4_11_INDEX.
673 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
674 (fields): Handle SVE_i2h field.
675 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
676 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
677
1be5f94f
MM		 6782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
679
680 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
681 sve_shift_tsz_bhsd iclass encode.
682 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
683 sve_shift_tsz_bhsd iclass decode.
684
3c17238b
MM		 6852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
686
687 * aarch64-asm-2.c: Regenerated.
688 * aarch64-dis-2.c: Regenerated.
689 * aarch64-opc-2.c: Regenerated.
690 * aarch64-asm.c (aarch64_ins_sve_shrimm):
691 (aarch64_encode_variant_using_iclass): Handle
692 sve_shift_tsz_hsd iclass encode.
693 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
694 sve_shift_tsz_hsd iclass decode.
695 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
696 for SVE_SHRIMM_UNPRED_22.
697 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
698 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
699 operand.
700
cd50a87a
MM		 7012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
702
703 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
704 sve_size_013 iclass encode.
705 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
706 sve_size_013 iclass decode.
707
3c705960
MM		 7082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
709
710 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
711 sve_size_bh iclass encode.
712 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
713 sve_size_bh iclass decode.
714
0a57e14f
MM		 7152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
716
717 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
718 sve_size_sd2 iclass encode.
719 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
720 sve_size_sd2 iclass decode.
721 * aarch64-opc.c (fields): Handle SVE_sz2 field.
722 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
723
c469c864
MM		 7242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
725
726 * aarch64-asm-2.c: Regenerated.
727 * aarch64-dis-2.c: Regenerated.
728 * aarch64-opc-2.c: Regenerated.
729 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
730 for SVE_ADDR_ZX.
731 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
732 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
733
116adc27
MM		 7342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
735
736 * aarch64-asm-2.c: Regenerated.
737 * aarch64-dis-2.c: Regenerated.
738 * aarch64-opc-2.c: Regenerated.
739 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
740 for SVE_Zm3_11_INDEX.
741 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
742 (fields): Handle SVE_i3l and SVE_i3h2 fields.
743 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
744 fields.
745 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
746
3bd82c86
MM		 7472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
748
749 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
750 sve_size_hsd2 iclass encode.
751 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
752 sve_size_hsd2 iclass decode.
753 * aarch64-opc.c (fields): Handle SVE_size field.
754 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
755
adccc507
MM		 7562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
757
758 * aarch64-asm-2.c: Regenerated.
759 * aarch64-dis-2.c: Regenerated.
760 * aarch64-opc-2.c: Regenerated.
761 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
762 for SVE_IMM_ROT3.
763 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
764 (fields): Handle SVE_rot3 field.
765 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
766 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
767
5cd99750
MM		 7682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
769
770 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
771 instructions.
772
7ce2460a
MM		 7732019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
774
775 * aarch64-tbl.h
776 (aarch64_feature_sve2, aarch64_feature_sve2aes,
777 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
778 aarch64_feature_sve2bitperm): New feature sets.
779 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
780 for feature set addresses.
781 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
782 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
783
41cee089
FS		 7842019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
785 Faraz Shahbazker <fshahbazker@wavecomp.com>
786
787 * mips-dis.c (mips_calculate_combination_ases): Add ISA
788 argument and set ASE_EVA_R6 appropriately.
789 (set_default_mips_dis_options): Pass ISA to above.
790 (parse_mips_dis_option): Likewise.
791 * mips-opc.c (EVAR6): New macro.
792 (mips_builtin_opcodes): Add llwpe, scwpe.
793
b83b4b13
SD		 7942019-05-01 Sudakshina Das <sudi.das@arm.com>
795
796 * aarch64-asm-2.c: Regenerated.
797 * aarch64-dis-2.c: Regenerated.
798 * aarch64-opc-2.c: Regenerated.
799 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
800 AARCH64_OPND_TME_UIMM16.
801 (aarch64_print_operand): Likewise.
802 * aarch64-tbl.h (QL_IMM_NIL): New.
803 (TME): New.
804 (_TME_INSN): New.
805 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
806
4a90ce95
JD		 8072019-04-29 John Darrington <john@darrington.wattle.id.au>
808
809 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
810
a45328b9
AB		 8112019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
812 Faraz Shahbazker <fshahbazker@wavecomp.com>
813
814 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
815
d10be0cb
JD		 8162019-04-24 John Darrington <john@darrington.wattle.id.au>
817
818 * s12z-opc.h: Add extern "C" bracketing to help
819 users who wish to use this interface in c++ code.
820
a679f24e
JD		 8212019-04-24 John Darrington <john@darrington.wattle.id.au>
822
823 * s12z-opc.c (bm_decode): Handle bit map operations with the
824 "reserved0" mode.
825
32c36c3c
AV		 8262019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
827
828 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
829 specifier. Add entries for VLDR and VSTR of system registers.
830 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
831 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
832 of %J and %K format specifier.
833
efd6b359
AV		 8342019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
835
836 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
837 Add new entries for VSCCLRM instruction.
838 (print_insn_coprocessor): Handle new %C format control code.
839
6b0dd094
AV		 8402019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
841
842 * arm-dis.c (enum isa): New enum.
843 (struct sopcode32): New structure.
844 (coprocessor_opcodes): change type of entries to struct sopcode32 and
845 set isa field of all current entries to ANY.
846 (print_insn_coprocessor): Change type of insn to struct sopcode32.
847 Only match an entry if its isa field allows the current mode.
848
4b5a202f
AV		 8492019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
850
851 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
852 CLRM.
853 (print_insn_thumb32): Add logic to print %n CLRM register list.
854
60f993ce
AV		 8552019-04-15 Sudakshina Das <sudi.das@arm.com>
856
857 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
858 and %Q patterns.
859
f6b2b12d
AV		 8602019-04-15 Sudakshina Das <sudi.das@arm.com>
861
862 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
863 (print_insn_thumb32): Edit the switch case for %Z.
864
1889da70
AV		 8652019-04-15 Sudakshina Das <sudi.das@arm.com>
866
867 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
868
65d1bc05
AV		 8692019-04-15 Sudakshina Das <sudi.das@arm.com>
870
871 * arm-dis.c (thumb32_opcodes): New instruction bfl.
872
1caf72a5
AV		 8732019-04-15 Sudakshina Das <sudi.das@arm.com>
874
875 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
876
f1c7f421
AV		 8772019-04-15 Sudakshina Das <sudi.das@arm.com>
878
879 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
880 Arm register with r13 and r15 unpredictable.
881 (thumb32_opcodes): New instructions for bfx and bflx.
882
4389b29a
AV		 8832019-04-15 Sudakshina Das <sudi.das@arm.com>
884
885 * arm-dis.c (thumb32_opcodes): New instructions for bf.
886
e5d6e09e
AV		 8872019-04-15 Sudakshina Das <sudi.das@arm.com>
888
889 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
890
e12437dc
AV		 8912019-04-15 Sudakshina Das <sudi.das@arm.com>
892
893 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
894
031254f2
AV		 8952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
896
897 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
898
e5a557ac
JD		 8992019-04-12 John Darrington <john@darrington.wattle.id.au>
900
901 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
902 "optr". ("operator" is a reserved word in c++).
903
bd7ceb8d
SD		 9042019-04-11 Sudakshina Das <sudi.das@arm.com>
905
906 * aarch64-opc.c (aarch64_print_operand): Add case for
907 AARCH64_OPND_Rt_SP.
908 (verify_constraints): Likewise.
909 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
910 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
911 to accept Rt|SP as first operand.
912 (AARCH64_OPERANDS): Add new Rt_SP.
913 * aarch64-asm-2.c: Regenerated.
914 * aarch64-dis-2.c: Regenerated.
915 * aarch64-opc-2.c: Regenerated.
916
e54010f1
SD		 9172019-04-11 Sudakshina Das <sudi.das@arm.com>
918
919 * aarch64-asm-2.c: Regenerated.
920 * aarch64-dis-2.c: Likewise.
921 * aarch64-opc-2.c: Likewise.
922 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
923
7e96e219
RS		 9242019-04-09 Robert Suchanek <robert.suchanek@mips.com>
925
926 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
927
6f2791d5
L		 9282019-04-08 H.J. Lu <hongjiu.lu@intel.com>
929
930 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
931 * i386-init.h: Regenerated.
932
e392bad3
AM		 9332019-04-07 Alan Modra <amodra@gmail.com>
934
935 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
936 op_separator to control printing of spaces, comma and parens
937 rather than need_comma, need_paren and spaces vars.
938
dffaa15c
AM		 9392019-04-07 Alan Modra <amodra@gmail.com>
940
941 PR 24421
942 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
943 (print_insn_neon, print_insn_arm): Likewise.
944
d6aab7a1
XG		 9452019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
946
947 * i386-dis-evex.h (evex_table): Updated to support BF16
948 instructions.
949 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
950 and EVEX_W_0F3872_P_3.
951 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
952 (cpu_flags): Add bitfield for CpuAVX512_BF16.
953 * i386-opc.h (enum): Add CpuAVX512_BF16.
954 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
955 * i386-opc.tbl: Add AVX512 BF16 instructions.
956 * i386-init.h: Regenerated.
957 * i386-tbl.h: Likewise.
958
66e85460
AM		 9592019-04-05 Alan Modra <amodra@gmail.com>
960
961 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
962 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
963 to favour printing of "-" branch hint when using the "y" bit.
964 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
965
c2b1c275
AM		 9662019-04-05 Alan Modra <amodra@gmail.com>
967
968 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
969 opcode until first operand is output.
970
aae9718e
PB		 9712019-04-04 Peter Bergner <bergner@linux.ibm.com>
972
973 PR gas/24349
974 * ppc-opc.c (valid_bo_pre_v2): Add comments.
975 (valid_bo_post_v2): Add support for 'at' branch hints.
976 (insert_bo): Only error on branch on ctr.
977 (get_bo_hint_mask): New function.
978 (insert_boe): Add new 'branch_taken' formal argument. Add support
979 for inserting 'at' branch hints.
980 (extract_boe): Add new 'branch_taken' formal argument. Add support
981 for extracting 'at' branch hints.
982 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
983 (BOE): Delete operand.
984 (BOM, BOP): New operands.
985 (RM): Update value.
986 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
987 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
988 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
989 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
990 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
991 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
992 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
993 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
994 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
995 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
996 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
997 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
998 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
999 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1000 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1001 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1002 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1003 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1004 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1005 bttarl+>: New extended mnemonics.
1006
96a86c01
AM		 10072019-03-28 Alan Modra <amodra@gmail.com>
1008
1009 PR 24390
1010 * ppc-opc.c (BTF): Define.
1011 (powerpc_opcodes): Use for mtfsb*.
1012 * ppc-dis.c (print_insn_powerpc): Print fields with both
1013 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1014
796d6298
TC		 10152019-03-25 Tamar Christina <tamar.christina@arm.com>
1016
1017 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1018 (mapping_symbol_for_insn): Implement new algorithm.
1019 (print_insn): Remove duplicate code.
1020
60df3720
TC		 10212019-03-25 Tamar Christina <tamar.christina@arm.com>
1022
1023 * aarch64-dis.c (print_insn_aarch64):
1024 Implement override.
1025
51457761
TC		 10262019-03-25 Tamar Christina <tamar.christina@arm.com>
1027
1028 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1029 order.
1030
53b2f36b
TC		 10312019-03-25 Tamar Christina <tamar.christina@arm.com>
1032
1033 * aarch64-dis.c (last_stop_offset): New.
1034 (print_insn_aarch64): Use stop_offset.
1035
89199bb5
L		 10362019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1037
1038 PR gas/24359
1039 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1040 CPU_ANY_AVX2_FLAGS.
1041 * i386-init.h: Regenerated.
1042
97ed31ae
L		 10432019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1044
1045 PR gas/24348
1046 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1047 vmovdqu16, vmovdqu32 and vmovdqu64.
1048 * i386-tbl.h: Regenerated.
1049
0919bfe9
AK		 10502019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1051
1052 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1053 from vstrszb, vstrszh, and vstrszf.
1054
10552019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1056
1057 * s390-opc.txt: Add instruction descriptions.
1058
21820ebe
JW		 10592019-02-08 Jim Wilson <jimw@sifive.com>
1060
1061 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1062 <bne>: Likewise.
1063
f7dd2fb2
TC		 10642019-02-07 Tamar Christina <tamar.christina@arm.com>
1065
1066 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1067
6456d318
TC		 10682019-02-07 Tamar Christina <tamar.christina@arm.com>
1069
1070 PR binutils/23212
1071 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1072 * aarch64-opc.c (verify_elem_sd): New.
1073 (fields): Add FLD_sz entr.
1074 * aarch64-tbl.h (_SIMD_INSN): New.
1075 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1076 fmulx scalar and vector by element isns.
1077
4a83b610
NC		 10782019-02-07 Nick Clifton <nickc@redhat.com>
1079
1080 * po/sv.po: Updated Swedish translation.
1081
fc60b8c8
AK		 10822019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1083
1084 * s390-mkopc.c (main): Accept arch13 as cpu string.
1085 * s390-opc.c: Add new instruction formats and instruction opcode
1086 masks.
1087 * s390-opc.txt: Add new arch13 instructions.
1088
e10620d3
TC		 10892019-01-25 Sudakshina Das <sudi.das@arm.com>
1090
1091 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1092 (aarch64_opcode): Change encoding for stg, stzg
1093 st2g and st2zg.
1094 * aarch64-asm-2.c: Regenerated.
1095 * aarch64-dis-2.c: Regenerated.
1096 * aarch64-opc-2.c: Regenerated.
1097
20a4ca55
SD		 10982019-01-25 Sudakshina Das <sudi.das@arm.com>
1099
1100 * aarch64-asm-2.c: Regenerated.
1101 * aarch64-dis-2.c: Likewise.
1102 * aarch64-opc-2.c: Likewise.
1103 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1104
550fd7bf
SD		 11052019-01-25 Sudakshina Das <sudi.das@arm.com>
1106 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1107
1108 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1109 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1110 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1111 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1112 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1113 case for ldstgv_indexed.
1114 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1115 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1116 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1117 * aarch64-asm-2.c: Regenerated.
1118 * aarch64-dis-2.c: Regenerated.
1119 * aarch64-opc-2.c: Regenerated.
1120
d9938630
NC		 11212019-01-23 Nick Clifton <nickc@redhat.com>
1122
1123 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1124
375cd423
NC		 11252019-01-21 Nick Clifton <nickc@redhat.com>
1126
1127 * po/de.po: Updated German translation.
1128 * po/uk.po: Updated Ukranian translation.
1129
57299f48
CX		 11302019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1131 * mips-dis.c (mips_arch_choices): Fix typo in
1132 gs464, gs464e and gs264e descriptors.
1133
f48dfe41
NC		 11342019-01-19 Nick Clifton <nickc@redhat.com>
1135
1136 * configure: Regenerate.
1137 * po/opcodes.pot: Regenerate.
1138
f974f26c
NC		 11392018-06-24 Nick Clifton <nickc@redhat.com>
1140
1141 2.32 branch created.
1142
39f286cd
JD		 11432019-01-09 John Darrington <john@darrington.wattle.id.au>
1144
448b8ca8
JD		 1145 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1146 if it is null.
1147 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1148 zero.
1149
3107326d
AP		 11502019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1151
1152 * configure: Regenerate.
1153
7e9ca91e
AM		 11542019-01-07 Alan Modra <amodra@gmail.com>
1155
1156 * configure: Regenerate.
1157 * po/POTFILES.in: Regenerate.
1158
ef1ad42b
JD		 11592019-01-03 John Darrington <john@darrington.wattle.id.au>
1160
1161 * s12z-opc.c: New file.
1162 * s12z-opc.h: New file.
1163 * s12z-dis.c: Removed all code not directly related to display
1164 of instructions. Used the interface provided by the new files
1165 instead.
1166 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1167 * Makefile.in: Regenerate.
ef1ad42b 1168 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1169 * configure: Regenerate.
ef1ad42b 1170
82704155
AM		 11712019-01-01 Alan Modra <amodra@gmail.com>
1172
1173 Update year range in copyright notice of all files.
1174
d5c04e1b 1175For older changes see ChangeLog-2018
3499769a 1176\f
d5c04e1b 1177Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1178
1179Copying and distribution of this file, with or without modification,
1180are permitted in any medium without royalty provided the copyright
1181notice and this notice are preserved.
1182
1183Local Variables:
1184mode: change-log
1185left-margin: 8
1186fill-column: 74
1187version-control: never
1188End:
GDB Binutils - Deliverables
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